sim/testsuite/sim/bfin/c_progctrl_raise_rt_i_n.S

   1 //Original:/proj/frio/dv/testcases/core/c_progctrl_raise_rt_i_n/c_progctrl_raise_rt_i_n.dsp
   2 // Spec Reference: progctrl raise rti rtn
   3 # mach: bfin
   4 # sim: --environment operating
   5
   6 #include "test.h"
   7 .include "testutils.inc"
   8 start
   9
  10 include(std.inc)
  11 include(selfcheck.inc)
  12 include(gen_int.inc)
  13 INIT_R_REGS(0);
  14 INIT_P_REGS(0);
  15 INIT_I_REGS(0);     // initialize the dsp address regs
  16 INIT_M_REGS(0);
  17 INIT_L_REGS(0);
  18 INIT_B_REGS(0);
  19 CHECK_INIT(p5, 0xe0000000);
  20
  21 #ifndef STACKSIZE
  22 #define STACKSIZE 0x10
  23 #endif
  24 #ifndef EVT
  25 #define EVT  0xFFE02000
  26 #endif
  27 #ifndef EVT15
  28 #define EVT15  0xFFE0203C
  29 #endif
  30 #ifndef EVT_OVERRIDE
  31 #define EVT_OVERRIDE 0xFFE02100
  32 #endif
  33 #ifndef ITABLE
  34 #define ITABLE 0xF0000000
  35 #endif
  36
  37 GEN_INT_INIT(ITABLE) // set location for interrupt table
  38
  39 //
  40 // Reset/Bootstrap Code
  41 //   (Here we should set the processor operating modes, initialize registers,
  42 //    etc.)
  43 //
  44
  45 BOOT:
  46
  47
  48 LD32_LABEL(sp, KSTACK);   // setup the stack pointer
  49 FP = SP;        // and frame pointer
  50
  51 LD32(p0, EVT);      // Setup Event Vectors and Handlers
  52 LD32_LABEL(r0, EHANDLE);  // Emulation Handler (Int0)
  53     [ P0 ++ ] = R0;
  54
  55 LD32_LABEL(r0, RHANDLE);  // Reset Handler (Int1)
  56     [ P0 ++ ] = R0;
  57
  58 LD32_LABEL(r0, NHANDLE);  // NMI Handler (Int2)
  59     [ P0 ++ ] = R0;
  60
  61 LD32_LABEL(r0, XHANDLE);  // Exception Handler (Int3)
  62     [ P0 ++ ] = R0;
  63
  64     [ P0 ++ ] = R0;        // IVT4 not used
  65
  66 LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
  67     [ P0 ++ ] = R0;
  68
  69 LD32_LABEL(r0, THANDLE);  // Timer Handler (Int6)
  70     [ P0 ++ ] = R0;
  71
  72 LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
  73     [ P0 ++ ] = R0;
  74
  75 LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
  76     [ P0 ++ ] = R0;
  77
  78 LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
  79     [ P0 ++ ] = R0;
  80
  81 LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
  82     [ P0 ++ ] = R0;
  83
  84 LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
  85     [ P0 ++ ] = R0;
  86
  87 LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
  88     [ P0 ++ ] = R0;
  89
  90 LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
  91     [ P0 ++ ] = R0;
  92
  93 LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
  94     [ P0 ++ ] = R0;
  95
  96 LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
  97     [ P0 ++ ] = R0;
  98
  99 LD32(p0, EVT_OVERRIDE);
 100     R0 = 0;
 101     [ P0 ++ ] = R0;
 102     R0 = -1;     // Change this to mask interrupts (*)
 103     [ P0 ] = R0;   // IMASK
 104
 105 DUMMY:
 106
 107     R0 = 0 (Z);
 108
 109 LT0 = r0;       // set loop counters to something deterministic
 110 LB0 = r0;
 111 LC0 = r0;
 112 LT1 = r0;
 113 LB1 = r0;
 114 LC1 = r0;
 115
 116 ASTAT = r0;     // reset other internal regs
 117
 118 // The following code sets up the test for running in USER mode
 119
 120 LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
 121                         // ReturnFromInterrupt (RTI)
 122 RETI = r0;      // We need to load the return address
 123
 124 // Comment the following line for a USER Mode test
 125
 126 JUMP    STARTSUP;   // jump to code start for SUPERVISOR mode
 127
 128 RTI;
 129
 130 STARTSUP:
 131 LD32_LABEL(p1, BEGIN);
 132
 133 LD32(p0, EVT15);
 134     [ P0 ] = P1;   // IVG15 (General) handler (Int 15) load with start
 135
 136 RAISE 15;       // after we RTI, INT 15 should be taken
 137
 138 NOP;    // Workaround for Bug 217
 139 RTI;
 140
 141 //
 142 // The Main Program
 143 //
 144 STARTUSER:
 145 LD32_LABEL(sp, USTACK);   // setup the stack pointer
 146 FP = SP;            // set frame pointer
 147 JUMP BEGIN;
 148
 149 //*********************************************************************
 150
 151 BEGIN:
 152
 153                 // COMMENT the following line for USER MODE tests
 154     [ -- SP ] = RETI;  // enable interrupts in supervisor mode
 155
 156                 // **** YOUR CODE GOES HERE ****
 157
 158
 159
 160     // PUT YOUR TEST HERE!
 161                 // Can't Raise 0, 3, or 4
 162                 // Raise 1 requires some intelligence so the test
 163                 //  doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD)
 164 RAISE 2;    // RTN
 165 RAISE 5;    // RTI
 166 RAISE 6;    // RTI
 167 RAISE 7;    // RTI
 168 RAISE 8;    // RTI
 169 RAISE 9;    // RTI
 170 RAISE 10;   // RTI
 171 RAISE 11;   // RTI
 172 RAISE 12;   // RTI
 173 RAISE 13;   // RTI
 174 RAISE 14;   // RTI
 175 RAISE 15;   // RTI
 176
 177 CHECKREG(r0, 0x0000000B);
 178 CHECKREG(r1, 0x0000000C);
 179 CHECKREG(r2, 0x0000000D);
 180 CHECKREG(r3, 0x0000000E);
 181 CHECKREG(r4, 0x00000007);
 182 CHECKREG(r5, 0x00000008);
 183 CHECKREG(r6, 0x00000009);
 184 CHECKREG(r7, 0x0000000A);
 185 R0 = I0;
 186 R1 = I1;
 187 R2 = I2;
 188 R3 = I3;
 189 R4 = M0;
 190 CHECKREG(r0, 0x00000002);
 191 CHECKREG(r1, 0x00000000);
 192 CHECKREG(r2, 0x00000005);
 193 CHECKREG(r3, 0x00000006);
 194 CHECKREG(r4, 0x00000007);
 195
 196
 197 END:
 198 dbg_pass;            // End the test
 199
 200 //*********************************************************************
 201
 202 //
 203 // Handlers for Events
 204 //
 205
 206 EHANDLE:            // Emulation Handler 0
 207 RTE;
 208
 209 RHANDLE:            // Reset Handler 1
 210 RTI;
 211
 212 NHANDLE:            // NMI Handler 2
 213     R0 = 2;
 214 RTN;
 215
 216 XHANDLE:            // Exception Handler 3
 217     R1 = 3;
 218 RTX;
 219
 220 HWHANDLE:           // HW Error Handler 5
 221     R2 = 5;
 222 RTI;
 223
 224 THANDLE:            // Timer Handler 6
 225     R3 = 6;
 226 RTI;
 227
 228 I7HANDLE:           // IVG 7 Handler
 229     R4 = 7;
 230 RTI;
 231
 232 I8HANDLE:           // IVG 8 Handler
 233     R5 = 8;
 234 RTI;
 235
 236 I9HANDLE:           // IVG 9 Handler
 237     R6 = 9;
 238 RTI;
 239
 240 I10HANDLE:          // IVG 10 Handler
 241     R7 = 10;
 242 RTI;
 243
 244 I11HANDLE:          // IVG 11 Handler
 245     I0 = R0;
 246     I1 = R1;
 247     I2 = R2;
 248     I3 = R3;
 249     M0 = R4;
 250     R0 = 11;
 251 RTI;
 252
 253 I12HANDLE:          // IVG 12 Handler
 254     R1 = 12;
 255 RTI;
 256
 257 I13HANDLE:          // IVG 13 Handler
 258     R2 = 13;
 259 RTI;
 260
 261 I14HANDLE:          // IVG 14 Handler
 262     R3 = 14;
 263 RTI;
 264
 265 I15HANDLE:          // IVG 15 Handler
 266     R4 = 15;
 267 RTI;
 268
 269 NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
 270
 271 //
 272 // Data Segment
 273 //
 274
 275 .data
 276 DATA:
 277     .space (0x10);
 278
 279 // Stack Segments (Both Kernel and User)
 280
 281     .space (STACKSIZE);
 282 KSTACK:
 283
 284     .space (STACKSIZE);
 285 USTACK: