sim/testsuite/sim/bfin/c_pushpopmultiple_dreg.s

   1 //Original:/testcases/core/c_pushpopmultiple_dreg/c_pushpopmultiple_dreg.dsp
   2 // Spec Reference: pushpopmultiple dreg
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8         FP = SP;
   9
  10         imm32 r0, 0x00000000;
  11         ASTAT = r0;
  12
  13         R0 = 0x01;
  14         R1 = 0x02;
  15         R2 = 0x03;
  16         R3 = 0x04;
  17         R4 = 0x05;
  18         R5 = 0x06;
  19         R6 = 0x07;
  20         R7 = 0x08;
  21         [ -- SP ] = ( R7:0 );
  22         R0 = 0;
  23         R1 = 0;
  24         R2 = 0;
  25         R3 = 0;
  26         R4 = 0;
  27         R5 = 0;
  28         R6 = 0;
  29         R7 = 0;
  30         ( R7:0 ) = [ SP ++ ];
  31         CHECKREG r0, 0x00000001;
  32         CHECKREG r1, 0x00000002;
  33         CHECKREG r2, 0x00000003;
  34         CHECKREG r3, 0x00000004;
  35         CHECKREG r4, 0x00000005;
  36         CHECKREG r5, 0x00000006;
  37         CHECKREG r6, 0x00000007;
  38         CHECKREG r7, 0x00000008;
  39
  40         R1 = 0x12;
  41         R2 = 0x13;
  42         R3 = 0x14;
  43         R4 = 0x15;
  44         R5 = 0x16;
  45         R6 = 0x17;
  46         R7 = 0x18;
  47         [ -- SP ] = ( R7:1 );
  48         R1 = 0;
  49         R2 = 0;
  50         R3 = 0;
  51         R4 = 0;
  52         R5 = 0;
  53         R6 = 0;
  54         R7 = 0;
  55         ( R7:1 ) = [ SP ++ ];
  56         CHECKREG r0, 0x00000001;
  57         CHECKREG r1, 0x00000012;
  58         CHECKREG r2, 0x00000013;
  59         CHECKREG r3, 0x00000014;
  60         CHECKREG r4, 0x00000015;
  61         CHECKREG r5, 0x00000016;
  62         CHECKREG r6, 0x00000017;
  63         CHECKREG r7, 0x00000018;
  64
  65         R2 = 0x23;
  66         R3 = 0x24;
  67         R4 = 0x25;
  68         R5 = 0x26;
  69         R6 = 0x27;
  70         R7 = 0x28;
  71         [ -- SP ] = ( R7:2 );
  72         R2 = 0;
  73         R3 = 0;
  74         R4 = 0;
  75         R5 = 0;
  76         R6 = 0;
  77         R7 = 0;
  78         ( R7:2 ) = [ SP ++ ];
  79         CHECKREG r0, 0x00000001;
  80         CHECKREG r1, 0x00000012;
  81         CHECKREG r2, 0x00000023;
  82         CHECKREG r3, 0x00000024;
  83         CHECKREG r4, 0x00000025;
  84         CHECKREG r5, 0x00000026;
  85         CHECKREG r6, 0x00000027;
  86         CHECKREG r7, 0x00000028;
  87
  88         R3 = 0x34;
  89         R4 = 0x35;
  90         R5 = 0x36;
  91         R6 = 0x37;
  92         R7 = 0x38;
  93         [ -- SP ] = ( R7:3 );
  94         R3 = 0;
  95         R4 = 0;
  96         R5 = 0;
  97         R6 = 0;
  98         R7 = 0;
  99         ( R7:3 ) = [ SP ++ ];
 100         CHECKREG r0, 0x00000001;
 101         CHECKREG r1, 0x00000012;
 102         CHECKREG r2, 0x00000023;
 103         CHECKREG r3, 0x00000034;
 104         CHECKREG r4, 0x00000035;
 105         CHECKREG r5, 0x00000036;
 106         CHECKREG r6, 0x00000037;
 107         CHECKREG r7, 0x00000038;
 108
 109         R4 = 0x45 (X);
 110         R5 = 0x46 (X);
 111         R6 = 0x47 (X);
 112         R7 = 0x48 (X);
 113         [ -- SP ] = ( R7:4 );
 114         R4 = 0;
 115         R5 = 0;
 116         R6 = 0;
 117         R7 = 0;
 118         ( R7:4 ) = [ SP ++ ];
 119         CHECKREG r0, 0x00000001;
 120         CHECKREG r1, 0x00000012;
 121         CHECKREG r2, 0x00000023;
 122         CHECKREG r3, 0x00000034;
 123         CHECKREG r4, 0x00000045;
 124         CHECKREG r5, 0x00000046;
 125         CHECKREG r6, 0x00000047;
 126         CHECKREG r7, 0x00000048;
 127
 128         R5 = 0x56 (X);
 129         R6 = 0x57 (X);
 130         R7 = 0x58 (X);
 131         [ -- SP ] = ( R7:5 );
 132         R5 = 0;
 133         R6 = 0;
 134         R7 = 0;
 135         ( R7:5 ) = [ SP ++ ];
 136         CHECKREG r0, 0x00000001;
 137         CHECKREG r1, 0x00000012;
 138         CHECKREG r2, 0x00000023;
 139         CHECKREG r3, 0x00000034;
 140         CHECKREG r4, 0x00000045;
 141         CHECKREG r5, 0x00000056;
 142         CHECKREG r6, 0x00000057;
 143         CHECKREG r7, 0x00000058;
 144
 145         R6 = 0x67 (X);
 146         R7 = 0x68 (X);
 147         [ -- SP ] = ( R7:6 );
 148         R6 = 0;
 149         R7 = 0;
 150         ( R7:6 ) = [ SP ++ ];
 151         CHECKREG r0, 0x00000001;
 152         CHECKREG r1, 0x00000012;
 153         CHECKREG r2, 0x00000023;
 154         CHECKREG r3, 0x00000034;
 155         CHECKREG r4, 0x00000045;
 156         CHECKREG r5, 0x00000056;
 157         CHECKREG r6, 0x00000067;
 158         CHECKREG r7, 0x00000068;
 159
 160         R7 = 0x78 (X);
 161         [ -- SP ] = ( R7:7 );
 162         R7 = 0;
 163         ( R7:7 ) = [ SP ++ ];
 164         CHECKREG r0, 0x00000001;
 165         CHECKREG r1, 0x00000012;
 166         CHECKREG r2, 0x00000023;
 167         CHECKREG r3, 0x00000034;
 168         CHECKREG r4, 0x00000045;
 169         CHECKREG r5, 0x00000056;
 170         CHECKREG r6, 0x00000067;
 171         CHECKREG r7, 0x00000078;
 172
 173         pass