sim/testsuite/sim/bfin/c_seq_ex2_raise_mmr_mvpop.S

   1 //Original:/proj/frio/dv/testcases/core/c_seq_ex2_raise_mmr_mvpop/c_seq_ex2_raise_mmr_mvpop.dsp
   2 // Spec Reference: sequencer stage ex2  (raise+  mmr + regmv + pushpopmultiple)
   3 # mach: bfin
   4 # sim: --environment operating
   5
   6 #include "test.h"
   7 .include "testutils.inc"
   8 start
   9
  10 include(std.inc)
  11 include(selfcheck.inc)
  12 include(gen_int.inc)
  13 INIT_R_REGS(0);
  14 INIT_P_REGS(0);
  15 INIT_I_REGS(0);     // initialize the dsp address regs
  16 INIT_M_REGS(0);
  17 INIT_L_REGS(0);
  18 INIT_B_REGS(0);
  19 //CHECK_INIT(p5, 0xe0000000);
  20 include(symtable.inc)
  21 CHECK_INIT_DEF(p5);
  22
  23 #ifndef STACKSIZE
  24 #define STACKSIZE 0x10
  25 #endif
  26 #ifndef EVT
  27 #define EVT  0xFFE02000
  28 #endif
  29 #ifndef EVT15
  30 #define EVT15  0xFFE0203C
  31 #endif
  32 #ifndef EVT_OVERRIDE
  33 #define EVT_OVERRIDE 0xFFE02100
  34 #endif
  35 #ifndef ITABLE
  36 #define ITABLE DATA_ADDR_1
  37 #endif
  38
  39 GEN_INT_INIT(ITABLE) // set location for interrupt table
  40
  41 //
  42 // Reset/Bootstrap Code
  43 //   (Here we should set the processor operating modes, initialize registers,
  44 //
  45
  46 BOOT:
  47
  48                               // in reset mode now
  49 LD32_LABEL(sp, KSTACK);   // setup the stack pointer
  50 FP = SP;        // and frame pointer
  51
  52 LD32(p0, EVT);      // Setup Event Vectors and Handlers
  53 LD32_LABEL(r0, EHANDLE);  // Emulation Handler (Int0)
  54     [ P0 ++ ] = R0;
  55
  56 LD32_LABEL(r0, RHANDLE);  // Reset Handler (Int1)
  57     [ P0 ++ ] = R0;
  58
  59 LD32_LABEL(r0, NHANDLE);  // NMI Handler (Int2)
  60     [ P0 ++ ] = R0;
  61
  62 LD32_LABEL(r0, XHANDLE);  // Exception Handler (Int3)
  63     [ P0 ++ ] = R0;
  64
  65     [ P0 ++ ] = R0;        // IVT4 not used
  66
  67 LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
  68     [ P0 ++ ] = R0;
  69
  70 LD32_LABEL(r0, THANDLE);  // Timer Handler (Int6)
  71     [ P0 ++ ] = R0;
  72
  73 LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
  74     [ P0 ++ ] = R0;
  75
  76 LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
  77     [ P0 ++ ] = R0;
  78
  79 LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
  80     [ P0 ++ ] = R0;
  81
  82 LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
  83     [ P0 ++ ] = R0;
  84
  85 LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
  86     [ P0 ++ ] = R0;
  87
  88 LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
  89     [ P0 ++ ] = R0;
  90
  91 LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
  92     [ P0 ++ ] = R0;
  93
  94 LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
  95     [ P0 ++ ] = R0;
  96
  97 LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
  98     [ P0 ++ ] = R0;
  99
 100 LD32(p0, EVT_OVERRIDE);
 101     R0 = 0;
 102     [ P0 ++ ] = R0;
 103     R0 = -1;     // Change this to mask interrupts (*)
 104     [ P0 ] = R0;   // IMASK
 105 CSYNC;
 106
 107 DUMMY:
 108
 109     R0 = 0 (Z);
 110
 111 LT0 = r0;       // set loop counters to something deterministic
 112 LB0 = r0;
 113 LC0 = r0;
 114 LT1 = r0;
 115 LB1 = r0;
 116 LC1 = r0;
 117
 118 ASTAT = r0;     // reset other internal regs
 119
 120 // The following code sets up the test for running in USER mode
 121
 122 LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
 123                         // ReturnFromInterrupt (RTI)
 124 RETI = r0;      // We need to load the return address
 125
 126 // Comment the following line for a USER Mode test
 127
 128 JUMP    STARTSUP;   // jump to code start for SUPERVISOR mode
 129
 130 RTI;
 131
 132 STARTSUP:
 133 LD32_LABEL(p1, BEGIN);
 134
 135 LD32(p0, EVT15);
 136     [ P0 ] = P1;   // IVG15 (General) handler (Int 15) load with start
 137
 138 RAISE 15;   // after we RTI, INT 15 should be taken,& return to BEGIN in
 139                 // SUPERVISOR MODE & go to different RAISE in supervisor mode
 140                 // until the end of the test.
 141
 142 NOP;    // Workaround for Bug 217
 143 RTI;
 144
 145 //
 146 // The Main Program
 147 //
 148 STARTUSER:
 149 LD32_LABEL(sp, USTACK);   // setup the stack pointer
 150 FP = SP;            // set frame pointer
 151 JUMP BEGIN;
 152
 153 //*********************************************************************
 154
 155 BEGIN:
 156
 157                 // COMMENT the following line for USER MODE tests
 158     [ -- SP ] = RETI;  // enable interrupts in supervisor mode
 159
 160                 // **** YOUR CODE GOES HERE ****
 161
 162
 163
 164     // PUT YOUR TEST HERE!
 165 // PUSH
 166         R0 = 0x01;
 167         R1 = 0x02;
 168         R2 = 0x03;
 169         R3 = 0x04;
 170         R4 = 0x05;
 171         R5 = 0x06;
 172         R6 = 0x07;
 173         R7 = 0x08;
 174 LD32(p1, 0x12345678);
 175 LD32(p2, 0x05612496);
 176 LD32(p3, 0xab5fd490);
 177 LD32(p4, 0xa581bd94);
 178
 179
 180 //      [--sp] = (r7-r0);
 181 LD32(p1, 0xFFE02034);       // wrt-rd     EVT13             = 0xFFE02034
 182 LD32(r0, 0x55552345);
 183 RAISE 2;    // RTN
 184     [ P1 ] = R0;
 185 //  jump LABEL1;
 186     P1 = R1;
 187     R2 = P1;
 188         [ -- SP ] = ( R7:0 );
 189         R1 = 0x12;
 190         R2 = 0x13;
 191         R3 = 0x14;
 192         R4 = 0x15;
 193         R5 = 0x16;
 194         R6 = 0x17;
 195         R7 = 0x18;
 196
 197 LABEL1:
 198 RAISE 5;    // RTI
 199     P2 = R2;
 200     R3 = P2;
 201
 202         [ -- SP ] = ( R7:0 );
 203
 204         R2 = 0x23;
 205         R3 = 0x24;
 206         R4 = 0x25;
 207         R5 = 0x26;
 208         R6 = 0x27;
 209         R7 = 0x28;
 210 CSYNC;
 211 // wrt-rd     EVT5              = 0xFFE02034
 212 LD32(p1, 0xFFE02034);       // wrt-rd     EVT13             = 0xFFE02034
 213 RAISE 6;    // RTI
 214     R0 = [ P1 ];
 215 //  jump LABEL2;
 216     P3 = R3;
 217     R4 = P3;
 218         [ -- SP ] = ( R7:0 );
 219 // POP
 220         R0 = 0x00;
 221         R1 = 0x00;
 222         R2 = 0x00;
 223         R3 = 0x00;
 224         R4 = 0x00;
 225         R5 = 0x00;
 226         R6 = 0x00;
 227         R7 = 0x00;
 228
 229 LABEL2:
 230 RAISE 7;    // RTI
 231     P4 = R4;
 232     R5 = P4;
 233         ( R7:0 ) = [ SP ++ ];
 234
 235
 236
 237 CHECKREG(r0, 0x55552345);
 238 CHECKREG(r1, 0x00000012);
 239 CHECKREG(r2, 0x00000023);
 240 CHECKREG(r3, 0x00000024);
 241 CHECKREG(r4, 0x00000024);
 242 CHECKREG(r5, 0x00000026);
 243 CHECKREG(r6, 0x00000027);
 244 CHECKREG(r7, 0x00000028);
 245 // wrt-rd     EVT13             = 0xFFE02034
 246 LD32(p1, 0xFFE02034);
 247 RAISE 8;    // RTI
 248     R0 = [ P1 ];
 249 //  jump LABEL3;
 250     P1 = R5;
 251     R6 = P1;
 252         ( R7:0 ) = [ SP ++ ];
 253 CSYNC;
 254 CHECKREG(r0, 0x55552345);  // CHECKREG can not be skipped
 255 CHECKREG(r1, 0x00000012);  // so they cannot appear here
 256 CHECKREG(r2, 0x00000013);
 257 CHECKREG(r3, 0x00000013);
 258 CHECKREG(r4, 0x00000015);
 259 CHECKREG(r5, 0x00000016);
 260 CHECKREG(r6, 0x00000017);
 261 CHECKREG(r7, 0x00000018);
 262    R0 = 12;
 263    R1 = 13;
 264    R2 = 14;
 265    R3 = 15;
 266    R4 = 16;
 267    R5 = 17;
 268    R6 = 18;
 269    R7 = 19;
 270
 271
 272 LABEL3:
 273 //CHECKREG(r0, 0x55552345);
 274 RAISE 9;    // RTI
 275     P2 = R6;
 276     R7 = P2;
 277         ( R7:0 ) = [ SP ++ ];
 278
 279 CHECKREG(r0, 0x55552345);
 280 CHECKREG(r1, 0x00000002);
 281 CHECKREG(r2, 0x00000002);
 282 CHECKREG(r3, 0x00000004);
 283 CHECKREG(r4, 0x00000005);
 284 CHECKREG(r5, 0x00000006);
 285 CHECKREG(r6, 0x00000007);
 286 CHECKREG(r7, 0x00000008);
 287 R0 = I0;
 288 R1 = I1;
 289 R2 = I2;
 290 R3 = I3;
 291 CHECKREG(r0, 0x00000006);
 292 CHECKREG(r1, 0x00000002);
 293 CHECKREG(r2, 0x00000002);
 294 CHECKREG(r3, 0x00000002);
 295
 296
 297 END:
 298 dbg_pass;            // End the test
 299
 300 //*********************************************************************
 301
 302 //
 303 // Handlers for Events
 304 //
 305
 306 EHANDLE:            // Emulation Handler 0
 307 RTE;
 308
 309 RHANDLE:            // Reset Handler 1
 310 RTI;
 311
 312 NHANDLE:            // NMI Handler 2
 313     I0 += 2;
 314 RTN;
 315
 316 XHANDLE:            // Exception Handler 3
 317     R1 = 3;
 318 RTX;
 319
 320 HWHANDLE:           // HW Error Handler 5
 321     I1 += 2;
 322 RTI;
 323
 324 THANDLE:            // Timer Handler 6
 325     I2 += 2;
 326 RTI;
 327
 328 I7HANDLE:           // IVG 7 Handler
 329     I3 += 2;
 330 RTI;
 331
 332 I8HANDLE:           // IVG 8 Handler
 333     I0 += 2;
 334 RTI;
 335
 336 I9HANDLE:           // IVG 9 Handler
 337     I0 += 2;
 338 RTI;
 339
 340 I10HANDLE:          // IVG 10 Handler
 341     R7 = 10;
 342 RTI;
 343
 344 I11HANDLE:          // IVG 11 Handler
 345     I0 = R0;
 346     I1 = R1;
 347     I2 = R2;
 348     I3 = R3;
 349     M0 = R4;
 350     R0 = 11;
 351 RTI;
 352
 353 I12HANDLE:          // IVG 12 Handler
 354     R1 = 12;
 355 RTI;
 356
 357 I13HANDLE:          // IVG 13 Handler
 358     R2 = 13;
 359 RTI;
 360
 361 I14HANDLE:          // IVG 14 Handler
 362     R3 = 14;
 363 RTI;
 364
 365 I15HANDLE:          // IVG 15 Handler
 366     R4 = 15;
 367 RTI;
 368
 369 NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
 370
 371 //
 372 // Data Segment
 373 //
 374
 375 .data
 376 DATA:
 377     .space (0x10);
 378
 379 // Stack Segments (Both Kernel and User)
 380
 381     .space (STACKSIZE);
 382 KSTACK:
 383
 384     .space (STACKSIZE);
 385 USTACK: