sim/testsuite/sim/bfin/c_seq_wb_cs_lsmmrj_mvp.S

   1 //Original:/proj/frio/dv/testcases/core/c_seq_wb_cs_lsmmrj_mvp/c_seq_wb_cs_lsmmrj_mvp.dsp
   2 // Spec Reference: sequencer:wb ( csync ldst mmr jump regmv pushpopmultiple)
   3 # mach: bfin
   4 # sim: --environment operating
   5
   6 #include "test.h"
   7 .include "testutils.inc"
   8 start
   9
  10 include(std.inc)
  11 include(selfcheck.inc)
  12 include(gen_int.inc)
  13 INIT_R_REGS(0);
  14 INIT_P_REGS(0);
  15 INIT_I_REGS(0);     // initialize the dsp address regs
  16 INIT_M_REGS(0);
  17 INIT_L_REGS(0);
  18 INIT_B_REGS(0);
  19 //CHECK_INIT(p5, 0xe0000000);
  20 include(symtable.inc)
  21 CHECK_INIT_DEF(p5);
  22
  23 #ifndef STACKSIZE
  24 #define STACKSIZE 0x10
  25 #endif
  26 #ifndef EVT
  27 #define EVT  0xFFE02000
  28 #endif
  29 #ifndef EVT15
  30 #define EVT15  0xFFE0203C
  31 #endif
  32 #ifndef EVT_OVERRIDE
  33 #define EVT_OVERRIDE 0xFFE02100
  34 #endif
  35 #ifndef ITABLE
  36 #define ITABLE DATA_ADDR_1
  37 #endif
  38
  39 GEN_INT_INIT(ITABLE) // set location for interrupt table
  40
  41 //
  42 // Reset/Bootstrap Code
  43 //   (Here we should set the processor operating modes, initialize registers,
  44 //
  45
  46 BOOT:
  47
  48                               // in reset mode now
  49 LD32_LABEL(sp, KSTACK);   // setup the stack pointer
  50 FP = SP;        // and frame pointer
  51
  52 LD32(p0, EVT);      // Setup Event Vectors and Handlers
  53 LD32_LABEL(r0, EHANDLE);  // Emulation Handler (Int0)
  54     [ P0 ++ ] = R0;
  55
  56 LD32_LABEL(r0, RHANDLE);  // Reset Handler (Int1)
  57     [ P0 ++ ] = R0;
  58
  59 LD32_LABEL(r0, NHANDLE);  // NMI Handler (Int2)
  60     [ P0 ++ ] = R0;
  61
  62 LD32_LABEL(r0, XHANDLE);  // Exception Handler (Int3)
  63     [ P0 ++ ] = R0;
  64
  65     [ P0 ++ ] = R0;        // IVT4 not used
  66
  67 LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
  68     [ P0 ++ ] = R0;
  69
  70 LD32_LABEL(r0, THANDLE);  // Timer Handler (Int6)
  71     [ P0 ++ ] = R0;
  72
  73 LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
  74     [ P0 ++ ] = R0;
  75
  76 LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
  77     [ P0 ++ ] = R0;
  78
  79 LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
  80     [ P0 ++ ] = R0;
  81
  82 LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
  83     [ P0 ++ ] = R0;
  84
  85 LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
  86     [ P0 ++ ] = R0;
  87
  88 LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
  89     [ P0 ++ ] = R0;
  90
  91 LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
  92     [ P0 ++ ] = R0;
  93
  94 LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
  95     [ P0 ++ ] = R0;
  96
  97 LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
  98     [ P0 ++ ] = R0;
  99
 100 LD32(p0, EVT_OVERRIDE);
 101     R0 = 0;
 102     [ P0 ++ ] = R0;
 103     R0 = -1;     // Change this to mask interrupts (*)
 104     [ P0 ] = R0;   // IMASK
 105 CSYNC;
 106
 107 DUMMY:
 108
 109     R0 = 0 (Z);
 110
 111 LT0 = r0;       // set loop counters to something deterministic
 112 LB0 = r0;
 113 LC0 = r0;
 114 LT1 = r0;
 115 LB1 = r0;
 116 LC1 = r0;
 117
 118 ASTAT = r0;     // reset other internal regs
 119
 120 // The following code sets up the test for running in USER mode
 121
 122 LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
 123                         // ReturnFromInterrupt (RTI)
 124 RETI = r0;      // We need to load the return address
 125
 126 // Comment the following line for a USER Mode test
 127
 128 JUMP    STARTSUP;   // jump to code start for SUPERVISOR mode
 129
 130 RTI;
 131
 132 STARTSUP:
 133 LD32_LABEL(p1, BEGIN);
 134
 135 LD32(p0, EVT15);
 136     [ P0 ] = P1;   // IVG15 (General) handler (Int 15) load with start
 137
 138 RAISE 15;   // after we RTI, INT 15 should be taken,& return to BEGIN in
 139                 // SUPERVISOR MODE & go to different RAISE in supervisor mode
 140                 // until the end of the test.
 141
 142 NOP;    // Workaround for Bug 217
 143 RTI;
 144
 145 //
 146 // The Main Program
 147 //
 148 STARTUSER:
 149 LD32_LABEL(sp, USTACK);   // setup the stack pointer
 150 FP = SP;            // set frame pointer
 151 JUMP BEGIN;
 152
 153 //*********************************************************************
 154
 155 BEGIN:
 156
 157                 // COMMENT the following line for USER MODE tests
 158     [ -- SP ] = RETI;  // enable interrupts in supervisor mode
 159
 160                 // **** YOUR CODE GOES HERE ****
 161
 162
 163
 164     // PUT YOUR TEST HERE!
 165 // PUSH
 166 LD32(p1, 0xFFE02034);       // wrt-rd     EVT13             = 0xFFE02034
 167 //LD32(p2, DATA_ADDR_1);
 168 loadsym P2, DATA;
 169 LD32(p3, 0xab5fd490);
 170 LD32(p4, 0xa581bd94);
 171
 172 LD32(r2, 0x14789232);
 173     [ P1 ] = R2;
 174         R0 = 0x01;
 175         R1 = 0x02;
 176         R2 = 0x03;
 177         R3 = 0x04;
 178         R4 = 0x05;
 179         R5 = 0x06;
 180         R6 = 0x07;
 181         R7 = 0x08;
 182         [ -- SP ] = ( R7:0 );
 183 //  RAISE 2;    // RTN
 184 CSYNC;
 185     R0 = [ P2 ++ ];
 186     R1 = [ P1 ];
 187 JUMP.S LABEL1;
 188     P3 = R7;
 189     R4 = P3;
 190         [ -- SP ] = ( R7:0 );
 191         R1 = 0x12;
 192         R2 = 0x13;
 193         R3 = 0x14;
 194         R4 = 0x15;
 195         R5 = 0x16;
 196         R6 = 0x17;
 197         R7 = 0x18;
 198
 199 LABEL1:
 200 //  RAISE 5;    // RTI
 201 CSYNC;
 202     R2 = [ P2 ++ ];
 203
 204     P4 = R6;
 205     R3 = P4;
 206
 207         [ -- SP ] = ( R7:0 );
 208
 209         R2 = 0x23;
 210         R3 = 0x24;
 211         R4 = 0x25;
 212         R5 = 0x26;
 213         R6 = 0x27;
 214         R7 = 0x28;
 215
 216 // wrt-rd     EVT5              = 0xFFE02034
 217 LD32(p1, 0xFFE02034);       // wrt-rd     EVT13             = 0xFFE02034
 218 //  RAISE 6;    // RTI
 219 CSYNC;
 220     R4 = [ P2 ++ ];
 221     R6 = [ P1 ];
 222 JUMP.S LABEL2;
 223     P3 = R3;
 224     R5 = P3;
 225         [ -- SP ] = ( R7:0 );
 226 // POP
 227         R0 = 0x00;
 228         R1 = 0x00;
 229         R2 = 0x00;
 230         R3 = 0x00;
 231         R4 = 0x00;
 232         R5 = 0x00;
 233         R6 = 0x00;
 234         R7 = 0x00;
 235
 236 LABEL2:
 237 CSYNC;
 238 CHECKREG(r0, 0x00010203);
 239 CHECKREG(r1, 0x14789232);
 240 CHECKREG(r2, 0x00000023);
 241 CHECKREG(r3, 0x00000024);
 242 CHECKREG(r4, 0x08090A0B);
 243 CHECKREG(r5, 0x00000026);
 244 CHECKREG(r6, 0x14789232);
 245 //  RAISE 7;    // RTI
 246 CSYNC;
 247     R0 = [ P2 ++ ];
 248     R1 = [ P1 ];
 249     P4 = R4;
 250     R2 = P4;
 251         ( R7:0 ) = [ SP ++ ];
 252
 253
 254
 255 CHECKREG(r0, 0x00010203);
 256 CHECKREG(r1, 0x14789232);
 257 CHECKREG(r2, 0x04050607);
 258 CHECKREG(r3, 0x00000007);
 259 CHECKREG(r4, 0x00000005);
 260 CHECKREG(r5, 0x00000006);
 261 CHECKREG(r6, 0x00000007);
 262 CHECKREG(r7, 0x00000008);
 263 // wrt-rd     EVT13             = 0xFFE02034
 264 LD32(p1, 0xFFE02034);
 265 //  RAISE 8;    // RTI
 266 CSYNC;
 267     R0 = [ P2 ++ ];
 268     R1 = [ P1 ];
 269 JUMP.S LABEL3;
 270     P1 = R5;
 271     R6 = P1;
 272         ( R7:0 ) = [ SP ++ ];
 273 //CHECKREG(r0, 0x000000a1);  // CHECKREG can not be skipped
 274 //CHECKREG(r1, 0x000000b2);  // so they cannot appear here
 275 //CHECKREG(r2, 0x000000c3);
 276 //CHECKREG(r3, 0x000000d4);
 277 //CHECKREG(r4, 0x000000e5);
 278 //CHECKREG(r5, 0x000000f6);
 279 //CHECKREG(r6, 0x00000017);
 280 //CHECKREG(r7, 0x00000028);
 281    R0 = 12;
 282    R1 = 13;
 283    R2 = 14;
 284    R3 = 15;
 285    R4 = 16;
 286    R5 = 17;
 287    R6 = 18;
 288    R7 = 19;
 289
 290
 291 LABEL3:
 292 CSYNC;
 293 CHECKREG(r0, 0x10111213);
 294 CHECKREG(r1, 0x14789232);
 295 //  RAISE 9;    // RTI
 296 CSYNC;
 297     P3 = R6;
 298     R7 = P3;
 299         ( R7:0 ) = [ SP ++ ];
 300
 301 CHECKREG(r0, 0x00000001);
 302 CHECKREG(r1, 0x00000002);
 303 CHECKREG(r2, 0x00000003);
 304 CHECKREG(r3, 0x00000004);
 305 CHECKREG(r4, 0x00000005);
 306 CHECKREG(r5, 0x00000006);
 307 CHECKREG(r6, 0x00000007);
 308 CHECKREG(r7, 0x00000008);
 309 R0 = I0;
 310 R1 = I1;
 311 R2 = I2;
 312 R3 = I3;
 313 CHECKREG(r0, 0x00000000);
 314 CHECKREG(r1, 0x00000000);
 315 CHECKREG(r2, 0x00000000);
 316 CHECKREG(r3, 0x00000000);
 317
 318
 319 END:
 320 dbg_pass;            // End the test
 321
 322 //*********************************************************************
 323
 324 //
 325 // Handlers for Events
 326 //
 327
 328 EHANDLE:            // Emulation Handler 0
 329 RTE;
 330
 331 RHANDLE:            // Reset Handler 1
 332 RTI;
 333
 334 NHANDLE:            // NMI Handler 2
 335     I0 += 2;
 336 RTN;
 337
 338 XHANDLE:            // Exception Handler 3
 339     R1 = 3;
 340 RTX;
 341
 342 HWHANDLE:           // HW Error Handler 5
 343     I1 += 2;
 344 RTI;
 345
 346 THANDLE:            // Timer Handler 6
 347     I2 += 2;
 348 RTI;
 349
 350 I7HANDLE:           // IVG 7 Handler
 351     I3 += 2;
 352 RTI;
 353
 354 I8HANDLE:           // IVG 8 Handler
 355     I0 += 2;
 356 RTI;
 357
 358 I9HANDLE:           // IVG 9 Handler
 359     I0 += 2;
 360 RTI;
 361
 362 I10HANDLE:          // IVG 10 Handler
 363     R7 = 10;
 364 RTI;
 365
 366 I11HANDLE:          // IVG 11 Handler
 367     I0 = R0;
 368     I1 = R1;
 369     I2 = R2;
 370     I3 = R3;
 371     M0 = R4;
 372     R0 = 11;
 373 RTI;
 374
 375 I12HANDLE:          // IVG 12 Handler
 376     R1 = 12;
 377 RTI;
 378
 379 I13HANDLE:          // IVG 13 Handler
 380     R2 = 13;
 381 RTI;
 382
 383 I14HANDLE:          // IVG 14 Handler
 384     R3 = 14;
 385 RTI;
 386
 387 I15HANDLE:          // IVG 15 Handler
 388     R4 = 15;
 389 RTI;
 390
 391 NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
 392
 393 //
 394 // Data Segment
 395 //
 396
 397 .section MEM_DATA_ADDR_1,"aw"
 398 DATA:
 399 //  .space (0x10);
 400 .dd 0x00010203
 401 .dd 0x04050607
 402 .dd 0x08090A0B
 403 .dd 0x0C0D0E0F
 404 .dd 0x10111213
 405 .dd 0x14151617
 406 .dd 0x18191A1B
 407 .dd 0x1C1D1E1F
 408 .dd 0x11223344
 409 .dd 0x55667788
 410 .dd 0x99717273
 411 .dd 0x74757677
 412 .dd 0x82838485
 413 .dd 0x86878889
 414 .dd 0x80818283
 415 .dd 0x84858687
 416 .dd 0x01020304
 417 .dd 0x05060708
 418 .dd 0x09101112
 419 .dd 0x14151617
 420 .dd 0x18192021
 421
 422
 423 // Stack Segments (Both Kernel and User)
 424
 425     .space (STACKSIZE);
 426 KSTACK:
 427
 428     .space (STACKSIZE);
 429 USTACK:
 430
 431 .section MEM_DATA_ADDR_2,"aw"
 432 .dd 0x20212223
 433 .dd 0x24252627
 434 .dd 0x28292A2B
 435 .dd 0x2C2D2E2F
 436 .dd 0x30313233
 437 .dd 0x34353637
 438 .dd 0x38393A3B
 439 .dd 0x3C3D3E3F
 440 .dd 0x91929394
 441 .dd 0x95969798
 442 .dd 0x99A1A2A3
 443 .dd 0xA5A6A7A8
 444 .dd 0xA9B0B1B2
 445 .dd 0xB3B4B5B6
 446 .dd 0xB7B8B9C0