sim/testsuite/sim/bfin/lmu_excpt_align.S

   1 //Original:/proj/frio/dv/testcases/lmu/lmu_excpt_align/lmu_excpt_align.dsp
   2 // Description: LMU data alignment exceptions
   3 # mach: bfin
   4 # sim: --environment operating
   5
   6 #include "test.h"
   7 .include "testutils.inc"
   8 start
   9
  10 include(selfcheck.inc)
  11 include(std.inc)
  12 include(mmrs.inc)
  13
  14 CHECK_INIT(p5, 0xE0000000);
  15
  16                 // test address for DAG0
  17                 // test address for DAG1
  18
  19         // setup interrupt controller with exception handler address
  20         WR_MMR_LABEL(EVT3, handler, p0, r1);
  21
  22         // Write fault addr MMR to known state
  23         WR_MMR(DCPLB_FAULT_ADDR, 0, p0, r6);
  24
  25         //nop;nop;nop;nop;nop;  // in lieu of CSYNC
  26         CSYNC;
  27
  28         A0 = 0;
  29
  30         // go to user mode. and enable exceptions
  31         LD32_LABEL(r0, User);
  32         RETI = R0;
  33         RTI;
  34
  35         // Nops to work around ICache bug
  36         NOP;NOP;NOP;NOP;NOP;
  37         NOP;NOP;NOP;NOP;NOP;
  38
  39
  40 User:
  41         NOP;NOP;NOP;NOP;NOP;
  42
  43         //-------------------------------------------------------
  44         // First do stores
  45         //-------------------------------------------------------
  46         // 16-bit alignment, DAG0
  47
  48
  49
  50         LD32(i1, ((0x1000 + 1)));
  51         LD32(p2, ((0x1000 + 1) & 0xFFFFFFFE));  // Aligned version
  52         LD32(r1, 0xDEADBEEF);
  53         R5 = 0;R6 = 0;R7 = 0;                           // Exception handler will set these, reset them first
  54
  55 X01:    W [ I1 ] = R1.L;                                // Exception should occur here
  56
  57         CHECKREG(r5,0x24);                      // supv and EXCPT_ALIGN
  58         CHECKREG(r6, (0x1000 + 1));             // FAULT_ADDR should contain fail address
  59         CHECKREG_SYM(r7, X01, r0);                      // RETX should be value of X01  (HARDCODED ADDR!!)
  60
  61
  62         //-------------------------------------------------------
  63         // 32-bit alignment, DAG0
  64
  65
  66
  67         LD32(i1, ((0x1000 + 1)));
  68         LD32(p2, ((0x1000 + 1) & 0xFFFFFFFC));  // Aligned version
  69         LD32(r1, 0xDEADBEEF);
  70         R5 = 0;R6 = 0;R7 = 0;                           // Exception handler will set these, reset them first
  71
  72 X02:    [ I1 ] = R1;                            // Exception should occur here
  73
  74         CHECKREG(r5,0x24);                      // supv and EXCPT_ALIGN
  75         CHECKREG(r6, (0x1000 + 1));             // FAULT_ADDR should contain fail address
  76         CHECKREG_SYM(r7, X02, r0);                      // RETX should be value of X02  (HARDCODED ADDR!!)
  77
  78
  79         //-------------------------------------------------------
  80         // 32-bit alignment, DAG0
  81
  82
  83
  84         LD32(i1, ((0x1000 + 2)));
  85         LD32(p2, ((0x1000 + 2) & 0xFFFFFFFC));  // Aligned version
  86         LD32(r1, 0xDEADBEEF);
  87         R5 = 0;R6 = 0;R7 = 0;                           // Exception handler will set these, reset them first
  88
  89 X03:    [ I1 ] = R1;                            // Exception should occur here
  90
  91         CHECKREG(r5,0x24);                      // supv and EXCPT_ALIGN
  92         CHECKREG(r6, (0x1000 + 2));             // FAULT_ADDR should contain fail address
  93         CHECKREG_SYM(r7, X03, r0);                      // RETX should be value of X03  (HARDCODED ADDR!!)
  94
  95
  96         //-------------------------------------------------------
  97         // 32-bit alignment, DAG0
  98
  99
 100
 101         LD32(i1, ((0x1000 + 3)));
 102         LD32(p2, ((0x1000 + 3) & 0xFFFFFFFC));  // Aligned version
 103         LD32(r1, 0xDEADBEEF);
 104         R5 = 0;R6 = 0;R7 = 0;                           // Exception handler will set these, reset them first
 105
 106 X04:    [ I1 ] = R1;                            // Exception should occur here
 107
 108         CHECKREG(r5,0x24);                      // supv and EXCPT_ALIGN
 109         CHECKREG(r6, (0x1000 + 3));             // FAULT_ADDR should contain fail address
 110         CHECKREG_SYM(r7, X04, r0);                      // RETX should be value of X04  (HARDCODED ADDR!!)
 111
 112
 113         //-------------------------------------------------------
 114         // 16-bit alignment, DAG1
 115
 116
 117
 118         LD32(i1, ((0x1000 + 1)));
 119         LD32(p2, ((0x1000 + 1) & 0xFFFFFFFE));  // Aligned version
 120         LD32(r1, 0xDEADBEEF);
 121         R5 = 0;R6 = 0;R7 = 0;                           // Exception handler will set these, reset them first
 122
 123 X05:    A0 = 0 || NOP || W [ I1 ] = R1.L;                       // Exception should occur here
 124
 125         CHECKREG(r5,0x24);                      // supv and EXCPT_ALIGN
 126         CHECKREG(r6, (0x1000 + 1));             // FAULT_ADDR should contain fail address
 127         CHECKREG_SYM(r7, X05, r0);                      // RETX should be value of X05  (HARDCODED ADDR!!)
 128
 129
 130         //-------------------------------------------------------
 131         // 32-bit alignment, DAG1
 132
 133
 134
 135         LD32(i1, ((0x1000 + 1)));
 136         LD32(p2, ((0x1000 + 1) & 0xFFFFFFFC));  // Aligned version
 137         LD32(r1, 0xDEADBEEF);
 138         R5 = 0;R6 = 0;R7 = 0;                           // Exception handler will set these, reset them first
 139
 140 X06:    A0 = 0 || NOP || [ I1 ] = R1;                   // Exception should occur here
 141
 142         CHECKREG(r5,0x24);                      // supv and EXCPT_ALIGN
 143         CHECKREG(r6, (0x1000 + 1));             // FAULT_ADDR should contain fail address
 144         CHECKREG_SYM(r7, X06, r0);                      // RETX should be value of X06  (HARDCODED ADDR!!)
 145
 146
 147         //-------------------------------------------------------
 148         // 32-bit alignment, DAG1
 149
 150
 151
 152         LD32(i1, ((0x1000 + 2)));
 153         LD32(p2, ((0x1000 + 2) & 0xFFFFFFFC));  // Aligned version
 154         LD32(r1, 0xDEADBEEF);
 155         R5 = 0;R6 = 0;R7 = 0;                           // Exception handler will set these, reset them first
 156
 157 X07:    A0 = 0 || NOP || [ I1 ] = R1;                   // Exception should occur here
 158
 159         CHECKREG(r5,0x24);                      // supv and EXCPT_ALIGN
 160         CHECKREG(r6, (0x1000 + 2));             // FAULT_ADDR should contain fail address
 161         CHECKREG_SYM(r7, X07, r0);                      // RETX should be value of X07  (HARDCODED ADDR!!)
 162
 163
 164         //-------------------------------------------------------
 165         // 32-bit alignment, DAG1
 166
 167
 168
 169         LD32(i1, ((0x1000 + 3)));
 170         LD32(p2, ((0x1000 + 3) & 0xFFFFFFFC));  // Aligned version
 171         LD32(r1, 0xDEADBEEF);
 172         R5 = 0;R6 = 0;R7 = 0;                           // Exception handler will set these, reset them first
 173
 174 X08:    A0 = 0 || NOP || [ I1 ] = R1;                   // Exception should occur here
 175
 176         CHECKREG(r5,0x24);                      // supv and EXCPT_ALIGN
 177         CHECKREG(r6, (0x1000 + 3));             // FAULT_ADDR should contain fail address
 178         CHECKREG_SYM(r7, X08, r0);                      // RETX should be value of X08  (HARDCODED ADDR!!)
 179
 180
 181         //-------------------------------------------------------
 182         // Now repeat for Loads
 183         //-------------------------------------------------------
 184         // 16-bit alignment, DAG0
 185
 186
 187
 188         LD32(i1, ((0x1000 + 1)));
 189         LD32(p2, ((0x1000 + 1) & 0xFFFFFFFE));  // Aligned version
 190         LD32(r1, 0xDEADBEEF);
 191         R5 = 0;R6 = 0;R7 = 0;                           // Exception handler will set these, reset them first
 192
 193 X11:    R1.L = W [ I1 ];                                // Exception should occur here
 194
 195         CHECKREG(r5,0x24);                      // supv and EXCPT_ALIGN
 196         CHECKREG(r6, (0x1000 + 1));             // FAULT_ADDR should contain fail address
 197         CHECKREG_SYM(r7, X11, r0);                      // RETX should be value of X11  (HARDCODED ADDR!!)
 198
 199
 200         //-------------------------------------------------------
 201         // 32-bit alignment, DAG0
 202
 203
 204
 205         LD32(i1, ((0x1000 + 1)));
 206         LD32(p2, ((0x1000 + 1) & 0xFFFFFFFC));  // Aligned version
 207         LD32(r1, 0xDEADBEEF);
 208         R5 = 0;R6 = 0;R7 = 0;                           // Exception handler will set these, reset them first
 209
 210 X12:    R1 = [ I1 ];                            // Exception should occur here
 211
 212         CHECKREG(r5,0x24);                      // supv and EXCPT_ALIGN
 213         CHECKREG(r6, (0x1000 + 1));             // FAULT_ADDR should contain fail address
 214         CHECKREG_SYM(r7, X12, r0);                      // RETX should be value of X12  (HARDCODED ADDR!!)
 215
 216
 217         //-------------------------------------------------------
 218         // 32-bit alignment, DAG0
 219
 220
 221
 222         LD32(i1, ((0x1000 + 2)));
 223         LD32(p2, ((0x1000 + 2) & 0xFFFFFFFC));  // Aligned version
 224         LD32(r1, 0xDEADBEEF);
 225         R5 = 0;R6 = 0;R7 = 0;                           // Exception handler will set these, reset them first
 226
 227 X13:    R1 = [ I1 ];                            // Exception should occur here
 228
 229         CHECKREG(r5,0x24);                      // supv and EXCPT_ALIGN
 230         CHECKREG(r6, (0x1000 + 2));             // FAULT_ADDR should contain fail address
 231         CHECKREG_SYM(r7, X13, r0);                      // RETX should be value of X13  (HARDCODED ADDR!!)
 232
 233
 234         //-------------------------------------------------------
 235         // 32-bit alignment, DAG0
 236
 237
 238
 239         LD32(i1, ((0x1000 + 3)));
 240         LD32(p2, ((0x1000 + 3) & 0xFFFFFFFC));  // Aligned version
 241         LD32(r1, 0xDEADBEEF);
 242         R5 = 0;R6 = 0;R7 = 0;                           // Exception handler will set these, reset them first
 243
 244 X14:    R1 = [ I1 ];                            // Exception should occur here
 245
 246         CHECKREG(r5,0x24);                      // supv and EXCPT_ALIGN
 247         CHECKREG(r6, (0x1000 + 3));             // FAULT_ADDR should contain fail address
 248         CHECKREG_SYM(r7, X14, r0);                      // RETX should be value of X14  (HARDCODED ADDR!!)
 249
 250
 251         //-------------------------------------------------------
 252         // 16-bit alignment, DAG1
 253
 254
 255
 256         LD32(i1, ((0x1000 + 1)));
 257         LD32(p2, ((0x1000 + 1) & 0xFFFFFFFE));  // Aligned version
 258         LD32(r1, 0xDEADBEEF);
 259         R5 = 0;R6 = 0;R7 = 0;                           // Exception handler will set these, reset them first
 260
 261 X15:    A0 = 0 || NOP || R1.L = W [ I1 ];                       // Exception should occur here
 262
 263         CHECKREG(r5,0x24);                      // supv and EXCPT_ALIGN
 264         CHECKREG(r6, (0x1000 + 1));             // FAULT_ADDR should contain fail address
 265         CHECKREG_SYM(r7, X15, r0);                      // RETX should be value of X15  (HARDCODED ADDR!!)
 266
 267
 268         //-------------------------------------------------------
 269         // 32-bit alignment, DAG1
 270
 271
 272
 273         LD32(i1, ((0x1000 + 1)));
 274         LD32(p2, ((0x1000 + 1) & 0xFFFFFFFC));  // Aligned version
 275         LD32(r1, 0xDEADBEEF);
 276         R5 = 0;R6 = 0;R7 = 0;                           // Exception handler will set these, reset them first
 277
 278 X16:    A0 = 0 || NOP || R1 = [ I1 ];                   // Exception should occur here
 279
 280         CHECKREG(r5,0x24);                      // supv and EXCPT_ALIGN
 281         CHECKREG(r6, (0x1000 + 1));             // FAULT_ADDR should contain fail address
 282         CHECKREG_SYM(r7, X16, r0);                      // RETX should be value of X16  (HARDCODED ADDR!!)
 283
 284
 285         //-------------------------------------------------------
 286         // 32-bit alignment, DAG1
 287
 288
 289
 290         LD32(i1, ((0x1000 + 2)));
 291         LD32(p2, ((0x1000 + 2) & 0xFFFFFFFC));  // Aligned version
 292         LD32(r1, 0xDEADBEEF);
 293         R5 = 0;R6 = 0;R7 = 0;                           // Exception handler will set these, reset them first
 294
 295 X17:    A0 = 0 || NOP || R1 = [ I1 ];                   // Exception should occur here
 296
 297         CHECKREG(r5,0x24);                      // supv and EXCPT_ALIGN
 298         CHECKREG(r6, (0x1000 + 2));             // FAULT_ADDR should contain fail address
 299         CHECKREG_SYM(r7, X17, r0);                      // RETX should be value of X17  (HARDCODED ADDR!!)
 300
 301
 302         //-------------------------------------------------------
 303         // 32-bit alignment, DAG1
 304
 305
 306
 307         LD32(i1, ((0x1000 + 3)));
 308         LD32(p2, ((0x1000 + 3) & 0xFFFFFFFC));  // Aligned version
 309         LD32(r1, 0xDEADBEEF);
 310         R5 = 0;R6 = 0;R7 = 0;                           // Exception handler will set these, reset them first
 311
 312 X18:    A0 = 0 || NOP || R1 = [ I1 ];                   // Exception should occur here
 313
 314         CHECKREG(r5,0x24);                      // supv and EXCPT_ALIGN
 315         CHECKREG(r6, (0x1000 + 3));             // FAULT_ADDR should contain fail address
 316         CHECKREG_SYM(r7, X18, r0);                      // RETX should be value of X18  (HARDCODED ADDR!!)
 317
 318
 319         //-------------------------------------------------------
 320         dbg_pass;
 321
 322
 323 handler:
 324         R5 = SEQSTAT;   // Get exception cause
 325
 326         // read and check fail addr (addr_which_causes_exception)
 327         // should not be set for alignment exception
 328         RD_MMR(DCPLB_FAULT_ADDR, p0, r6);
 329
 330         R7 = RETX;      // get address of excepting instruction
 331
 332         // align the offending address
 333         I1 = P2;
 334
 335         RTX;
 336         // Nops to work around ICache bug
 337         NOP;NOP;NOP;NOP;NOP;
 338         NOP;NOP;NOP;NOP;NOP;
 339
 340
 341 .section MEM_0x1000,"aw"
 342         .dd 0x00000000
 343         .dd 0x00000000
 344         .dd 0x00000000
 345         .dd 0x00000000