sim/testsuite/sim/bfin/s18.s

   1 //  Immediate dual 16b SHIFT test program.
   2 //  Test  r4 = ASHIFT/ASHIFT (r2 by 10);
   3 //  Test  r4 = ASHIFT/ASHIFT (r2 by 10) S;
   4 //  Test  r4 = LSHIFT/LSHIFT (r2 by 10);
   5 # mach: bfin
   6
   7 .include "testutils.inc"
   8         start
   9
  10
  11 // arithmetic
  12 //  left by largest positive magnitude of 15 (0xf)
  13 // 8001 -> 8000
  14         R7 = 0;
  15         ASTAT = R7;
  16         R0.L = 0x8001;
  17         R0.H = 0x0100;
  18         R6 = R0 << 15 (V);
  19         DBGA ( R6.L , 0x8000 );
  20         DBGA ( R6.H , 0x0000 );
  21         CC = AZ;        R7 = CC; DBGA ( R7.L , 0x1 );
  22         CC = AN;        R7 = CC; DBGA ( R7.L , 0x1 );
  23         CC = AC0;       R7 = CC; DBGA ( R7.L , 0x0 );
  24         CC = AV0;       R7 = CC; DBGA ( R7.L , 0x0 );
  25         CC = AV1;       R7 = CC; DBGA ( R7.L , 0x0 );
  26
  27 // arithmetic
  28 //  left by largest positive magnitude of 15 (0xf) with saturation
  29         R7 = 0;
  30         ASTAT = R7;
  31         R0.L = 0x8001;
  32         R0.H = 0x0100;
  33         R6 = R0 << 15 (V , S);
  34         DBGA ( R6.L , 0x8000 );
  35         DBGA ( R6.H , 0x7fff );
  36         CC = AZ;        R7 = CC; DBGA ( R7.L , 0x0 );
  37         CC = AN;        R7 = CC; DBGA ( R7.L , 0x1 );
  38         CC = AC0;       R7 = CC; DBGA ( R7.L , 0x0 );
  39         CC = AV0;       R7 = CC; DBGA ( R7.L , 0x0 );
  40         CC = AV1;       R7 = CC; DBGA ( R7.L , 0x0 );
  41
  42 // arithmetic
  43 //  left by 1
  44         R7 = 0;
  45         ASTAT = R7;
  46         R0.L = 0x8001;
  47         R0.H = 0x0100;
  48         R6 = R0 << 1 (V);
  49         DBGA ( R6.L , 0x0002 );
  50         DBGA ( R6.H , 0x0200 );
  51         CC = AZ;        R7 = CC; DBGA ( R7.L , 0x0 );
  52         CC = AN;        R7 = CC; DBGA ( R7.L , 0x0 );
  53         CC = AC0;       R7 = CC; DBGA ( R7.L , 0x0 );
  54         CC = AV0;       R7 = CC; DBGA ( R7.L , 0x0 );
  55         CC = AV1;       R7 = CC; DBGA ( R7.L , 0x0 );
  56
  57 // arithmetic
  58 //  left by 1 saturating
  59         R7 = 0;
  60         ASTAT = R7;
  61         R0.L = 0x8001;
  62         R0.H = 0x0100;
  63         R6 = R0 << 1 (V , S);
  64         DBGA ( R6.L , 0x8000 );
  65         DBGA ( R6.H , 0x0200 );
  66         CC = AZ;        R7 = CC; DBGA ( R7.L , 0x0 );
  67         CC = AN;        R7 = CC; DBGA ( R7.L , 0x1 );
  68         CC = AC0;       R7 = CC; DBGA ( R7.L , 0x0 );
  69         CC = AV0;       R7 = CC; DBGA ( R7.L , 0x0 );
  70         CC = AV1;       R7 = CC; DBGA ( R7.L , 0x0 );
  71
  72 // arithmetic
  73 //  left by 15 saturating
  74         R7 = 0;
  75         ASTAT = R7;
  76         R0.L = 0xfff0;
  77         R0.H = 0x0000;
  78         R6 = R0 << 15 (V , S);
  79         DBGA ( R6.L , 0x8000 );
  80         DBGA ( R6.H , 0x0000 );
  81         CC = AZ;        R7 = CC; DBGA ( R7.L , 0x1 );
  82         CC = AN;        R7 = CC; DBGA ( R7.L , 0x1 );
  83         CC = AC0;       R7 = CC; DBGA ( R7.L , 0x0 );
  84         CC = AV0;       R7 = CC; DBGA ( R7.L , 0x0 );
  85         CC = AV1;       R7 = CC; DBGA ( R7.L , 0x0 );
  86
  87 // arithmetic
  88 //  right by 15
  89         R7 = 0;
  90         ASTAT = R7;
  91         R0.L = 0x8000;
  92         R0.H = 0x0100;
  93         R6 = R0 >>> 15 (V);
  94         DBGA ( R6.L , 0xffff );
  95         DBGA ( R6.H , 0x0000 );
  96         CC = AZ;        R7 = CC; DBGA ( R7.L , 0x1 );
  97         CC = AN;        R7 = CC; DBGA ( R7.L , 0x1 );
  98         CC = AC0;       R7 = CC; DBGA ( R7.L , 0x0 );
  99         CC = AV0;       R7 = CC; DBGA ( R7.L , 0x0 );
 100         CC = AV1;       R7 = CC; DBGA ( R7.L , 0x0 );
 101
 102 // arithmetic
 103 //  right by 15 (sat has no effect)
 104         R7 = 0;
 105         ASTAT = R7;
 106         R0.L = 0x8000;
 107         R0.H = 0x0100;
 108         R6 = R0 >>> 15 (V);
 109         DBGA ( R6.L , 0xffff );
 110         DBGA ( R6.H , 0x0000 );
 111         CC = AZ;        R7 = CC; DBGA ( R7.L , 0x1 );
 112         CC = AN;        R7 = CC; DBGA ( R7.L , 0x1 );
 113         CC = AC0;       R7 = CC; DBGA ( R7.L , 0x0 );
 114         CC = AV0;       R7 = CC; DBGA ( R7.L , 0x0 );
 115         CC = AV1;       R7 = CC; DBGA ( R7.L , 0x0 );
 116
 117 // logic
 118 //  right by 15
 119         R7 = 0;
 120         ASTAT = R7;
 121         R0.L = 0x8000;
 122         R0.H = 0x0100;
 123         R6 = R0 >> 15 (V);
 124         DBGA ( R6.L , 0x0001 );
 125         DBGA ( R6.H , 0x0000 );
 126         CC = AZ;        R7 = CC; DBGA ( R7.L , 0x1 );
 127         CC = AN;        R7 = CC; DBGA ( R7.L , 0x0 );
 128         CC = AC0;       R7 = CC; DBGA ( R7.L , 0x0 );
 129         CC = AV0;       R7 = CC; DBGA ( R7.L , 0x0 );
 130         CC = AV1;       R7 = CC; DBGA ( R7.L , 0x0 );
 131
 132         pass