sim/testsuite/sim/bfin/s19.s

   1 //  REG-BASED dual 16b SHIFT test program.
   2 //  Test  r4 = ASHIFT/ASHIFT (r2 by rl1);
   3 //  Test  r4 = ASHIFT/ASHIFT (r2 by rl1) S;
   4 //  Test  r4 = LSHIFT/LSHIFT (r2 by rl1);
   5 # mach: bfin
   6
   7 .include "testutils.inc"
   8         start
   9
  10
  11 // arithmetic
  12 //  left by largest positive magnitude of 15 (0xf)
  13 // 8001 -> 8000
  14         R7 = 0;
  15         ASTAT = R7;
  16         R0.L = 0x8001;
  17         R0.H = 0x0100;
  18         R1.L = 15;
  19         R6 = ASHIFT R0 BY R1.L (V);
  20         DBGA ( R6.L , 0x8000 );
  21         DBGA ( R6.H , 0x0000 );
  22         CC = AZ;        R7 = CC; DBGA ( R7.L , 0x1 );
  23         CC = AN;        R7 = CC; DBGA ( R7.L , 0x1 );
  24         CC = AC0;       R7 = CC; DBGA ( R7.L , 0x0 );
  25         CC = AV0;       R7 = CC; DBGA ( R7.L , 0x0 );
  26         CC = AV1;       R7 = CC; DBGA ( R7.L , 0x0 );
  27
  28 // arithmetic
  29 //  left by largest positive magnitude of 15 (0xf) with saturation
  30         R7 = 0;
  31         ASTAT = R7;
  32         R0.L = 0x8001;
  33         R0.H = 0x0100;
  34         R1.L = 15;
  35         R6 = ASHIFT R0 BY R1.L (V , S);
  36         DBGA ( R6.L , 0x8000 );
  37         DBGA ( R6.H , 0x7fff );
  38         CC = AZ;        R7 = CC; DBGA ( R7.L , 0x0 );
  39         CC = AN;        R7 = CC; DBGA ( R7.L , 0x1 );
  40         CC = AC0;       R7 = CC; DBGA ( R7.L , 0x0 );
  41         CC = AV0;       R7 = CC; DBGA ( R7.L , 0x0 );
  42         CC = AV1;       R7 = CC; DBGA ( R7.L , 0x0 );
  43
  44 // arithmetic
  45 //  left by 1
  46         R7 = 0;
  47         ASTAT = R7;
  48         R0.L = 0x8001;
  49         R0.H = 0x0100;
  50         R1.L = 1;
  51         R6 = ASHIFT R0 BY R1.L (V);
  52         DBGA ( R6.L , 0x0002 );
  53         DBGA ( R6.H , 0x0200 );
  54         CC = AZ;        R7 = CC; DBGA ( R7.L , 0x0 );
  55         CC = AN;        R7 = CC; DBGA ( R7.L , 0x0 );
  56         CC = AC0;       R7 = CC; DBGA ( R7.L , 0x0 );
  57         CC = AV0;       R7 = CC; DBGA ( R7.L , 0x0 );
  58         CC = AV1;       R7 = CC; DBGA ( R7.L , 0x0 );
  59
  60 // arithmetic
  61 //  left by 1 saturating
  62         R7 = 0;
  63         ASTAT = R7;
  64         R0.L = 0x8001;
  65         R0.H = 0x0100;
  66         R1.L = 1;
  67         R6 = ASHIFT R0 BY R1.L (V , S);
  68         DBGA ( R6.L , 0x8000 );
  69         DBGA ( R6.H , 0x0200 );
  70         CC = AZ;        R7 = CC; DBGA ( R7.L , 0x0 );
  71         CC = AN;        R7 = CC; DBGA ( R7.L , 0x1 );
  72         CC = AC0;       R7 = CC; DBGA ( R7.L , 0x0 );
  73         CC = AV0;       R7 = CC; DBGA ( R7.L , 0x0 );
  74         CC = AV1;       R7 = CC; DBGA ( R7.L , 0x0 );
  75
  76 // arithmetic
  77 //  left by 15 saturating
  78         R7 = 0;
  79         ASTAT = R7;
  80         R0.L = 0xfff0;
  81         R0.H = 0x0000;
  82         R1.L = 15;
  83         R6 = ASHIFT R0 BY R1.L (V , S);
  84         DBGA ( R6.L , 0x8000 );
  85         DBGA ( R6.H , 0x0000 );
  86         CC = AZ;        R7 = CC; DBGA ( R7.L , 0x1 );
  87         CC = AN;        R7 = CC; DBGA ( R7.L , 0x1 );
  88         CC = AC0;       R7 = CC; DBGA ( R7.L , 0x0 );
  89         CC = AV0;       R7 = CC; DBGA ( R7.L , 0x0 );
  90         CC = AV1;       R7 = CC; DBGA ( R7.L , 0x0 );
  91
  92 // arithmetic
  93 //  right by 15
  94         R7 = 0;
  95         ASTAT = R7;
  96         R0.L = 0x8000;
  97         R0.H = 0x0100;
  98         R1.L = -15;
  99         R6 = ASHIFT R0 BY R1.L (V);
 100         DBGA ( R6.L , 0xffff );
 101         DBGA ( R6.H , 0x0000 );
 102         CC = AZ;        R7 = CC; DBGA ( R7.L , 0x1 );
 103         CC = AN;        R7 = CC; DBGA ( R7.L , 0x1 );
 104         CC = AC0;       R7 = CC; DBGA ( R7.L , 0x0 );
 105         CC = AV0;       R7 = CC; DBGA ( R7.L , 0x0 );
 106         CC = AV1;       R7 = CC; DBGA ( R7.L , 0x0 );
 107
 108 // arithmetic
 109 //  right by 15 (sat has no effect)
 110         R7 = 0;
 111         ASTAT = R7;
 112         R0.L = 0x8000;
 113         R0.H = 0x0100;
 114         R1.L = -15;
 115         R6 = ASHIFT R0 BY R1.L (V , S);
 116         DBGA ( R6.L , 0xffff );
 117         DBGA ( R6.H , 0x0000 );
 118         CC = AZ;        R7 = CC; DBGA ( R7.L , 0x1 );
 119         CC = AN;        R7 = CC; DBGA ( R7.L , 0x1 );
 120         CC = AC0;       R7 = CC; DBGA ( R7.L , 0x0 );
 121         CC = AV0;       R7 = CC; DBGA ( R7.L , 0x0 );
 122         CC = AV1;       R7 = CC; DBGA ( R7.L , 0x0 );
 123
 124 // logic
 125 //  right by 15
 126         R7 = 0;
 127         ASTAT = R7;
 128         R0.L = 0x8000;
 129         R0.H = 0x0100;
 130         R1.L = -15;
 131         R6 = LSHIFT R0 BY R1.L (V);
 132         DBGA ( R6.L , 0x0001 );
 133         DBGA ( R6.H , 0x0000 );
 134         CC = AZ;        R7 = CC; DBGA ( R7.L , 0x1 );
 135         CC = AN;        R7 = CC; DBGA ( R7.L , 0x0 );
 136         CC = AC0;       R7 = CC; DBGA ( R7.L , 0x0 );
 137         CC = AV0;       R7 = CC; DBGA ( R7.L , 0x0 );
 138         CC = AV1;       R7 = CC; DBGA ( R7.L , 0x0 );
 139
 140         pass