sim/testsuite/sim/bfin/se_cc2stat_haz.S

   1 //Original:/proj/frio/dv/testcases/seq/se_cc2stat_haz/se_cc2stat_haz.dsp
   2 // Description:
   3 //   Verify CC hazards under the following condition:
   4 //
   5 //      (1a) cc2stat (that modifies CC) followed by  that uses CC
   6 //      (1b) same as (1a) but kill cc2stat instruction in WB
   7 //
   8 //      (2a) cc2stat (that modifies CC) followed by conditional branch (predicted)
   9 //      (2b) same as (2a) but kill cc2stat instruction in WB
  10 //
  11 //      (3a) cc2stat (that modifies CC) followed by conditional branch (mispredicted)
  12 //      (3b) same as (3a) but kill cc2stat instruction in WB
  13 //
  14 //      (4a) cc2stat (that modifies CC) followed by testset
  15 //      (4b) same as (4a) but kill cc2stat instruction in WB
  16 //
  17 //      (5a) cc2stat (that modifies CC) followed by dag instruction that modifies CC
  18 //      (5b) same as (5a) but kill cc2stat instruction in WB
  19 # mach: bfin
  20 # sim: --environment operating
  21
  22 #include "test.h"
  23 .include "testutils.inc"
  24 start
  25
  26 // ----------------------------------------------------------------
  27 //   Include Files
  28 // ----------------------------------------------------------------
  29
  30 include(std.inc)
  31 include(selfcheck.inc)
  32 include(symtable.inc)
  33 include(mmrs.inc)
  34
  35 // ----------------------------------------------------------------
  36 //   Defines
  37 // ----------------------------------------------------------------
  38
  39 #ifndef STACKSIZE
  40 #define STACKSIZE     0x00000010
  41 #endif
  42 #ifndef ITABLE
  43 #define ITABLE        CODE_ADDR_1   //
  44 #endif
  45
  46 // ----------------------------------------------------------------
  47 //   Reset ISR
  48 //      - set the processor operating modes
  49 //      - initialize registers
  50 //      - etc ...
  51 // ----------------------------------------------------------------
  52
  53 RST_ISR:
  54
  55     // Initialize data registers
  56     //INIT_R_REGS(0);
  57     R7 = 0;
  58     R6 = 0;
  59     R5 = 0;
  60     R4 = 0;
  61     R3 = 0;
  62     R2 = 0;
  63     R1 = 0;
  64     R0 = 0;
  65
  66     // Initialize pointer registers
  67 INIT_P_REGS(0);
  68
  69     // Initialize address registers
  70 INIT_I_REGS(0);
  71 INIT_M_REGS(0);
  72 INIT_L_REGS(0);
  73 INIT_B_REGS(0);
  74
  75     // Initialize the address of the checkreg data segment
  76     // **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
  77 CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
  78
  79     // Inhibit events during MMR writes
  80 CLI R1;
  81
  82     // Setup user stack
  83 LD32_LABEL(sp, USTACK);
  84 USP = SP;
  85
  86     // Setup kernel stack
  87 LD32_LABEL(sp, KSTACK);
  88
  89     // Setup frame pointer
  90 FP = SP;
  91
  92     // Setup event vector table
  93 LD32(p0, EVT0);
  94
  95 LD32_LABEL(r0, EMU_ISR);    // Emulation Handler (EVT0)
  96     [ P0 ++ ] = R0;
  97 LD32_LABEL(r0, RST_ISR);    // Reset Handler (EVT1)
  98     [ P0 ++ ] = R0;
  99 LD32_LABEL(r0, NMI_ISR);    // NMI Handler (EVT2)
 100     [ P0 ++ ] = R0;
 101 LD32_LABEL(r0, EXC_ISR);    // Exception Handler (EVT3)
 102     [ P0 ++ ] = R0;
 103     [ P0 ++ ] = R0;                // EVT4 not used
 104 LD32_LABEL(r0, HWE_ISR);    // HW Error Handler (EVT5)
 105     [ P0 ++ ] = R0;
 106 LD32_LABEL(r0, TMR_ISR);    // Timer Handler (EVT6)
 107     [ P0 ++ ] = R0;
 108 LD32_LABEL(r0, IGV7_ISR);   // IVG7 Handler
 109     [ P0 ++ ] = R0;
 110 LD32_LABEL(r0, IGV8_ISR);   // IVG8 Handler
 111     [ P0 ++ ] = R0;
 112 LD32_LABEL(r0, IGV9_ISR);   // IVG9 Handler
 113     [ P0 ++ ] = R0;
 114 LD32_LABEL(r0, IGV10_ISR);  // IVG10 Handler
 115     [ P0 ++ ] = R0;
 116 LD32_LABEL(r0, IGV11_ISR);  // IVG11 Handler
 117     [ P0 ++ ] = R0;
 118 LD32_LABEL(r0, IGV12_ISR);  // IVG12 Handler
 119     [ P0 ++ ] = R0;
 120 LD32_LABEL(r0, IGV13_ISR);  // IVG13 Handler
 121     [ P0 ++ ] = R0;
 122 LD32_LABEL(r0, IGV14_ISR);  // IVG14 Handler
 123     [ P0 ++ ] = R0;
 124 LD32_LABEL(r0, IGV15_ISR);  // IVG15 Handler
 125     [ P0 ++ ] = R0;
 126
 127     // Set the EVT_OVERRIDE MMR
 128 LD32(p0, EVT_OVERRIDE);
 129     R0 = 0;
 130     [ P0 ++ ] = R0;
 131
 132     // Disable L1 data cache
 133 WR_MMR(DMEM_CONTROL, 0x00000000, p0, r0);
 134
 135     // Mask interrupts (*)
 136     R1 = -1;
 137
 138     // Wait for MMR writes to finish
 139 CSYNC;
 140
 141     // Re-enable events
 142 STI R1;
 143
 144     // Reset accumulator registers
 145     A0 = 0;
 146     A1 = 0;
 147
 148     // Reset loop counters to deterministic values
 149     R0 = 0 (Z);
 150
 151 LT0 = R0;
 152 LB0 = R0;
 153 LC0 = R0;
 154 LT1 = R0;
 155 LB1 = R0;
 156 LC1 = R0;
 157
 158     // Reset other internal regs
 159 ASTAT = R0;
 160 SYSCFG = R0;
 161 RETS = R0;
 162
 163     // Setup the test to run in USER mode
 164 LD32_LABEL(r0, USER_CODE);
 165 RETI = R0;
 166
 167     // Setup the test to run in SUPERVISOR mode
 168     // Comment the following line for a USER mode test
 169 JUMP.S SUPERVISOR_CODE;
 170 RTI;
 171
 172 SUPERVISOR_CODE:
 173     // Load IVG15 general handler (Int15) with MAIN_CODE
 174 LD32_LABEL(p1, MAIN_CODE);
 175
 176 LD32(p0, EVT15);
 177
 178 CLI R1;
 179     [ P0 ] = P1;
 180 CSYNC;
 181 STI R1;
 182
 183     // Take Int15 which branch to MAIN_CODE after RTI
 184 RAISE 15;
 185 RTI;
 186
 187 USER_CODE:
 188     // Setup the stack pointer and the frame pointer
 189 LD32_LABEL(sp, USTACK);
 190 FP = SP;
 191 JUMP.S MAIN_CODE;
 192
 193 .dw 0xFFFF
 194 .dw 0xFFFF
 195 .dw 0xFFFF
 196 .dw 0xFFFF
 197 .dw 0xFFFF
 198 .dw 0xFFFF
 199 .dw 0xFFFF
 200
 201 // ----------------------------------------------------------------
 202 //   ISR Table
 203 // ----------------------------------------------------------------
 204
 205
 206 // ----------------------------------------------------------------
 207 //   EMU ISR
 208 // ----------------------------------------------------------------
 209
 210  EMU_ISR :
 211
 212 RTE;
 213
 214 .dw 0xFFFF
 215 .dw 0xFFFF
 216 .dw 0xFFFF
 217 .dw 0xFFFF
 218 .dw 0xFFFF
 219 .dw 0xFFFF
 220 .dw 0xFFFF
 221
 222 // ----------------------------------------------------------------
 223 //   NMI ISR
 224 // ----------------------------------------------------------------
 225
 226  NMI_ISR :
 227
 228 RTN;
 229
 230 .dw 0xFFFF
 231 .dw 0xFFFF
 232 .dw 0xFFFF
 233 .dw 0xFFFF
 234 .dw 0xFFFF
 235 .dw 0xFFFF
 236 .dw 0xFFFF
 237
 238 // ----------------------------------------------------------------
 239 //   EXC ISR
 240 // ----------------------------------------------------------------
 241
 242  EXC_ISR :
 243
 244 RTX;
 245
 246 .dw 0xFFFF
 247 .dw 0xFFFF
 248 .dw 0xFFFF
 249 .dw 0xFFFF
 250 .dw 0xFFFF
 251 .dw 0xFFFF
 252 .dw 0xFFFF
 253
 254 // ----------------------------------------------------------------
 255 //   HWE ISR
 256 // ----------------------------------------------------------------
 257
 258  HWE_ISR :
 259
 260 RTI;
 261
 262 .dw 0xFFFF
 263 .dw 0xFFFF
 264 .dw 0xFFFF
 265 .dw 0xFFFF
 266 .dw 0xFFFF
 267 .dw 0xFFFF
 268 .dw 0xFFFF
 269
 270 // ----------------------------------------------------------------
 271 //   TMR ISR
 272 // ----------------------------------------------------------------
 273
 274  TMR_ISR :
 275
 276 RTI;
 277
 278 .dw 0xFFFF
 279 .dw 0xFFFF
 280 .dw 0xFFFF
 281 .dw 0xFFFF
 282 .dw 0xFFFF
 283 .dw 0xFFFF
 284 .dw 0xFFFF
 285
 286 // ----------------------------------------------------------------
 287 //   IGV7 ISR
 288 // ----------------------------------------------------------------
 289
 290  IGV7_ISR :
 291
 292 RTI;
 293
 294 .dw 0xFFFF
 295 .dw 0xFFFF
 296 .dw 0xFFFF
 297 .dw 0xFFFF
 298 .dw 0xFFFF
 299 .dw 0xFFFF
 300 .dw 0xFFFF
 301
 302 // ----------------------------------------------------------------
 303 //   IGV8 ISR
 304 // ----------------------------------------------------------------
 305
 306  IGV8_ISR :
 307
 308 RTI;
 309
 310 .dw 0xFFFF
 311 .dw 0xFFFF
 312 .dw 0xFFFF
 313 .dw 0xFFFF
 314 .dw 0xFFFF
 315 .dw 0xFFFF
 316 .dw 0xFFFF
 317
 318 // ----------------------------------------------------------------
 319 //   IGV9 ISR
 320 // ----------------------------------------------------------------
 321
 322  IGV9_ISR :
 323
 324 RTI;
 325
 326 .dw 0xFFFF
 327 .dw 0xFFFF
 328 .dw 0xFFFF
 329 .dw 0xFFFF
 330 .dw 0xFFFF
 331 .dw 0xFFFF
 332 .dw 0xFFFF
 333
 334 // ----------------------------------------------------------------
 335 //   IGV10 ISR
 336 // ----------------------------------------------------------------
 337
 338  IGV10_ISR :
 339
 340 RTI;
 341
 342 .dw 0xFFFF
 343 .dw 0xFFFF
 344 .dw 0xFFFF
 345 .dw 0xFFFF
 346 .dw 0xFFFF
 347 .dw 0xFFFF
 348 .dw 0xFFFF
 349
 350 // ----------------------------------------------------------------
 351 //   IGV11 ISR
 352 // ----------------------------------------------------------------
 353
 354  IGV11_ISR :
 355
 356 RTI;
 357
 358 .dw 0xFFFF
 359 .dw 0xFFFF
 360 .dw 0xFFFF
 361 .dw 0xFFFF
 362 .dw 0xFFFF
 363 .dw 0xFFFF
 364 .dw 0xFFFF
 365
 366 // ----------------------------------------------------------------
 367 //   IGV12 ISR
 368 // ----------------------------------------------------------------
 369
 370  IGV12_ISR :
 371
 372 RTI;
 373
 374 .dw 0xFFFF
 375 .dw 0xFFFF
 376 .dw 0xFFFF
 377 .dw 0xFFFF
 378 .dw 0xFFFF
 379 .dw 0xFFFF
 380 .dw 0xFFFF
 381
 382 // ----------------------------------------------------------------
 383 //   IGV13 ISR
 384 // ----------------------------------------------------------------
 385
 386  IGV13_ISR :
 387
 388 RTI;
 389
 390 .dw 0xFFFF
 391 .dw 0xFFFF
 392 .dw 0xFFFF
 393 .dw 0xFFFF
 394 .dw 0xFFFF
 395 .dw 0xFFFF
 396 .dw 0xFFFF
 397
 398 // ----------------------------------------------------------------
 399 //   IGV14 ISR
 400 // ----------------------------------------------------------------
 401
 402  IGV14_ISR :
 403
 404 RTI;
 405
 406 .dw 0xFFFF
 407 .dw 0xFFFF
 408 .dw 0xFFFF
 409 .dw 0xFFFF
 410 .dw 0xFFFF
 411 .dw 0xFFFF
 412 .dw 0xFFFF
 413
 414 // ----------------------------------------------------------------
 415 //   IGV15 ISR
 416 // ----------------------------------------------------------------
 417
 418  IGV15_ISR :
 419
 420 RTI;
 421
 422 .dw 0xFFFF
 423 .dw 0xFFFF
 424 .dw 0xFFFF
 425 .dw 0xFFFF
 426 .dw 0xFFFF
 427 .dw 0xFFFF
 428 .dw 0xFFFF
 429
 430 // ----------------------------------------------------------------
 431 //   Main Code
 432 // ----------------------------------------------------------------
 433
 434
 435 MAIN_CODE:
 436     // Enable interrupts in SUPERVISOR mode
 437     // Comment the following line for a USER mode test
 438     [ -- SP ] = RETI;
 439
 440     // Start of the program code
 441     R0 = 0;
 442     R1 = 1;
 443     R2 = 2;
 444
 445     //   Verify CC hazards under the following condition:
 446     //
 447     //      (1a) cc2stat (that modifies CC) followed by  that uses CC
 448     A0 = 0;
 449     A1 = R1;
 450 CC = R0 < R2;
 451 CC = AV0;
 452     A0 = BXORSHIFT( A0 , A1, CC );
 453     R7 = CC;   CHECKREG(R7, 0);
 454     R6 = A0;   CHECKREG(R6, 0);
 455     R6 = A0.X; CHECKREG(R6, 0);
 456     R7 = A1;   CHECKREG(R7, 1);
 457     R7 = A1.X; CHECKREG(R7, 0);
 458
 459     //      (1b) same as (1a) but kill cc2stat instruction in WB
 460     A0 = R1;
 461     A1 = R1;
 462 CC = R0 < R2;
 463 EXCPT 3;
 464 CC = AV0;
 465     A0 = BXORSHIFT( A0 , A1, CC );
 466     R7 = CC;   CHECKREG(R7, 0);
 467     R6 = A0;   CHECKREG(R6, 3);
 468     R6 = A0.X; CHECKREG(R6, 0);
 469     R7 = A1;   CHECKREG(R7, 1);
 470     R7 = A1.X; CHECKREG(R7, 0);
 471
 472     //      (2a) cc2stat (that modifies CC) followed by conditional branch (predicted)
 473     R3 = 0;
 474     A0 = 0;
 475     A1 = R1;
 476 CC = R0 < R2;
 477 CC = AV0;
 478 IF !CC JUMP INC_R3_TO_10 (BP);
 479     R3 += 2;
 480     R3 += 2;
 481     R3 += 2;
 482     R3 += 2;
 483     R3 += 2;
 484     R3 += 2;
 485     R3 += 2;
 486     R3 += 2;
 487     R3 += 2;
 488     R3 += 2;
 489 INC_R3_TO_10:
 490     R3 += 1;
 491     R3 += 1;
 492     R3 += 1;
 493     R3 += 1;
 494     R3 += 1;
 495     R3 += 1;
 496     R3 += 1;
 497     R3 += 1;
 498     R3 += 1;
 499     R3 += 1;
 500
 501     //      (2b) same as (2a) but kill cc2stat instruction in WB
 502     A0 = 0;
 503     A1 = R1;
 504 CC = R0 < R2;
 505 EXCPT 3;
 506 CC = AV0;
 507 IF !CC JUMP INC_R3_TO_20 (BP);
 508     R3 += 2;
 509     R3 += 2;
 510     R3 += 2;
 511     R3 += 2;
 512     R3 += 2;
 513     R3 += 2;
 514     R3 += 2;
 515     R3 += 2;
 516     R3 += 2;
 517     R3 += 2;
 518 INC_R3_TO_20:
 519     R3 += 1;
 520     R3 += 1;
 521     R3 += 1;
 522     R3 += 1;
 523     R3 += 1;
 524     R3 += 1;
 525     R3 += 1;
 526     R3 += 1;
 527     R3 += 1;
 528     R3 += 1;
 529
 530     //      (3a) cc2stat (that modifies CC) followed by conditional branch (mispredicted)
 531     A0 = 0;
 532     A1 = R1;
 533 CC = R0 < R2;
 534 CC = AV0;
 535 IF CC JUMP INC_R3_TO_20 (BP);
 536     R3 += 2;
 537     R3 += 2;
 538     R3 += 2;
 539     R3 += 2;
 540     R3 += 2;
 541     R3 += 2;
 542     R3 += 2;
 543     R3 += 2;
 544     R3 += 2;
 545     R3 += 2;
 546
 547     //      (3b) same as (3a) but kill cc2stat instruction in WB
 548     A0 = 0;
 549     A1 = R1;
 550 CC = R0 < R2;
 551 EXCPT 3;
 552 CC = AV0;
 553 IF CC JUMP INC_R3_TO_20 (BP);
 554     R3 += 2;
 555     R3 += 2;
 556     R3 += 2;
 557     R3 += 2;
 558     R3 += 2;
 559     R3 += 2;
 560     R3 += 2;
 561     R3 += 2;
 562     R3 += 2;
 563     R3 += 2;
 564
 565 CHECKREG(r3, 60);
 566
 567 dbg_pass;
 568
 569     //      (4a) cc2stat (that modifies CC) followed by testset
 570 LD32(p0, DATA_ADDR_3);  //LD32(p0, 0xff000000);
 571 LD32(p1, DATA_ADDR_2);  //LD32(p1, 0xffe00000);
 572     [ P0 ] = R0;
 573
 574     A0 = 0;
 575     A1 = R1;
 576 CC = R0 < R2;
 577 CC = AV0;
 578 QUERY_0:
 579 TESTSET ( P0 );
 580 IF !CC JUMP QUERY_0;
 581     [ P0 ] = R1;
 582 CHECKMEM32(DATA_ADDR_3, 1);  //CHECKMEM32(0xff000000, 1);
 583     [ P0 ] = R0;
 584 CHECKMEM32(DATA_ADDR_3, 0);  //CHECKMEM32(0xff000000, 0);
 585
 586     //      (4b) same as (4a) but kill cc2stat instruction in WB
 587     A0 = 0;
 588     A1 = R1;
 589 CC = R0 < R2;
 590 EXCPT 3;
 591 CC = AV0;
 592 QUERY_1:
 593 TESTSET ( P0 );
 594 IF !CC JUMP QUERY_1;
 595     [ P0 ] = R2;
 596 CHECKMEM32(DATA_ADDR_3, 2);  //CHECKMEM32(0xff000000, 2);
 597     [ P0 ] = R0;
 598 CHECKMEM32(DATA_ADDR_3, 0);  //CHECKMEM32(0xff000000, 0);
 599
 600     //      (5a) cc2stat (that modifies CC) followed by dag instruction that modifies CC
 601     A0 = 0;
 602     A1 = R1;
 603 CC = R0 < R2;
 604 CC = AV0;
 605 CC = P0 < P1;
 606
 607     //      (5b) same as (5a) but kill cc2stat instruction in WB
 608     A0 = 0;
 609     A1 = R1;
 610 CC = R0 < R2;
 611 EXCPT 3;
 612 CC = AV0;
 613 CC = P0 < P1;
 614
 615
 616 END:
 617 dbg_pass;
 618
 619 // ----------------------------------------------------------------
 620 //   Data Segment
 621 //      - define kernel and user stacks
 622 // ----------------------------------------------------------------
 623
 624 .data
 625     DATA:
 626     .space (STACKSIZE);
 627
 628     .space (STACKSIZE);
 629     KSTACK:
 630
 631     .space (STACKSIZE);
 632     USTACK: