1 //Original:/proj/frio/dv/testcases/seq/se_illegalcombination/se_illegalcombination.dsp
2 // Description: Multi-issue Illegal Combinations
4 # sim: --environment operating
5 # xfail: "missing a few checks; hardware doesnt seem to match PRM?" bfin-*
8 .include "testutils.inc"
12 // Constants and Defines
16 include(selfcheck.inc)
22 #define STACKSIZE 0x100 // change for how much stack you need
25 #define ITABLE 0xF0000000
28 GEN_INT_INIT(ITABLE) // set location for interrupt table
31 // Reset/Bootstrap Code
32 // (Here we should set the processor operating modes, initialize registers,
37 INIT_R_REGS(0); // initialize general purpose regs
39 INIT_P_REGS(0); // initialize the pointers
41 INIT_I_REGS(0); // initialize the dsp address regs
46 CLI R1; // inhibit events during MMR writes
48 LD32_LABEL(sp, USTACK); // setup the user stack pointer
51 LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer
52 FP = SP; // and frame pointer
54 LD32(p0, EVT0); // Setup Event Vectors and Handlers
56 P0 += 4; // EVT0 not used (Emulation)
58 P0 += 4; // EVT1 not used (Reset)
60 LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
63 LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
66 P0 += 4; // EVT4 not used (Global Interrupt Enable)
68 LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
71 LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
74 LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
77 LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
80 LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
83 LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
86 LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
89 LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
92 LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
95 LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
98 LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
101 LD32(p0, EVT_OVERRIDE);
105 R1 = -1; // Change this to mask interrupts (*)
106 CSYNC; // wait for MMR writes to finish
107 STI R1; // sync and reenable events (implicit write to IMASK)
111 A0 = 0; // reset accumulators
116 LT0 = r0; // set loop counters to something deterministic
123 ASTAT = r0; // reset other internal regs
125 RETS = r0; // prevent X's breaking LINK instruction
127 // The following code sets up the test for running in USER mode
129 LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
130 // ReturnFromInterrupt (RTI)
131 RETI = r0; // We need to load the return address
133 // Comment the following line for a USER Mode test
135 JUMP STARTSUP; // jump to code start for SUPERVISOR mode
140 LD32_LABEL(p1, BEGIN);
144 CLI R1; // inhibit events during write to MMR
145 [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
146 CSYNC; // wait for it
147 STI R1; // reenable events with proper imask
149 RAISE 15; // after we RTI, INT 15 should be taken
159 LINK 0; // change for how much stack frame space you need.
163 //*********************************************************************
167 // COMMENT the following line for USER MODE tests
168 [ -- SP ] = RETI; // enable interrupts in supervisor mode
170 // **** YOUR CODE GOES HERE ****
172 // PUT YOUR TEST HERE!
174 // Slot 0 can only be LDST LOAD with search instruction (2 instrs)
177 .dw 0xcc0d //(R0,R1)=SEARCH R2(GT)||[P0]=R3||NOP;
181 // (r0,r1) = search r2 gt, nop, r3 = [i0]; // nop supposedly ok
182 ( R0 , R1 ) = SEARCH R2 (GT) || R4 = [ P0 ++ P1 ] || NOP;
184 // only nop or dspLDST allowed in slot 1 (1 instr)
186 // a0 = r0, nop, [p0] = r3;
187 .dw 0xCC09; // can't assemble
192 // Slot 0 illegal opcodes (1 instr)
194 // a0 = r0, raise 15, nop;
195 .dw 0xCC09; // can't assemble
200 // multiissue with two stores (8 instrs)
203 .dw 0xcc09 //A0=R0||W[P3]=R5.L||[I0]=R4;
208 .dw 0xcc09 //A0=R0||[I2]=R2||[I0]=R4;
213 .dw 0xcc09 //A0=R0||[P3]=R0||[I0]=R4;
218 .dw 0xcc09 //A0=R0||[P3]=P0||[I0]=R4;
223 .dw 0xcc09 //A0=R0||[FP+-36]=R0||[I0]=R4;
228 .dw 0xcc09 //A0=R0||[FP+-48]=P0||[I0]=R4;
233 .dw 0xcc09 //A0=R0||[P3+0x20]=R1||[I0]=R4;
238 .dw 0xcc09 //A0=R0||[P3+0x20]=P1||[I0]=R4;
243 // multiissue two instructions can't modify same ireg (6 instrs)
246 .dw 0xcc09 //A0=R0||I0+=M1(BREV)||R1.L=W[I0++];
251 .dw 0xcc09 //A0=R0||I1-=M3||R0=[I1++M3];
256 .dw 0xcc09 //A0=R0||I2+=2||W[I2++]=R0.L;
261 .dw 0xcc09 //A0=R0||I3-=4||[I3++M1]=R7;
266 .dw 0xcc09 //A0=R0||R1.L=W[I1++]||W[I1++]=R2.L;
271 .dw 0xcc09 //A0=R0||[I2++M3]=R7||R6=[I2++M0];
276 // multiissue two instructions can't load same dreg (9 instrs)
279 .dw 0xcc09 //A0=R0||R0.L=W[P0++P2]||R0=[I0++];
284 .dw 0xcc09 //A0=R0||R1=W[P0++P3](X)||R1.L=W[I2];
289 .dw 0xcc09 //A0=R0||R2=W[P0++P3](X)||R2=[I1++M3];
294 .dw 0xcc09 //A0=R0||R3=[I0++]||R3=[I1++];
299 .dw 0xcc09 //A0=R0||R4.L=W[I2]||R4.L=W[I3];
304 .dw 0xcc09 //A0=R0||R5=[I1++M3]||R5.L=W[I2++];
309 .dw 0xcc09 //A0=R0||R6=[P0]||R6=[I0++];
314 .dw 0xcc09 //A0=R0||R7=[FP+-56]||R7.L=W[I1];
319 .dw 0xcc09 //A0=R0||R0=W[P1+0x1e](X)||R0=[I0++];
324 // dsp32alu instructions with one dest and slot 0 multi with same dest (1 ins)
327 .dw 0xcc00 //R0=R2+|+R3||R0=W[P1+0x1e](X)||NOP;
331 // other slot 0 dreg cases already covered
333 // dsp32alu one dest and slot 1 multi with same dest (1 ins)
336 .dw 0xcc18 //R1=BYTEPACK(R4,R5)||NOP||R1.L=W[I2];
340 // other slot 1 dreg dest cases already covered
342 // dsp32alu dual dests and slot 0 multi with either same dest (2 instrs)
345 .dw 0xcc18 //(R2,R3)=BYTEUNPACKR1:0||R2=W[P0++P3](X)||NOP;
350 .dw 0xcc01 //R2=R2+|+R3,R3=R2-|-R3||R3=[P3]||NOP;
355 // dsp32alu dual dests and slot 1 multi with either same dest (2 instrs)
358 .dw 0xcc18 //(R4,R5)=BYTEUNPACKR1:0||NOP||R4=[I1++M3];
363 .dw 0xcc01 //R4=R2+|+R3,R5=R2-|-R3||NOP||R5.L=W[I2++];
368 // dsp32shift one dest and slot 0 multi with same dest (1 instruction)
371 .dw 0xce0d //R6=ALIGN8(R4,R5)||R6=[P0]||NOP;
376 // dsp32shift one dest and slot 1 multi with same dest (1 instruction)
379 .dw 0xce00 //R7.L=ASHIFTR0.HBYR7.L||NOP||R7.L=W[I1];
384 // dsp32shift two dests and slot 0 multi with either same dest (2 instrs)
387 .dw 0xce08 //BITMUX(R0,R1,A0)(ASR)||R0.L=W[P0++P2]||NOP;
392 .dw 0xce08 //BITMUX(R2,R3,A0)(ASL)||R3=[I0++]||NOP;
397 // dsp32shift two dests and slot 1 multi with either same dest (2 instrs)
400 .dw 0xce08 //BITMUX(R4,R5,A0)(ASR)||NOP||R4.H=W[I3];
405 .dw 0xce08 //BITMUX(R6,R7,A0)(ASL)||NOP||R7.L=W[I1];
410 // dsp32shiftimm one dest and slot 0 with same dest (1 instr)
413 .dw 0xce80 //R1.L=R0.H<<0x7||R1=W[P0++P3](X)||NOP;
418 // dsp32shiftimm one dest and slot 1 with same dest (1 instr)
421 .dw 0xce81 //R5=R2<<0x9(V)||NOP||R5.L=W[I2++];
426 // dsp32mac one dest and slot 0 multi with same dest (1 inst)
429 .dw 0xc805 //A0+=R1.H*R0.L,R6.H=(A1+=R1.L*R0.H)||R6=W[P0++P3](X)||NOP;
434 // dsp32mult one dest and slot 0 multi with same dest (1 inst)
437 .dw 0xca04 //R7.H=R3.L*R4.H||R7=[FP+-56]||NOP;
442 // dsp32 mac one dest and slot 1 multi with same dest (1 inst)
445 .dw 0xc805 //A0+=R1.H*R0.L,R0.H=(A1+=R1.L*R0.H)||NOP||R0=[I0++];
450 // dsp32mult one dest and slot 1 multi with same dest (1 inst)
453 .dw 0xca04 //R1.H=R3.L*R4.H||NOP||R1.H=W[I1];
458 // dsp32mac write to register pair and slot 0 same dest - even (1 instr)
461 .dw 0xc80d //R3=(A1+=R1.L*R0.H),R2=(A0+=R1.H*R0.L)||R2=W[P0++P3](X)||NOP;
466 // dsp32mult write to register pair and slot 0 same dest - even (1 instr)
469 .dw 0xca0c //R5=R1.L*R0.H,R4=R1.H*R0.L||R4=[P0++P1]||NOP;
474 // dsp32mac write to register pair and slot 1 same dest - even (1 instr)
477 .dw 0xc80d //R3=(A1+=R1.L*R0.H),R2=(A0+=R1.H*R0.L)||NOP||R2=[I1++M3];
482 // dsp32mult write to register pair and slot 1 same dest - even (1 instr)
485 .dw 0xca0c //R5=R1.L*R0.H,R4=R1.H*R0.L||NOP||R4=[I1++M3];
490 // dsp32mac write to register pair and slot 0 same dest - odd (1 instr)
493 .dw 0xc80d //A0+=R1.H*R0.L,R3=(A1+=R1.L*R0.H)||R3=W[P0++P3](X)||NOP;
498 // dsp32mult write to register pair and slot 0 same dest - odd (1 instr)
501 .dw 0xca0c //R5=R1.L*R0.H,R4=R1.H*R0.L||R5=[P0++P1]||NOP;
506 // dsp32mac write to register pair and slot 1 same dest - odd (1 instr)
509 .dw 0xc80d //A0+=R1.H*R0.L,R3=(A1+=R1.L*R0.H)||NOP||R3=[I1++M3];
514 // dsp32mult write to register pair and slot 1 same dest - odd (1 instr)
517 .dw 0xca0c //R5=R1.L*R0.H,R4=R1.H*R0.L||NOP||R5=[I1++M3];
524 CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC);
525 // Xhandler counts all EXCAUSE = 0x22;
526 CHECKREG(r5, 53); // count of all Illegal Combination Exceptions.
529 dbg_pass; // End the test
531 //*********************************************************************
534 // Handlers for Events
537 NHANDLE: // NMI Handler 2
540 XHANDLE: // Exception Handler 3
541 // 16 bit illegal opcode handler - skips bad instruction
543 [ -- SP ] = ASTAT; // save what we damage
544 [ -- SP ] = ( R7:6 );
547 R7 >>= 26; // only want EXCAUSE
548 R6 = 0x22; // EXCAUSE 0x22 means I-Fetch Undefined Instruction
550 IF CC JUMP ILLEGALCOMBINATION; // If EXCAUSE != 0x22 then leave
553 JUMP.S OUT; // if the EXCAUSE is wrong the test will infinite loop
556 R7 = RETX; // Fix up return address
558 R7 += 8; // skip offending 64 bit instruction
560 RETX = r7; // and put back in RETX
562 R5 += 1; // Increment global counter
565 ( R7:6 ) = [ SP ++ ];
570 HWHANDLE: // HW Error Handler 5
573 THANDLE: // Timer Handler 6
576 I7HANDLE: // IVG 7 Handler
579 I8HANDLE: // IVG 8 Handler
582 I9HANDLE: // IVG 9 Handler
585 I10HANDLE: // IVG 10 Handler
588 I11HANDLE: // IVG 11 Handler
591 I12HANDLE: // IVG 12 Handler
594 I13HANDLE: // IVG 13 Handler
597 I14HANDLE: // IVG 14 Handler
600 I15HANDLE: // IVG 15 Handler
604 // padding for the icache
606 EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0;
616 // Stack Segments (Both Kernel and User)