sim/testsuite/sim/bfin/x1.s

   1 # mach: bfin
   2
   3 .include "testutils.inc"
   4         start
   5
   6
   7 // 0.5
   8         imm32 r0, 0x40004000;
   9         imm32 r1, 0x40004000;
  10         R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR);
  11         checkreg r2, 0x40004000;
  12         checkreg r3, 0;
  13
  14         imm32 r1, 0x10001000;
  15
  16         R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR);
  17         checkreg r2, 0x28002800;
  18         checkreg r3, 0x18001800;
  19
  20         R0 = R2 +|+ R3, R1 = R2 -|- R3 (S , ASR);
  21         checkreg r0, 0x20002000;
  22         checkreg r1, 0x08000800;
  23
  24         R0 = 1;
  25         R0 <<= 15;
  26         R1 = R0 << 16;
  27         R0 = R0 | R1;
  28         R1 = R0;
  29         checkreg r0, 0x80008000;
  30         checkreg r1, 0x80008000;
  31
  32         R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR);
  33         checkreg r2, 0x80008000;
  34         checkreg r3, 0x0;
  35
  36         R4 = 0;
  37         R2 = R2 +|+ R4, R3 = R2 -|- R4 (S , ASR);
  38         checkreg r2, 0xc000c000;
  39         checkreg r3, 0xc000c000;
  40
  41         R2 = R2 +|+ R3, R3 = R2 -|- R3 (S , ASR);
  42         checkreg r2, 0xc000c000;
  43         checkreg r3, 0x0;
  44
  45         R4 = R2 +|+ R2, R5 = R2 -|- R2 (ASL);
  46         checkreg r4, 0x0
  47         checkreg r5, 0x0
  48
  49         R2 = R2 +|+ R2, R3 = R2 -|- R2 (S , ASL);
  50         checkreg r2, 0x80008000;
  51         checkreg r3, 0x0;
  52
  53
  54 imm32 r0, 0x50004000;
  55 imm32 r1, 0x40005000;
  56 R2 = R0 +|+ R1, R3 = R0 -|- R1 (S, ASL);
  57 checkreg r2, 0x7fff7fff;
  58 checkreg r3, 0x2000e000;
  59 R4 = R0 +|+ R1, R5 = R0 -|- R1 (ASL);
  60 checkreg r4, 0x20002000
  61 checkreg r5, 0x2000e000
  62
  63 imm32 r0, 0x30001000;
  64 imm32 r1, 0x10003000;
  65 R2 = R0 +|+ R1, R3 = R0 -|- R1 (S, ASL);
  66 checkreg r2, 0x7fff7fff;
  67 checkreg r3, 0x4000c000;
  68 R4 = R0 +|+ R1, R5 = R0 -|- R1 (ASL);
  69 checkreg r4, 0x80008000
  70 checkreg r5, 0x4000c000
  71
  72 imm32 r0, 0x20001fff;
  73 imm32 r1, 0x1fff2000;
  74 R2 = R0 +|+ R1, R3 = R0 -|- R1 (S, ASL);
  75 checkreg r2, 0x7ffe7ffe;
  76 checkreg r3, 0x0002fffe;
  77
  78
  79         pass