sim/testsuite/sim/fr30/asr.cgs

   1 # fr30 testcase for asr $Rj,$Ri, asr $u4,$Rj
   2 # mach(): fr30
   3
   4         .include "testutils.inc"
   5
   6         START
   7
   8         .text
   9         .global asr
  10 asr:
  11         ; Test asr $Rj,$Ri
  12         mvi_h_gr        0xdeadbee0,r7   ; Shift by 0
  13         mvi_h_gr        0x80000000,r8
  14         set_cc          0x05            ; Set mask opposite of expected
  15         asr             r7,r8
  16         test_cc         1 0 0 0
  17         test_h_gr       0x80000000,r8
  18
  19         mvi_h_gr        0xdeadbee1,r7   ; Shift by 1
  20         mvi_h_gr        0x80000000,r8
  21         set_cc          0x07            ; Set mask opposite of expected
  22         asr             r7,r8
  23         test_cc         1 0 1 0
  24         test_h_gr       0xc0000000,r8
  25
  26         mvi_h_gr        0xdeadbeff,r7   ; Shift by 31
  27         mvi_h_gr        0x80000000,r8
  28         set_cc          0x07            ; Set mask opposite of expected
  29         asr             r7,r8
  30         test_cc         1 0 1 0
  31         test_h_gr       -1,r8
  32
  33         mvi_h_gr        0xdeadbeff,r7   ; clear register
  34         mvi_h_gr        0x40000000,r8
  35         set_cc          0x0a            ; Set mask opposite of expected
  36         asr             r7,r8
  37         test_cc         0 1 1 1
  38         test_h_gr       0x00000000,r8
  39
  40         ; Test asr $u4Ri
  41         mvi_h_gr        0x80000000,r8
  42         set_cc          0x05            ; Set mask opposite of expected
  43         asr             0,r8
  44         test_cc         1 0 0 0
  45         test_h_gr       0x80000000,r8
  46
  47         mvi_h_gr        0x80000000,r8
  48         set_cc          0x07            ; Set mask opposite of expected
  49         asr             1,r8
  50         test_cc         1 0 1 0
  51         test_h_gr       0xc0000000,r8
  52
  53         mvi_h_gr        0x80000000,r8
  54         set_cc          0x07            ; Set mask opposite of expected
  55         asr             15,r8
  56         test_cc         1 0 1 0
  57         test_h_gr       0xffff0000,r8
  58
  59         mvi_h_gr        0x00004000,r8
  60         set_cc          0x0a            ; Set mask opposite of expected
  61         asr             15,r8
  62         test_cc         0 1 1 1
  63         test_h_gr       0x00000000,r8
  64
  65         pass