sim/testsuite/sim/fr30/div.ms

   1 # fr30 testcase for division
   2 # mach(): fr30
   3
   4         .include "testutils.inc"
   5
   6         START
   7
   8         .text
   9         .global div
  10 div:
  11         ; example 1 from div0s the manual
  12         mvi_h_gr        0x01234567,r2
  13         mvi_h_dr        0xdeadbeef,mdh
  14         mvi_h_dr        0xfedcba98,mdl
  15         div0s           r2
  16         div1            r2
  17         div1            r2
  18         div1            r2
  19         div1            r2
  20         div1            r2
  21         div1            r2
  22         div1            r2
  23         div1            r2
  24         div1            r2
  25         div1            r2
  26         div1            r2
  27         div1            r2
  28         div1            r2
  29         div1            r2
  30         div1            r2
  31         div1            r2
  32         div1            r2
  33         div1            r2
  34         div1            r2
  35         div1            r2
  36         div1            r2
  37         div1            r2
  38         div1            r2
  39         div1            r2
  40         div1            r2
  41         div1            r2
  42         div1            r2
  43         div1            r2
  44         div1            r2
  45         div1            r2
  46         div1            r2
  47         div1            r2
  48         div2            r2
  49         div3
  50         div4s
  51         test_h_gr       0x01234567,r2
  52         test_h_dr       0xffffffff,mdh
  53         test_h_dr       0xffffffff,mdl
  54         test_dbits      0x3
  55
  56         ; example 2 from div0s the manual
  57         mvi_h_dr        0xdeadbeef,mdh
  58         mvi_h_dr        0xfedcba98,mdl
  59         mvi_h_gr        0x1234567,r2
  60         mvi_h_gr        1,r0
  61         mvi_h_gr        32,r1
  62         div0s           r2
  63 loop1:  sub             r0,r1
  64         bne:d           loop1
  65         div1            r2
  66         div2            r2
  67         div3
  68         div4s
  69         test_h_gr       0x01234567,r2
  70         test_h_dr       0xffffffff,mdh
  71         test_h_dr       0xffffffff,mdl
  72         test_dbits      0x3
  73
  74         ; example 1 from div0u in the manual
  75         mvi_h_gr        0x01234567,r2
  76         mvi_h_dr        0xdeadbeef,mdh
  77         mvi_h_dr        0xfedcba98,mdl
  78         div0u           r2
  79         div1            r2
  80         div1            r2
  81         div1            r2
  82         div1            r2
  83         div1            r2
  84         div1            r2
  85         div1            r2
  86         div1            r2
  87         div1            r2
  88         div1            r2
  89         div1            r2
  90         div1            r2
  91         div1            r2
  92         div1            r2
  93         div1            r2
  94         div1            r2
  95         div1            r2
  96         div1            r2
  97         div1            r2
  98         div1            r2
  99         div1            r2
 100         div1            r2
 101         div1            r2
 102         div1            r2
 103         div1            r2
 104         div1            r2
 105         div1            r2
 106         div1            r2
 107         div1            r2
 108         div1            r2
 109         div1            r2
 110         div1            r2
 111         test_h_gr       0x01234567,r2
 112         test_h_dr       0x00000078,mdh
 113         test_h_dr       0x000000e0,mdl
 114         test_dbits      0x0
 115
 116         ; example 2 from div0u in the manual
 117         mvi_h_dr        0xdeadbeef,mdh
 118         mvi_h_dr        0xfedcba98,mdl
 119         mvi_h_gr        0x1234567,r2
 120         mvi_h_gr        1,r0
 121         mvi_h_gr        32,r1
 122         div0u           r2
 123 loop2:  sub             r0,r1
 124         bne:d           loop2
 125         div1            r2
 126         test_h_gr       0x01234567,r2
 127         test_h_dr       0x00000078,mdh
 128         test_h_dr       0x000000e0,mdl
 129         test_dbits      0x0
 130
 131         pass