sim/testsuite/sim/fr30/div0s.cgs

   1 # fr30 testcase for div0s $Ri
   2 # mach(): fr30
   3
   4         .include "testutils.inc"
   5
   6         START
   7
   8         .text
   9         .global div0s
  10 div0s:
  11         ; Test div0s $Rj,$Ri
  12         ; example from the manual - negative dividend
  13         mvi_h_gr        0x0fffffff,r2
  14         mvi_h_dr        0x00000000,mdh
  15         mvi_h_dr        0xfffffff0,mdl
  16         set_dbits       0x0             ; Set opposite of expected
  17         set_cc          0x0f            ; Condition codes should not change
  18         div0s           r2
  19         test_cc         1 1 1 1
  20         test_h_gr       0x0fffffff,r2
  21         test_h_dr       0xffffffff,mdh
  22         test_h_dr       0xfffffff0,mdl
  23         test_dbits      0x3
  24
  25         ; negative divisor
  26         mvi_h_gr        0xffffffff,r2
  27         mvi_h_dr        0xffffffff,mdh
  28         mvi_h_dr        0x7fffffff,mdl
  29         set_dbits       0x1             ; Set opposite of expected
  30         set_cc          0x0f            ; Condition codes should not change
  31         div0s           r2
  32         test_cc         1 1 1 1
  33         test_h_gr       0xffffffff,r2
  34         test_h_dr       0x00000000,mdh
  35         test_h_dr       0x7fffffff,mdl
  36         test_dbits      0x2
  37
  38         ; Both sign bits 0
  39         mvi_h_gr        0x0fffffff,r2
  40         mvi_h_dr        0xffffffff,mdh
  41         mvi_h_dr        0x7ffffff0,mdl
  42         set_dbits       0x3             ; Set opposite of expected
  43         set_cc          0x0f            ; Condition codes should not change
  44         div0s           r2
  45         test_cc         1 1 1 1
  46         test_h_gr       0x0fffffff,r2
  47         test_h_dr       0x00000000,mdh
  48         test_h_dr       0x7ffffff0,mdl
  49         test_dbits      0x0
  50
  51         ; Both sign bits 1
  52         mvi_h_gr        0xffffffff,r2
  53         mvi_h_dr        0x00000000,mdh
  54         mvi_h_dr        0xffffffff,mdl
  55         set_dbits       0x2             ; Set opposite of expected
  56         set_cc          0x0f            ; Condition codes should not change
  57         div0s           r2
  58         test_cc         1 1 1 1
  59         test_h_gr       0xffffffff,r2
  60         test_h_dr       0xffffffff,mdh
  61         test_h_dr       0xffffffff,mdl
  62         test_dbits      0x1
  63
  64         pass