1 # frv testcase for caddcc $GRi,$GRj,$GRk,$CCi,$cond
4 .include "testutils.inc"
10 set_spr_immed 0x1b1b,cccr
14 set_icc 0x0f,0 ; Set mask opposite of expected
15 caddcc gr7,gr8,gr8,cc0,1
19 set_gr_limmed 0x7fff,0xffff,gr7
21 set_icc 0x05,0 ; Set mask opposite of expected
22 caddcc gr7,gr8,gr8,cc0,1
24 test_gr_limmed 0x8000,0x0000,gr8
26 set_icc 0x08,0 ; Set mask opposite of expected
27 caddcc gr8,gr8,gr8,cc4,1
31 set_gr_limmed 0x8000,0x0000,gr8
32 set_icc 0x08,0 ; Set mask opposite of expected
33 caddcc gr8,gr8,gr8,cc4,1; test zero, carry and overflow bits
39 set_icc 0x0f,0 ; Set mask opposite of expected
40 caddcc gr7,gr8,gr8,cc0,0
44 set_gr_limmed 0x7fff,0xffff,gr7
46 set_icc 0x05,0 ; Set mask opposite of expected
47 caddcc gr7,gr8,gr8,cc0,0
51 set_icc 0x08,0 ; Set mask opposite of expected
52 caddcc gr8,gr8,gr8,cc4,0
56 set_gr_limmed 0x8000,0x0000,gr8
57 set_icc 0x08,0 ; Set mask opposite of expected
58 caddcc gr8,gr8,gr8,cc4,0; test zero, carry and overflow bits
60 test_gr_limmed 0x8000,0x0000,gr8
64 set_icc 0x0f,1 ; Set mask opposite of expected
65 caddcc gr7,gr8,gr8,cc1,0
69 set_gr_limmed 0x7fff,0xffff,gr7
71 set_icc 0x05,1 ; Set mask opposite of expected
72 caddcc gr7,gr8,gr8,cc1,0
74 test_gr_limmed 0x8000,0x0000,gr8
76 set_icc 0x08,1 ; Set mask opposite of expected
77 caddcc gr8,gr8,gr8,cc5,0
81 set_gr_limmed 0x8000,0x0000,gr8
82 set_icc 0x08,1 ; Set mask opposite of expected
83 caddcc gr8,gr8,gr8,cc5,0; test zero, carry and overflow bits
89 set_icc 0x0f,1 ; Set mask opposite of expected
90 caddcc gr7,gr8,gr8,cc1,1
94 set_gr_limmed 0x7fff,0xffff,gr7
96 set_icc 0x05,1 ; Set mask opposite of expected
97 caddcc gr7,gr8,gr8,cc1,1
101 set_icc 0x08,1 ; Set mask opposite of expected
102 caddcc gr8,gr8,gr8,cc5,1
103 test_icc 1 0 0 0 icc1
106 set_gr_limmed 0x8000,0x0000,gr8
107 set_icc 0x08,1 ; Set mask opposite of expected
108 caddcc gr8,gr8,gr8,cc5,1; test zero, carry and overflow bits
109 test_icc 1 0 0 0 icc1
110 test_gr_limmed 0x8000,0x0000,gr8
114 set_icc 0x0f,2 ; Set mask opposite of expected
115 caddcc gr7,gr8,gr8,cc2,0
116 test_icc 1 1 1 1 icc2
119 set_gr_limmed 0x7fff,0xffff,gr7
121 set_icc 0x05,2 ; Set mask opposite of expected
122 caddcc gr7,gr8,gr8,cc2,0
123 test_icc 0 1 0 1 icc2
126 set_icc 0x08,2 ; Set mask opposite of expected
127 caddcc gr8,gr8,gr8,cc6,1
128 test_icc 1 0 0 0 icc2
131 set_gr_limmed 0x8000,0x0000,gr8
132 set_icc 0x08,2 ; Set mask opposite of expected
133 caddcc gr8,gr8,gr8,cc6,1; test zero, carry and overflow bits
134 test_icc 1 0 0 0 icc2
135 test_gr_limmed 0x8000,0x0000,gr8
139 set_icc 0x0f,3 ; Set mask opposite of expected
140 caddcc gr7,gr8,gr8,cc3,0
141 test_icc 1 1 1 1 icc3
144 set_gr_limmed 0x7fff,0xffff,gr7
146 set_icc 0x05,3 ; Set mask opposite of expected
147 caddcc gr7,gr8,gr8,cc3,0
148 test_icc 0 1 0 1 icc3
151 set_icc 0x08,3 ; Set mask opposite of expected
152 caddcc gr8,gr8,gr8,cc7,1
153 test_icc 1 0 0 0 icc3
156 set_gr_limmed 0x8000,0x0000,gr8
157 set_icc 0x08,3 ; Set mask opposite of expected
158 caddcc gr8,gr8,gr8,cc7,1; test zero, carry and overflow bits
159 test_icc 1 0 0 0 icc3
160 test_gr_limmed 0x8000,0x0000,gr8