New sim testsuite for Fujitsu FRV. Contributed by Red Hat.
[deliverable/binutils-gdb.git] / sim / testsuite / sim / frv / fcblglr.cgs
1 # frv testcase for fcblglr $FCCi,$ccond,$hint
2 # mach: all
3
4 .include "testutils.inc"
5
6 start
7
8 .global fcblglr
9 fcblglr:
10 ; ccond is true
11 set_spr_immed 128,lcr
12 set_spr_addr bad,lr
13 set_fcc 0x0 0
14 fcblglr fcc0,0,0
15
16 set_spr_addr bad,lr
17 set_fcc 0x1 1
18 fcblglr fcc1,0,1
19
20 set_spr_addr ok3,lr
21 set_fcc 0x2 2
22 fcblglr fcc2,0,2
23 fail
24 ok3:
25 set_spr_addr ok4,lr
26 set_fcc 0x3 3
27 fcblglr fcc3,0,3
28 fail
29 ok4:
30 set_spr_addr ok5,lr
31 set_fcc 0x4 0
32 fcblglr fcc0,0,0
33 fail
34 ok5:
35 set_spr_addr ok6,lr
36 set_fcc 0x5 1
37 fcblglr fcc1,0,1
38 fail
39 ok6:
40 set_spr_addr ok7,lr
41 set_fcc 0x6 2
42 fcblglr fcc2,0,2
43 fail
44 ok7:
45 set_spr_addr ok8,lr
46 set_fcc 0x7 3
47 fcblglr fcc3,0,3
48 fail
49 ok8:
50 set_spr_addr bad,lr
51 set_fcc 0x8 0
52 fcblglr fcc0,0,0
53
54 set_spr_addr bad,lr
55 set_fcc 0x9 1
56 fcblglr fcc1,0,1
57
58 set_spr_addr okb,lr
59 set_fcc 0xa 2
60 fcblglr fcc2,0,2
61 fail
62 okb:
63 set_spr_addr okc,lr
64 set_fcc 0xb 3
65 fcblglr fcc3,0,3
66 fail
67 okc:
68 set_spr_addr okd,lr
69 set_fcc 0xc 0
70 fcblglr fcc0,0,0
71 fail
72 okd:
73 set_spr_addr oke,lr
74 set_fcc 0xd 1
75 fcblglr fcc1,0,1
76 fail
77 oke:
78 set_spr_addr okf,lr
79 set_fcc 0xe 2
80 fcblglr fcc2,0,2
81 fail
82 okf:
83 set_spr_addr okg,lr
84 set_fcc 0xf 3
85 fcblglr fcc3,0,3
86 fail
87 okg:
88
89 ; ccond is true
90 set_spr_immed 1,lcr
91 set_spr_addr bad,lr
92 set_fcc 0x0 0
93 fcblglr fcc0,1,0
94
95 set_spr_immed 1,lcr
96 set_spr_addr bad,lr
97 set_fcc 0x1 1
98 fcblglr fcc1,1,1
99
100 set_spr_immed 1,lcr
101 set_spr_addr okj,lr
102 set_fcc 0x2 2
103 fcblglr fcc2,1,2
104 fail
105 okj:
106 set_spr_immed 1,lcr
107 set_spr_addr okk,lr
108 set_fcc 0x3 3
109 fcblglr fcc3,1,3
110 fail
111 okk:
112 set_spr_immed 1,lcr
113 set_spr_addr okl,lr
114 set_fcc 0x4 0
115 fcblglr fcc0,1,0
116 fail
117 okl:
118 set_spr_immed 1,lcr
119 set_spr_addr okm,lr
120 set_fcc 0x5 1
121 fcblglr fcc1,1,1
122 fail
123 okm:
124 set_spr_immed 1,lcr
125 set_spr_addr okn,lr
126 set_fcc 0x6 2
127 fcblglr fcc2,1,2
128 fail
129 okn:
130 set_spr_immed 1,lcr
131 set_spr_addr oko,lr
132 set_fcc 0x7 3
133 fcblglr fcc3,1,3
134 fail
135 oko:
136 set_spr_immed 1,lcr
137 set_spr_addr bad,lr
138 set_fcc 0x8 0
139 fcblglr fcc0,1,0
140
141 set_spr_immed 1,lcr
142 set_spr_addr bad,lr
143 set_fcc 0x9 1
144 fcblglr fcc1,1,1
145
146 set_spr_immed 1,lcr
147 set_spr_addr okr,lr
148 set_fcc 0xa 2
149 fcblglr fcc2,1,2
150 fail
151 okr:
152 set_spr_immed 1,lcr
153 set_spr_addr oks,lr
154 set_fcc 0xb 3
155 fcblglr fcc3,1,3
156 fail
157 oks:
158 set_spr_immed 1,lcr
159 set_spr_addr okt,lr
160 set_fcc 0xc 0
161 fcblglr fcc0,1,0
162 fail
163 okt:
164 set_spr_immed 1,lcr
165 set_spr_addr oku,lr
166 set_fcc 0xd 1
167 fcblglr fcc1,1,1
168 fail
169 oku:
170 set_spr_immed 1,lcr
171 set_spr_addr okv,lr
172 set_fcc 0xe 2
173 fcblglr fcc2,1,2
174 fail
175 okv:
176 set_spr_immed 1,lcr
177 set_spr_addr okw,lr
178 set_fcc 0xf 3
179 fcblglr fcc3,1,3
180 fail
181 okw:
182 ; ccond is false
183 set_spr_immed 128,lcr
184
185 set_fcc 0x0 0
186 fcblglr fcc0,1,0
187 set_fcc 0x1 1
188 fcblglr fcc1,1,1
189 set_fcc 0x2 2
190 fcblglr fcc2,1,2
191 set_fcc 0x3 3
192 fcblglr fcc3,1,3
193 set_fcc 0x4 0
194 fcblglr fcc0,1,0
195 set_fcc 0x5 1
196 fcblglr fcc1,1,1
197 set_fcc 0x6 2
198 fcblglr fcc2,1,2
199 set_fcc 0x7 3
200 fcblglr fcc3,1,3
201 set_fcc 0x8 0
202 fcblglr fcc0,1,0
203 set_fcc 0x9 1
204 fcblglr fcc1,1,1
205 set_fcc 0xa 2
206 fcblglr fcc2,1,2
207 set_fcc 0xb 3
208 fcblglr fcc3,1,3
209 set_fcc 0xc 0
210 fcblglr fcc0,1,0
211 set_fcc 0xd 1
212 fcblglr fcc1,1,1
213 set_fcc 0xe 2
214 fcblglr fcc2,1,2
215 set_fcc 0xf 3
216 fcblglr fcc3,1,3
217
218 ; ccond is false
219 set_spr_immed 1,lcr
220 set_fcc 0x0 0
221 fcblglr fcc0,0,0
222 set_spr_immed 1,lcr
223 set_fcc 0x1 1
224 fcblglr fcc1,0,1
225 set_spr_immed 1,lcr
226 set_fcc 0x2 2
227 fcblglr fcc2,0,2
228 set_spr_immed 1,lcr
229 set_fcc 0x3 3
230 fcblglr fcc3,0,3
231 set_spr_immed 1,lcr
232 set_fcc 0x4 0
233 fcblglr fcc0,0,0
234 set_spr_immed 1,lcr
235 set_fcc 0x5 1
236 fcblglr fcc1,0,1
237 set_spr_immed 1,lcr
238 set_fcc 0x6 2
239 fcblglr fcc2,0,2
240 set_spr_immed 1,lcr
241 set_fcc 0x7 3
242 fcblglr fcc3,0,3
243 set_spr_immed 1,lcr
244 set_fcc 0x8 0
245 fcblglr fcc0,0,0
246 set_spr_immed 1,lcr
247 set_fcc 0x9 1
248 fcblglr fcc1,0,1
249 set_spr_immed 1,lcr
250 set_fcc 0xa 2
251 fcblglr fcc2,0,2
252 set_spr_immed 1,lcr
253 set_fcc 0xb 3
254 fcblglr fcc3,0,3
255 set_spr_immed 1,lcr
256 set_fcc 0xc 0
257 fcblglr fcc0,0,0
258 set_spr_immed 1,lcr
259 set_fcc 0xd 1
260 fcblglr fcc1,0,1
261 set_spr_immed 1,lcr
262 set_fcc 0xe 2
263 fcblglr fcc2,0,2
264 set_spr_immed 1,lcr
265 set_fcc 0xf 3
266 fcblglr fcc3,0,3
267
268 pass
269 bad:
270 fail
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