sim/testsuite/sim/frv/fr500/cmqsubhss.cgs

   1 # frv testcase for cmqsubhss $FRi,$FRj,$FRj,$CCi,$cond
   2 # mach: all
   3
   4         .include "../testutils.inc"
   5
   6         start
   7
   8         .global msubhss
   9 msubhss:
  10         set_spr_immed   0x1b1b,cccr
  11
  12         set_fr_iimmed   0x0000,0x0000,fr10
  13         set_fr_iimmed   0xdead,0x0000,fr11
  14         set_fr_iimmed   0x0000,0x0000,fr12
  15         set_fr_iimmed   0x0000,0xbeef,fr13
  16         cmqsubhss       fr10,fr12,fr14,cc0,1
  17         test_fr_limmed  0x0000,0x0000,fr14
  18         test_fr_limmed  0xdead,0x4111,fr15
  19         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  20         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  21         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  22         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
  23
  24         set_fr_iimmed   0x0000,0xdead,fr10
  25         set_fr_iimmed   0x1234,0x5678,fr11
  26         set_fr_iimmed   0xbeef,0x0000,fr12
  27         set_fr_iimmed   0x1111,0x1111,fr13
  28         cmqsubhss       fr10,fr12,fr14,cc0,1
  29         test_fr_limmed  0x4111,0xdead,fr14
  30         test_fr_limmed  0x0123,0x4567,fr15
  31         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  32         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  33         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  34         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
  35
  36         set_spr_immed   0,msr0
  37         set_fr_iimmed   0x1234,0x5678,fr10
  38         set_fr_iimmed   0x7ffe,0x7ffe,fr11
  39         set_fr_iimmed   0xffff,0xffff,fr12
  40         set_fr_iimmed   0xfffe,0xffff,fr13
  41         cmqsubhss       fr10,fr12,fr14,cc0,1
  42         test_fr_limmed  0x1235,0x5679,fr14
  43         test_fr_limmed  0x7fff,0x7fff,fr15
  44         test_spr_bits   0x3c,2,0x2,msr0         ; msr0.sie is set
  45         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
  46         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
  47         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
  48
  49         set_spr_immed   0,msr0
  50         set_fr_iimmed   0x8001,0x8001,fr10
  51         set_fr_iimmed   0x8001,0x8001,fr11
  52         set_fr_iimmed   0x0001,0x0002,fr12
  53         set_fr_iimmed   0x0002,0x0001,fr13
  54         cmqsubhss       fr10,fr12,fr14,cc4,1
  55         test_fr_limmed  0x8000,0x8000,fr14
  56         test_fr_limmed  0x8000,0x8000,fr15
  57         test_spr_bits   0x3c,2,0x6,msr0         ; msr0.sie is set
  58         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
  59         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
  60         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
  61
  62         set_spr_immed   0,msr0
  63         set_spr_immed   0,msr1
  64         set_fr_iimmed   0x0001,0x0001,fr10
  65         set_fr_iimmed   0xffff,0xffff,fr11
  66         set_fr_iimmed   0x8000,0x8000,fr12
  67         set_fr_iimmed   0x8000,0x8000,fr13
  68         cmqsubhss.p     fr10,fr10,fr14,cc4,1
  69         cmqsubhss       fr12,fr10,fr16,cc4,1
  70         test_fr_limmed  0x0000,0x0000,fr14
  71         test_fr_limmed  0x0000,0x0000,fr15
  72         test_fr_limmed  0x8000,0x8000,fr16
  73         test_fr_limmed  0x8001,0x8001,fr17
  74         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  75         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  76         test_spr_bits   0x3c,2,0xc,msr1         ; msr0.sie is set
  77         test_spr_bits   2,1,1,msr1              ; msr1.ovf set
  78         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
  79         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
  80
  81         set_spr_immed   0,msr0
  82         set_spr_immed   0,msr1
  83         set_fr_iimmed   0x0000,0x0000,fr10
  84         set_fr_iimmed   0xdead,0x0000,fr11
  85         set_fr_iimmed   0x0000,0x0000,fr12
  86         set_fr_iimmed   0x0000,0xbeef,fr13
  87         cmqsubhss       fr10,fr12,fr14,cc1,0
  88         test_fr_limmed  0x0000,0x0000,fr14
  89         test_fr_limmed  0xdead,0x4111,fr15
  90         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  91         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  92         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  93         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
  94
  95         set_fr_iimmed   0x0000,0xdead,fr10
  96         set_fr_iimmed   0x1234,0x5678,fr11
  97         set_fr_iimmed   0xbeef,0x0000,fr12
  98         set_fr_iimmed   0x1111,0x1111,fr13
  99         cmqsubhss       fr10,fr12,fr14,cc1,0
 100         test_fr_limmed  0x4111,0xdead,fr14
 101         test_fr_limmed  0x0123,0x4567,fr15
 102         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 103         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 104         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 105         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 106
 107         set_spr_immed   0,msr0
 108         set_fr_iimmed   0x1234,0x5678,fr10
 109         set_fr_iimmed   0x7ffe,0x7ffe,fr11
 110         set_fr_iimmed   0xffff,0xffff,fr12
 111         set_fr_iimmed   0xfffe,0xffff,fr13
 112         cmqsubhss       fr10,fr12,fr14,cc1,0
 113         test_fr_limmed  0x1235,0x5679,fr14
 114         test_fr_limmed  0x7fff,0x7fff,fr15
 115         test_spr_bits   0x3c,2,0x2,msr0         ; msr0.sie is set
 116         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
 117         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
 118         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
 119
 120         set_spr_immed   0,msr0
 121         set_fr_iimmed   0x8001,0x8001,fr10
 122         set_fr_iimmed   0x8001,0x8001,fr11
 123         set_fr_iimmed   0x0001,0x0002,fr12
 124         set_fr_iimmed   0x0002,0x0001,fr13
 125         cmqsubhss       fr10,fr12,fr14,cc5,0
 126         test_fr_limmed  0x8000,0x8000,fr14
 127         test_fr_limmed  0x8000,0x8000,fr15
 128         test_spr_bits   0x3c,2,0x6,msr0         ; msr0.sie is set
 129         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
 130         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
 131         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
 132
 133         set_spr_immed   0,msr0
 134         set_spr_immed   0,msr1
 135         set_fr_iimmed   0x0001,0x0001,fr10
 136         set_fr_iimmed   0xffff,0xffff,fr11
 137         set_fr_iimmed   0x8000,0x8000,fr12
 138         set_fr_iimmed   0x8000,0x8000,fr13
 139         cmqsubhss.p     fr10,fr10,fr14,cc5,0
 140         cmqsubhss       fr12,fr10,fr16,cc5,0
 141         test_fr_limmed  0x0000,0x0000,fr14
 142         test_fr_limmed  0x0000,0x0000,fr15
 143         test_fr_limmed  0x8000,0x8000,fr16
 144         test_fr_limmed  0x8001,0x8001,fr17
 145         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 146         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 147         test_spr_bits   0x3c,2,0xc,msr1         ; msr0.sie is set
 148         test_spr_bits   2,1,1,msr1              ; msr1.ovf set
 149         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
 150         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
 151
 152         set_fr_iimmed   0x1111,0x1111,fr14
 153         set_fr_iimmed   0x2222,0x2222,fr15
 154         set_spr_immed   0,msr0
 155         set_spr_immed   0,msr1
 156         set_fr_iimmed   0x0000,0x0000,fr10
 157         set_fr_iimmed   0xdead,0x0000,fr11
 158         set_fr_iimmed   0x0000,0x0000,fr12
 159         set_fr_iimmed   0x0000,0xbeef,fr13
 160         cmqsubhss       fr10,fr12,fr14,cc0,0
 161         test_fr_limmed  0x1111,0x1111,fr14
 162         test_fr_limmed  0x2222,0x2222,fr15
 163         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 164         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 165         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 166         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 167
 168         set_fr_iimmed   0x0000,0xdead,fr10
 169         set_fr_iimmed   0x1234,0x5678,fr11
 170         set_fr_iimmed   0xbeef,0x0000,fr12
 171         set_fr_iimmed   0x1111,0x1111,fr13
 172         cmqsubhss       fr10,fr12,fr14,cc0,0
 173         test_fr_limmed  0x1111,0x1111,fr14
 174         test_fr_limmed  0x2222,0x2222,fr15
 175         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 176         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 177         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 178         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 179
 180         set_spr_immed   0,msr0
 181         set_fr_iimmed   0x1234,0x5678,fr10
 182         set_fr_iimmed   0x7ffe,0x7ffe,fr11
 183         set_fr_iimmed   0xffff,0xffff,fr12
 184         set_fr_iimmed   0xfffe,0xffff,fr13
 185         cmqsubhss       fr10,fr12,fr14,cc0,0
 186         test_fr_limmed  0x1111,0x1111,fr14
 187         test_fr_limmed  0x2222,0x2222,fr15
 188         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 189         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 190         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 191         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 192
 193         set_spr_immed   0,msr0
 194         set_fr_iimmed   0x8001,0x8001,fr10
 195         set_fr_iimmed   0x8001,0x8001,fr11
 196         set_fr_iimmed   0x0001,0x0002,fr12
 197         set_fr_iimmed   0x0002,0x0001,fr13
 198         cmqsubhss       fr10,fr12,fr14,cc4,0
 199         test_fr_limmed  0x1111,0x1111,fr14
 200         test_fr_limmed  0x2222,0x2222,fr15
 201         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 202         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 203         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 204         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 205
 206         set_fr_iimmed   0x3333,0x3333,fr16
 207         set_fr_iimmed   0x4444,0x4444,fr17
 208         set_spr_immed   0,msr0
 209         set_spr_immed   0,msr1
 210         set_fr_iimmed   0x0001,0x0001,fr10
 211         set_fr_iimmed   0xffff,0xffff,fr11
 212         set_fr_iimmed   0x8000,0x8000,fr12
 213         set_fr_iimmed   0x8000,0x8000,fr13
 214         cmqsubhss.p     fr10,fr10,fr14,cc4,0
 215         cmqsubhss       fr12,fr10,fr16,cc4,0
 216         test_fr_limmed  0x1111,0x1111,fr14
 217         test_fr_limmed  0x2222,0x2222,fr15
 218         test_fr_limmed  0x3333,0x3333,fr16
 219         test_fr_limmed  0x4444,0x4444,fr17
 220         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 221         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 222         test_spr_bits   2,1,0,msr1              ; msr1.ovf not set
 223         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 224         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 225
 226         set_fr_iimmed   0x1111,0x1111,fr14
 227         set_fr_iimmed   0x2222,0x2222,fr15
 228         set_spr_immed   0,msr0
 229         set_spr_immed   0,msr1
 230         set_fr_iimmed   0x0000,0x0000,fr10
 231         set_fr_iimmed   0xdead,0x0000,fr11
 232         set_fr_iimmed   0x0000,0x0000,fr12
 233         set_fr_iimmed   0x0000,0xbeef,fr13
 234         cmqsubhss       fr10,fr12,fr14,cc1,1
 235         test_fr_limmed  0x1111,0x1111,fr14
 236         test_fr_limmed  0x2222,0x2222,fr15
 237         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 238         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 239         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 240         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 241
 242         set_fr_iimmed   0x0000,0xdead,fr10
 243         set_fr_iimmed   0x1234,0x5678,fr11
 244         set_fr_iimmed   0xbeef,0x0000,fr12
 245         set_fr_iimmed   0x1111,0x1111,fr13
 246         cmqsubhss       fr10,fr12,fr14,cc1,1
 247         test_fr_limmed  0x1111,0x1111,fr14
 248         test_fr_limmed  0x2222,0x2222,fr15
 249         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 250         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 251         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 252         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 253
 254         set_spr_immed   0,msr0
 255         set_fr_iimmed   0x1234,0x5678,fr10
 256         set_fr_iimmed   0x7ffe,0x7ffe,fr11
 257         set_fr_iimmed   0xffff,0xffff,fr12
 258         set_fr_iimmed   0xfffe,0xffff,fr13
 259         cmqsubhss       fr10,fr12,fr14,cc1,1
 260         test_fr_limmed  0x1111,0x1111,fr14
 261         test_fr_limmed  0x2222,0x2222,fr15
 262         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 263         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 264         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 265         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 266
 267         set_spr_immed   0,msr0
 268         set_fr_iimmed   0x8001,0x8001,fr10
 269         set_fr_iimmed   0x8001,0x8001,fr11
 270         set_fr_iimmed   0x0001,0x0002,fr12
 271         set_fr_iimmed   0x0002,0x0001,fr13
 272         cmqsubhss       fr10,fr12,fr14,cc5,1
 273         test_fr_limmed  0x1111,0x1111,fr14
 274         test_fr_limmed  0x2222,0x2222,fr15
 275         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 276         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 277         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 278         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 279
 280         set_fr_iimmed   0x3333,0x3333,fr16
 281         set_fr_iimmed   0x4444,0x4444,fr17
 282         set_spr_immed   0,msr0
 283         set_spr_immed   0,msr1
 284         set_fr_iimmed   0x0001,0x0001,fr10
 285         set_fr_iimmed   0xffff,0xffff,fr11
 286         set_fr_iimmed   0x8000,0x8000,fr12
 287         set_fr_iimmed   0x8000,0x8000,fr13
 288         cmqsubhss.p     fr10,fr10,fr14,cc5,1
 289         cmqsubhss       fr12,fr10,fr16,cc5,1
 290         test_fr_limmed  0x1111,0x1111,fr14
 291         test_fr_limmed  0x2222,0x2222,fr15
 292         test_fr_limmed  0x3333,0x3333,fr16
 293         test_fr_limmed  0x4444,0x4444,fr17
 294         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 295         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 296         test_spr_bits   2,1,0,msr1              ; msr1.ovf not set
 297         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 298         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 299
 300         set_fr_iimmed   0x1111,0x1111,fr14
 301         set_fr_iimmed   0x2222,0x2222,fr15
 302         set_spr_immed   0,msr0
 303         set_spr_immed   0,msr1
 304         set_fr_iimmed   0x0000,0x0000,fr10
 305         set_fr_iimmed   0xdead,0x0000,fr11
 306         set_fr_iimmed   0x0000,0x0000,fr12
 307         set_fr_iimmed   0x0000,0xbeef,fr13
 308         cmqsubhss       fr10,fr12,fr14,cc2,1
 309         test_fr_limmed  0x1111,0x1111,fr14
 310         test_fr_limmed  0x2222,0x2222,fr15
 311         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 312         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 313         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 314         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 315
 316         set_fr_iimmed   0x0000,0xdead,fr10
 317         set_fr_iimmed   0x1234,0x5678,fr11
 318         set_fr_iimmed   0xbeef,0x0000,fr12
 319         set_fr_iimmed   0x1111,0x1111,fr13
 320         cmqsubhss       fr10,fr12,fr14,cc2,0
 321         test_fr_limmed  0x1111,0x1111,fr14
 322         test_fr_limmed  0x2222,0x2222,fr15
 323         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 324         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 325         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 326         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 327
 328         set_spr_immed   0,msr0
 329         set_fr_iimmed   0x1234,0x5678,fr10
 330         set_fr_iimmed   0x7ffe,0x7ffe,fr11
 331         set_fr_iimmed   0xffff,0xffff,fr12
 332         set_fr_iimmed   0xfffe,0xffff,fr13
 333         cmqsubhss       fr10,fr12,fr14,cc2,1
 334         test_fr_limmed  0x1111,0x1111,fr14
 335         test_fr_limmed  0x2222,0x2222,fr15
 336         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 337         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 338         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 339         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 340
 341         set_spr_immed   0,msr0
 342         set_fr_iimmed   0x8001,0x8001,fr10
 343         set_fr_iimmed   0x8001,0x8001,fr11
 344         set_fr_iimmed   0x0001,0x0002,fr12
 345         set_fr_iimmed   0x0002,0x0001,fr13
 346         cmqsubhss       fr10,fr12,fr14,cc6,0
 347         test_fr_limmed  0x1111,0x1111,fr14
 348         test_fr_limmed  0x2222,0x2222,fr15
 349         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 350         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 351         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 352         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 353
 354         set_fr_iimmed   0x3333,0x3333,fr16
 355         set_fr_iimmed   0x4444,0x4444,fr17
 356         set_spr_immed   0,msr0
 357         set_spr_immed   0,msr1
 358         set_fr_iimmed   0x0001,0x0001,fr10
 359         set_fr_iimmed   0xffff,0xffff,fr11
 360         set_fr_iimmed   0x8000,0x8000,fr12
 361         set_fr_iimmed   0x8000,0x8000,fr13
 362         cmqsubhss.p     fr10,fr10,fr14,cc6,1
 363         cmqsubhss       fr12,fr10,fr16,cc6,0
 364         test_fr_limmed  0x1111,0x1111,fr14
 365         test_fr_limmed  0x2222,0x2222,fr15
 366         test_fr_limmed  0x3333,0x3333,fr16
 367         test_fr_limmed  0x4444,0x4444,fr17
 368         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 369         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 370         test_spr_bits   2,1,0,msr1              ; msr1.ovf not set
 371         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 372         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 373
 374         set_fr_iimmed   0x1111,0x1111,fr14
 375         set_fr_iimmed   0x2222,0x2222,fr15
 376         set_spr_immed   0,msr0
 377         set_spr_immed   0,msr1
 378         set_fr_iimmed   0x0000,0x0000,fr10
 379         set_fr_iimmed   0xdead,0x0000,fr11
 380         set_fr_iimmed   0x0000,0x0000,fr12
 381         set_fr_iimmed   0x0000,0xbeef,fr13
 382         cmqsubhss       fr10,fr12,fr14,cc3,1
 383         test_fr_limmed  0x1111,0x1111,fr14
 384         test_fr_limmed  0x2222,0x2222,fr15
 385         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 386         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 387         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 388         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 389
 390         set_fr_iimmed   0x0000,0xdead,fr10
 391         set_fr_iimmed   0x1234,0x5678,fr11
 392         set_fr_iimmed   0xbeef,0x0000,fr12
 393         set_fr_iimmed   0x1111,0x1111,fr13
 394         cmqsubhss       fr10,fr12,fr14,cc3,0
 395         test_fr_limmed  0x1111,0x1111,fr14
 396         test_fr_limmed  0x2222,0x2222,fr15
 397         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 398         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 399         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 400         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 401
 402         set_spr_immed   0,msr0
 403         set_fr_iimmed   0x1234,0x5678,fr10
 404         set_fr_iimmed   0x7ffe,0x7ffe,fr11
 405         set_fr_iimmed   0xffff,0xffff,fr12
 406         set_fr_iimmed   0xfffe,0xffff,fr13
 407         cmqsubhss       fr10,fr12,fr14,cc3,1
 408         test_fr_limmed  0x1111,0x1111,fr14
 409         test_fr_limmed  0x2222,0x2222,fr15
 410         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 411         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 412         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 413         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 414
 415         set_spr_immed   0,msr0
 416         set_fr_iimmed   0x8001,0x8001,fr10
 417         set_fr_iimmed   0x8001,0x8001,fr11
 418         set_fr_iimmed   0x0001,0x0002,fr12
 419         set_fr_iimmed   0x0002,0x0001,fr13
 420         cmqsubhss       fr10,fr12,fr14,cc7,0
 421         test_fr_limmed  0x1111,0x1111,fr14
 422         test_fr_limmed  0x2222,0x2222,fr15
 423         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 424         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 425         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 426         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 427
 428         set_fr_iimmed   0x3333,0x3333,fr16
 429         set_fr_iimmed   0x4444,0x4444,fr17
 430         set_spr_immed   0,msr0
 431         set_spr_immed   0,msr1
 432         set_fr_iimmed   0x0001,0x0001,fr10
 433         set_fr_iimmed   0xffff,0xffff,fr11
 434         set_fr_iimmed   0x8000,0x8000,fr12
 435         set_fr_iimmed   0x8000,0x8000,fr13
 436         cmqsubhss.p     fr10,fr10,fr14,cc7,1
 437         cmqsubhss       fr12,fr10,fr16,cc7,0
 438         test_fr_limmed  0x1111,0x1111,fr14
 439         test_fr_limmed  0x2222,0x2222,fr15
 440         test_fr_limmed  0x3333,0x3333,fr16
 441         test_fr_limmed  0x4444,0x4444,fr17
 442         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 443         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 444         test_spr_bits   2,1,0,msr1              ; msr1.ovf not set
 445         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 446         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 447
 448         pass