sim/testsuite/sim/frv/fr500/cmqsubhus.cgs

   1 # frv testcase for cmqsubhus $FRi,$FRj,$FRj,$CCi,$cond
   2 # mach: all
   3
   4         .include "../testutils.inc"
   5
   6         start
   7
   8         .global cmqsubhus
   9 cmqsubhus:
  10         set_spr_immed   0x1b1b,cccr
  11
  12         set_fr_iimmed   0x0000,0x0000,fr10
  13         set_fr_iimmed   0xdead,0xbeef,fr11
  14         set_fr_iimmed   0x0000,0x0000,fr12
  15         set_fr_iimmed   0x0000,0x0000,fr13
  16         cmqsubhus       fr10,fr12,fr14,cc0,1
  17         test_fr_limmed  0x0000,0x0000,fr14
  18         test_fr_limmed  0xdead,0xbeef,fr15
  19         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  20         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  21         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  22         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
  23
  24         set_fr_iimmed   0x1234,0x5678,fr10
  25         set_fr_iimmed   0x7ffe,0x7ffe,fr11
  26         set_fr_iimmed   0x1111,0x1111,fr12
  27         set_fr_iimmed   0x0002,0x0001,fr13
  28         cmqsubhus       fr10,fr12,fr14,cc0,1
  29         test_fr_limmed  0x0123,0x4567,fr14
  30         test_fr_limmed  0x7ffc,0x7ffd,fr15
  31         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  32         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  33         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  34         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
  35
  36         set_spr_immed   0,msr0
  37         set_fr_iimmed   0x0001,0x0001,fr10
  38         set_fr_iimmed   0x0001,0x0001,fr11
  39         set_fr_iimmed   0x0001,0x0002,fr12
  40         set_fr_iimmed   0x0002,0x0001,fr13
  41         cmqsubhus       fr10,fr12,fr14,cc4,1
  42         test_fr_limmed  0x0000,0x0000,fr14
  43         test_fr_limmed  0x0000,0x0000,fr15
  44         test_spr_bits   0x3c,2,0x6,msr0         ; msr0.sie is set
  45         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
  46         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
  47         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
  48
  49         set_spr_immed   0,msr0
  50         set_spr_immed   0,msr1
  51         set_fr_iimmed   0x0001,0x0001,fr10
  52         set_fr_iimmed   0x0002,0x0002,fr11
  53         set_fr_iimmed   0x0000,0x0001,fr12
  54         set_fr_iimmed   0x0002,0x0003,fr13
  55         cmqsubhus.p     fr10,fr10,fr14,cc4,1
  56         cmqsubhus       fr10,fr12,fr16,cc4,1
  57         test_fr_limmed  0x0000,0x0000,fr14
  58         test_fr_limmed  0x0000,0x0000,fr15
  59         test_fr_limmed  0x0001,0x0000,fr16
  60         test_fr_limmed  0x0000,0x0000,fr17
  61         test_spr_bits   0x3c,2,0x0,msr0         ; msr0.sie is clear
  62         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  63         test_spr_bits   0x3c,2,0x1,msr1         ; msr1.sie is set
  64         test_spr_bits   2,1,1,msr1              ; msr1.ovf set
  65         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
  66         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
  67
  68         set_spr_immed   0,msr0
  69         set_spr_immed   0,msr1
  70         set_fr_iimmed   0x0000,0x0000,fr10
  71         set_fr_iimmed   0xdead,0xbeef,fr11
  72         set_fr_iimmed   0x0000,0x0000,fr12
  73         set_fr_iimmed   0x0000,0x0000,fr13
  74         cmqsubhus       fr10,fr12,fr14,cc1,0
  75         test_fr_limmed  0x0000,0x0000,fr14
  76         test_fr_limmed  0xdead,0xbeef,fr15
  77         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  78         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  79         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  80         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
  81
  82         set_fr_iimmed   0x1234,0x5678,fr10
  83         set_fr_iimmed   0x7ffe,0x7ffe,fr11
  84         set_fr_iimmed   0x1111,0x1111,fr12
  85         set_fr_iimmed   0x0002,0x0001,fr13
  86         cmqsubhus       fr10,fr12,fr14,cc1,0
  87         test_fr_limmed  0x0123,0x4567,fr14
  88         test_fr_limmed  0x7ffc,0x7ffd,fr15
  89         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  90         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  91         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  92         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
  93
  94         set_spr_immed   0,msr0
  95         set_fr_iimmed   0x0001,0x0001,fr10
  96         set_fr_iimmed   0x0001,0x0001,fr11
  97         set_fr_iimmed   0x0001,0x0002,fr12
  98         set_fr_iimmed   0x0002,0x0001,fr13
  99         cmqsubhus       fr10,fr12,fr14,cc5,0
 100         test_fr_limmed  0x0000,0x0000,fr14
 101         test_fr_limmed  0x0000,0x0000,fr15
 102         test_spr_bits   0x3c,2,0x6,msr0         ; msr0.sie is set
 103         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
 104         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
 105         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
 106
 107         set_spr_immed   0,msr0
 108         set_spr_immed   0,msr1
 109         set_fr_iimmed   0x0001,0x0001,fr10
 110         set_fr_iimmed   0x0002,0x0002,fr11
 111         set_fr_iimmed   0x0000,0x0001,fr12
 112         set_fr_iimmed   0x0002,0x0003,fr13
 113         cmqsubhus.p     fr10,fr10,fr14,cc5,0
 114         cmqsubhus       fr10,fr12,fr16,cc5,0
 115         test_fr_limmed  0x0000,0x0000,fr14
 116         test_fr_limmed  0x0000,0x0000,fr15
 117         test_fr_limmed  0x0001,0x0000,fr16
 118         test_fr_limmed  0x0000,0x0000,fr17
 119         test_spr_bits   0x3c,2,0x0,msr0         ; msr0.sie is clear
 120         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 121         test_spr_bits   0x3c,2,0x1,msr1         ; msr1.sie is set
 122         test_spr_bits   2,1,1,msr1              ; msr1.ovf set
 123         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
 124         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
 125
 126         set_fr_iimmed   0x1111,0x1111,fr14
 127         set_fr_iimmed   0x2222,0x2222,fr15
 128         set_spr_immed   0,msr0
 129         set_spr_immed   0,msr1
 130         set_fr_iimmed   0x0000,0x0000,fr10
 131         set_fr_iimmed   0xdead,0xbeef,fr11
 132         set_fr_iimmed   0x0000,0x0000,fr12
 133         set_fr_iimmed   0x0000,0x0000,fr13
 134         cmqsubhus       fr10,fr12,fr14,cc0,0
 135         test_fr_limmed  0x1111,0x1111,fr14
 136         test_fr_limmed  0x2222,0x2222,fr15
 137         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 138         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 139         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 140         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 141
 142         set_fr_iimmed   0x1234,0x5678,fr10
 143         set_fr_iimmed   0x7ffe,0x7ffe,fr11
 144         set_fr_iimmed   0x1111,0x1111,fr12
 145         set_fr_iimmed   0x0002,0x0001,fr13
 146         cmqsubhus       fr10,fr12,fr14,cc0,0
 147         test_fr_limmed  0x1111,0x1111,fr14
 148         test_fr_limmed  0x2222,0x2222,fr15
 149         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 150         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 151         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 152         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 153
 154         set_spr_immed   0,msr0
 155         set_fr_iimmed   0x0001,0x0001,fr10
 156         set_fr_iimmed   0x0001,0x0001,fr11
 157         set_fr_iimmed   0x0001,0x0002,fr12
 158         set_fr_iimmed   0x0002,0x0001,fr13
 159         cmqsubhus       fr10,fr12,fr14,cc4,0
 160         test_fr_limmed  0x1111,0x1111,fr14
 161         test_fr_limmed  0x2222,0x2222,fr15
 162         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 163         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 164         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 165         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 166
 167         set_fr_iimmed   0x3333,0x3333,fr16
 168         set_fr_iimmed   0x4444,0x4444,fr17
 169         set_spr_immed   0,msr0
 170         set_spr_immed   0,msr1
 171         set_fr_iimmed   0x0001,0x0001,fr10
 172         set_fr_iimmed   0x0002,0x0002,fr11
 173         set_fr_iimmed   0x0000,0x0001,fr12
 174         set_fr_iimmed   0x0002,0x0003,fr13
 175         cmqsubhus.p     fr10,fr10,fr14,cc4,0
 176         cmqsubhus       fr10,fr12,fr16,cc4,0
 177         test_fr_limmed  0x1111,0x1111,fr14
 178         test_fr_limmed  0x2222,0x2222,fr15
 179         test_fr_limmed  0x3333,0x3333,fr16
 180         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 181         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 182         test_spr_bits   2,1,0,msr1              ; msr1.ovf not set
 183         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 184         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 185         test_fr_limmed  0x4444,0x4444,fr17
 186
 187         set_fr_iimmed   0x1111,0x1111,fr14
 188         set_fr_iimmed   0x2222,0x2222,fr15
 189         set_spr_immed   0,msr0
 190         set_spr_immed   0,msr1
 191         set_fr_iimmed   0x0000,0x0000,fr10
 192         set_fr_iimmed   0xdead,0xbeef,fr11
 193         set_fr_iimmed   0x0000,0x0000,fr12
 194         set_fr_iimmed   0x0000,0x0000,fr13
 195         cmqsubhus       fr10,fr12,fr14,cc1,1
 196         test_fr_limmed  0x1111,0x1111,fr14
 197         test_fr_limmed  0x2222,0x2222,fr15
 198         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 199         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 200         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 201         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 202
 203         set_fr_iimmed   0x1234,0x5678,fr10
 204         set_fr_iimmed   0x7ffe,0x7ffe,fr11
 205         set_fr_iimmed   0x1111,0x1111,fr12
 206         set_fr_iimmed   0x0002,0x0001,fr13
 207         cmqsubhus       fr10,fr12,fr14,cc1,1
 208         test_fr_limmed  0x1111,0x1111,fr14
 209         test_fr_limmed  0x2222,0x2222,fr15
 210         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 211         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 212         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 213         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 214
 215         set_spr_immed   0,msr0
 216         set_fr_iimmed   0x0001,0x0001,fr10
 217         set_fr_iimmed   0x0001,0x0001,fr11
 218         set_fr_iimmed   0x0001,0x0002,fr12
 219         set_fr_iimmed   0x0002,0x0001,fr13
 220         cmqsubhus       fr10,fr12,fr14,cc5,1
 221         test_fr_limmed  0x1111,0x1111,fr14
 222         test_fr_limmed  0x2222,0x2222,fr15
 223         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 224         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 225         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 226         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 227
 228         set_fr_iimmed   0x3333,0x3333,fr16
 229         set_fr_iimmed   0x4444,0x4444,fr17
 230         set_spr_immed   0,msr0
 231         set_spr_immed   0,msr1
 232         set_fr_iimmed   0x0001,0x0001,fr10
 233         set_fr_iimmed   0x0002,0x0002,fr11
 234         set_fr_iimmed   0x0000,0x0001,fr12
 235         set_fr_iimmed   0x0002,0x0003,fr13
 236         cmqsubhus.p     fr10,fr10,fr14,cc5,1
 237         cmqsubhus       fr10,fr12,fr16,cc5,1
 238         test_fr_limmed  0x1111,0x1111,fr14
 239         test_fr_limmed  0x2222,0x2222,fr15
 240         test_fr_limmed  0x3333,0x3333,fr16
 241         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 242         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 243         test_spr_bits   2,1,0,msr1              ; msr1.ovf not set
 244         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 245         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 246         test_fr_limmed  0x4444,0x4444,fr17
 247
 248         set_fr_iimmed   0x1111,0x1111,fr14
 249         set_fr_iimmed   0x2222,0x2222,fr15
 250         set_spr_immed   0,msr0
 251         set_spr_immed   0,msr1
 252         set_fr_iimmed   0x0000,0x0000,fr10
 253         set_fr_iimmed   0xdead,0xbeef,fr11
 254         set_fr_iimmed   0x0000,0x0000,fr12
 255         set_fr_iimmed   0x0000,0x0000,fr13
 256         cmqsubhus       fr10,fr12,fr14,cc2,1
 257         test_fr_limmed  0x1111,0x1111,fr14
 258         test_fr_limmed  0x2222,0x2222,fr15
 259         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 260         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 261         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 262         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 263
 264         set_fr_iimmed   0x1234,0x5678,fr10
 265         set_fr_iimmed   0x7ffe,0x7ffe,fr11
 266         set_fr_iimmed   0x1111,0x1111,fr12
 267         set_fr_iimmed   0x0002,0x0001,fr13
 268         cmqsubhus       fr10,fr12,fr14,cc2,0
 269         test_fr_limmed  0x1111,0x1111,fr14
 270         test_fr_limmed  0x2222,0x2222,fr15
 271         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 272         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 273         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 274         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 275
 276         set_spr_immed   0,msr0
 277         set_fr_iimmed   0x0001,0x0001,fr10
 278         set_fr_iimmed   0x0001,0x0001,fr11
 279         set_fr_iimmed   0x0001,0x0002,fr12
 280         set_fr_iimmed   0x0002,0x0001,fr13
 281         cmqsubhus       fr10,fr12,fr14,cc6,1
 282         test_fr_limmed  0x1111,0x1111,fr14
 283         test_fr_limmed  0x2222,0x2222,fr15
 284         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 285         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 286         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 287         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 288
 289         set_fr_iimmed   0x3333,0x3333,fr16
 290         set_fr_iimmed   0x4444,0x4444,fr17
 291         set_spr_immed   0,msr0
 292         set_spr_immed   0,msr1
 293         set_fr_iimmed   0x0001,0x0001,fr10
 294         set_fr_iimmed   0x0002,0x0002,fr11
 295         set_fr_iimmed   0x0000,0x0001,fr12
 296         set_fr_iimmed   0x0002,0x0003,fr13
 297         cmqsubhus.p     fr10,fr10,fr14,cc6,0
 298         cmqsubhus       fr10,fr12,fr16,cc6,1
 299         test_fr_limmed  0x1111,0x1111,fr14
 300         test_fr_limmed  0x2222,0x2222,fr15
 301         test_fr_limmed  0x3333,0x3333,fr16
 302         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 303         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 304         test_spr_bits   2,1,0,msr1              ; msr1.ovf not set
 305         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 306         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 307         test_fr_limmed  0x4444,0x4444,fr17
 308 ;
 309         set_fr_iimmed   0x1111,0x1111,fr14
 310         set_fr_iimmed   0x2222,0x2222,fr15
 311         set_spr_immed   0,msr0
 312         set_spr_immed   0,msr1
 313         set_fr_iimmed   0x0000,0x0000,fr10
 314         set_fr_iimmed   0xdead,0xbeef,fr11
 315         set_fr_iimmed   0x0000,0x0000,fr12
 316         set_fr_iimmed   0x0000,0x0000,fr13
 317         cmqsubhus       fr10,fr12,fr14,cc3,1
 318         test_fr_limmed  0x1111,0x1111,fr14
 319         test_fr_limmed  0x2222,0x2222,fr15
 320         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 321         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 322         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 323         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 324
 325         set_fr_iimmed   0x1234,0x5678,fr10
 326         set_fr_iimmed   0x7ffe,0x7ffe,fr11
 327         set_fr_iimmed   0x1111,0x1111,fr12
 328         set_fr_iimmed   0x0002,0x0001,fr13
 329         cmqsubhus       fr10,fr12,fr14,cc3,0
 330         test_fr_limmed  0x1111,0x1111,fr14
 331         test_fr_limmed  0x2222,0x2222,fr15
 332         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 333         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 334         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 335         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 336
 337         set_spr_immed   0,msr0
 338         set_fr_iimmed   0x0001,0x0001,fr10
 339         set_fr_iimmed   0x0001,0x0001,fr11
 340         set_fr_iimmed   0x0001,0x0002,fr12
 341         set_fr_iimmed   0x0002,0x0001,fr13
 342         cmqsubhus       fr10,fr12,fr14,cc7,1
 343         test_fr_limmed  0x1111,0x1111,fr14
 344         test_fr_limmed  0x2222,0x2222,fr15
 345         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 346         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 347         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 348         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 349
 350         set_fr_iimmed   0x3333,0x3333,fr16
 351         set_fr_iimmed   0x4444,0x4444,fr17
 352         set_spr_immed   0,msr0
 353         set_spr_immed   0,msr1
 354         set_fr_iimmed   0x0001,0x0001,fr10
 355         set_fr_iimmed   0x0002,0x0002,fr11
 356         set_fr_iimmed   0x0000,0x0001,fr12
 357         set_fr_iimmed   0x0002,0x0003,fr13
 358         cmqsubhus.p     fr10,fr10,fr14,cc7,0
 359         cmqsubhus       fr10,fr12,fr16,cc7,1
 360         test_fr_limmed  0x1111,0x1111,fr14
 361         test_fr_limmed  0x2222,0x2222,fr15
 362         test_fr_limmed  0x3333,0x3333,fr16
 363         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 364         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 365         test_spr_bits   2,1,0,msr1              ; msr1.ovf not set
 366         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 367         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 368         test_fr_limmed  0x4444,0x4444,fr17
 369
 370         pass