sim/testsuite/sim/frv/ftige.cgs

   1 # frv testcase for ftige $FCCi_2,$GRi,$s12
   2 # mach: all
   3
   4         .include "testutils.inc"
   5
   6         start
   7
   8         .global ftige
   9 ftige:
  10         and_spr_immed   -4081,tbr               ; clear tbr.tt
  11         set_gr_spr      tbr,gr7
  12         inc_gr_immed    2112,gr7                ; address of exception handler
  13         set_bctrlr_0_0  gr7     ; bctrlr 0,0
  14
  15         set_spr_immed   128,lcr
  16         set_gr_immed    0,gr7
  17
  18         set_spr_addr    bad,lr
  19         set_fcc         0x0 0
  20         ftige           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  21
  22         set_spr_addr    bad,lr
  23         set_fcc         0x1 0
  24         ftige           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  25
  26         set_psr_et      1
  27         set_spr_addr    ok2,lr
  28         set_fcc         0x2 0
  29         ftige           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  30         fail
  31 ok2:
  32         set_psr_et      1
  33         set_spr_addr    ok3,lr
  34         set_fcc         0x3 0
  35         ftige           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  36         fail
  37 ok3:
  38         set_spr_addr    bad,lr
  39         set_fcc         0x4 0
  40         ftige           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  41
  42         set_spr_addr    bad,lr
  43         set_fcc         0x5 0
  44         ftige           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  45
  46         set_psr_et      1
  47         set_spr_addr    ok6,lr
  48         set_fcc         0x6 0
  49         ftige           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  50         fail
  51 ok6:
  52         set_psr_et      1
  53         set_spr_addr    ok7,lr
  54         set_fcc         0x7 0
  55         ftige           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  56         fail
  57 ok7:
  58         set_psr_et      1
  59         set_spr_addr    ok8,lr
  60         set_fcc         0x8 0
  61         ftige           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  62         fail
  63 ok8:
  64         set_psr_et      1
  65         set_spr_addr    ok9,lr
  66         set_fcc         0x9 0
  67         ftige           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  68         fail
  69 ok9:
  70         set_psr_et      1
  71         set_spr_addr    oka,lr
  72         set_fcc         0xa 0
  73         ftige           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  74         fail
  75 oka:
  76         set_psr_et      1
  77         set_spr_addr    okb,lr
  78         set_fcc         0xb 0
  79         ftige           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  80         fail
  81 okb:
  82         set_psr_et      1
  83         set_spr_addr    okc,lr
  84         set_fcc         0xc 0
  85         ftige           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  86         fail
  87 okc:
  88         set_psr_et      1
  89         set_spr_addr    okd,lr
  90         set_fcc         0xd 0
  91         ftige           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  92         fail
  93 okd:
  94         set_psr_et      1
  95         set_spr_addr    oke,lr
  96         set_fcc         0xe 0
  97         ftige           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  98         fail
  99 oke:
 100         set_psr_et      1
 101         set_spr_addr    okf,lr
 102         set_fcc         0xf 0
 103         ftige           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 104         fail
 105 okf:
 106         pass
 107 bad:
 108         fail