sim/testsuite/sim/frv/ftiug.cgs

   1 # frv testcase for ftiug $FCCi_2,$GRi,$s12
   2 # mach: all
   3
   4         .include "testutils.inc"
   5
   6         start
   7
   8         .global ftiug
   9 ftiug:
  10         and_spr_immed   -4081,tbr               ; clear tbr.tt
  11         set_gr_spr      tbr,gr7
  12         inc_gr_immed    2112,gr7                ; address of exception handler
  13         set_bctrlr_0_0  gr7     ; bctrlr 0,0
  14
  15         set_spr_immed   128,lcr
  16         set_gr_immed    0,gr7
  17
  18         set_spr_addr    bad,lr
  19         set_fcc         0x0 0
  20         ftiug           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  21
  22         set_psr_et      1
  23         set_spr_addr    ok1,lr
  24         set_fcc         0x1 0
  25         ftiug           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  26         fail
  27 ok1:
  28         set_psr_et      1
  29         set_spr_addr    ok2,lr
  30         set_fcc         0x2 0
  31         ftiug           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  32         fail
  33 ok2:
  34         set_psr_et      1
  35         set_spr_addr    ok3,lr
  36         set_fcc         0x3 0
  37         ftiug           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  38         fail
  39 ok3:
  40         set_spr_addr    bad,lr
  41         set_fcc         0x4 0
  42         ftiug           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  43
  44         set_psr_et      1
  45         set_spr_addr    ok5,lr
  46         set_fcc         0x5 0
  47         ftiug           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  48         fail
  49 ok5:
  50         set_psr_et      1
  51         set_spr_addr    ok6,lr
  52         set_fcc         0x6 0
  53         ftiug           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  54         fail
  55 ok6:
  56         set_psr_et      1
  57         set_spr_addr    ok7,lr
  58         set_fcc         0x7 0
  59         ftiug           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  60         fail
  61 ok7:
  62         set_spr_addr    bad,lr
  63         set_fcc         0x8 0
  64         ftiug           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  65
  66         set_psr_et      1
  67         set_spr_addr    ok9,lr
  68         set_fcc         0x9 0
  69         ftiug           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  70         fail
  71 ok9:
  72         set_psr_et      1
  73         set_spr_addr    oka,lr
  74         set_fcc         0xa 0
  75         ftiug           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  76         fail
  77 oka:
  78         set_psr_et      1
  79         set_spr_addr    okb,lr
  80         set_fcc         0xb 0
  81         ftiug           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  82         fail
  83 okb:
  84         set_spr_addr    bad,lr
  85         set_fcc         0xc 0
  86         ftiug           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  87
  88         set_psr_et      1
  89         set_spr_addr    okd,lr
  90         set_fcc         0xd 0
  91         ftiug           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  92         fail
  93 okd:
  94         set_psr_et      1
  95         set_spr_addr    oke,lr
  96         set_fcc         0xe 0
  97         ftiug           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  98         fail
  99 oke:
 100         set_psr_et      1
 101         set_spr_addr    okf,lr
 102         set_fcc         0xf 0
 103         ftiug           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 104         fail
 105 okf:
 106         pass
 107 bad:
 108         fail