sim/testsuite/sim/frv/ftu.cgs

   1 # frv testcase for ftu $FCCi_2,$GRi,$GRj
   2 # mach: all
   3
   4         .include "testutils.inc"
   5
   6         start
   7
   8         .global ftu
   9 ftu:
  10         and_spr_immed   -4081,tbr               ; clear tbr.tt
  11         set_gr_spr      tbr,gr7
  12         inc_gr_immed    2112,gr7                ; address of exception handler
  13         set_bctrlr_0_0  gr7     ; bctrlr 0,0
  14
  15         set_spr_immed   128,lcr
  16         set_gr_immed    0,gr7
  17         set_gr_immed    4,gr8
  18
  19         set_spr_addr    bad,lr
  20         set_fcc         0x0 0
  21         ftu             fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  22
  23         set_psr_et      1
  24         set_spr_addr    ok1,lr
  25         set_fcc         0x1 0
  26         ftu             fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  27         fail
  28 ok1:
  29         set_spr_addr    bad,lr
  30         set_fcc         0x2 0
  31         ftu             fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  32
  33         set_psr_et      1
  34         set_spr_addr    ok3,lr
  35         set_fcc         0x3 0
  36         ftu             fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  37         fail
  38 ok3:
  39         set_spr_addr    bad,lr
  40         set_fcc         0x4 0
  41         ftu             fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  42
  43         set_psr_et      1
  44         set_spr_addr    ok5,lr
  45         set_fcc         0x5 0
  46         ftu             fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  47         fail
  48 ok5:
  49         set_spr_addr    bad,lr
  50         set_fcc         0x6 0
  51         ftu             fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  52
  53         set_psr_et      1
  54         set_spr_addr    ok7,lr
  55         set_fcc         0x7 0
  56         ftu             fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  57         fail
  58 ok7:
  59         set_spr_addr    bad,lr
  60         set_fcc         0x8 0
  61         ftu             fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  62
  63         set_psr_et      1
  64         set_spr_addr    ok9,lr
  65         set_fcc         0x9 0
  66         ftu             fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  67         fail
  68 ok9:
  69         set_spr_addr    bad,lr
  70         set_fcc         0xa 0
  71         ftu             fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  72
  73         set_psr_et      1
  74         set_spr_addr    okb,lr
  75         set_fcc         0xb 0
  76         ftu             fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  77         fail
  78 okb:
  79         set_spr_addr    bad,lr
  80         set_fcc         0xc 0
  81         ftu             fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  82
  83         set_psr_et      1
  84         set_spr_addr    okd,lr
  85         set_fcc         0xd 0
  86         ftu             fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  87         fail
  88 okd:
  89         set_spr_addr    bad,lr
  90         set_fcc         0xe 0
  91         ftu             fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  92
  93         set_psr_et      1
  94         set_spr_addr    okf,lr
  95         set_fcc         0xf 0
  96         ftu             fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  97         fail
  98 okf:
  99         pass
 100 bad:
 101         fail