sim/testsuite/sim/frv/ftuge.cgs

   1 # frv testcase for ftuge $FCCi_2,$GRi,$GRj
   2 # mach: all
   3
   4         .include "testutils.inc"
   5
   6         start
   7
   8         .global ftuge
   9 ftuge:
  10         and_spr_immed   -4081,tbr               ; clear tbr.tt
  11         set_gr_spr      tbr,gr7
  12         inc_gr_immed    2112,gr7                ; address of exception handler
  13         set_bctrlr_0_0  gr7     ; bctrlr 0,0
  14
  15         set_spr_immed   128,lcr
  16         set_gr_immed    0,gr7
  17         set_gr_immed    4,gr8
  18
  19         set_spr_addr    bad,lr
  20         set_fcc         0x0 0
  21         ftuge           fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  22
  23         set_psr_et      1
  24         set_spr_addr    ok1,lr
  25         set_fcc         0x1 0
  26         ftuge           fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  27         fail
  28 ok1:
  29         set_psr_et      1
  30         set_spr_addr    ok2,lr
  31         set_fcc         0x2 0
  32         ftuge           fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  33         fail
  34 ok2:
  35         set_psr_et      1
  36         set_spr_addr    ok3,lr
  37         set_fcc         0x3 0
  38         ftuge           fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  39         fail
  40 ok3:
  41         set_spr_addr    bad,lr
  42         set_fcc         0x4 0
  43         ftuge           fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  44
  45         set_psr_et      1
  46         set_spr_addr    ok5,lr
  47         set_fcc         0x5 0
  48         ftuge           fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  49         fail
  50 ok5:
  51         set_psr_et      1
  52         set_spr_addr    ok6,lr
  53         set_fcc         0x6 0
  54         ftuge           fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  55         fail
  56 ok6:
  57         set_psr_et      1
  58         set_spr_addr    ok7,lr
  59         set_fcc         0x7 0
  60         ftuge           fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  61         fail
  62 ok7:
  63         set_psr_et      1
  64         set_spr_addr    ok8,lr
  65         set_fcc         0x8 0
  66         ftuge           fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  67         fail
  68 ok8:
  69         set_psr_et      1
  70         set_spr_addr    ok9,lr
  71         set_fcc         0x9 0
  72         ftuge           fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  73         fail
  74 ok9:
  75         set_psr_et      1
  76         set_spr_addr    oka,lr
  77         set_fcc         0xa 0
  78         ftuge           fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  79         fail
  80 oka:
  81         set_psr_et      1
  82         set_spr_addr    okb,lr
  83         set_fcc         0xb 0
  84         ftuge           fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  85         fail
  86 okb:
  87         set_psr_et      1
  88         set_spr_addr    okc,lr
  89         set_fcc         0xc 0
  90         ftuge           fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  91         fail
  92 okc:
  93         set_psr_et      1
  94         set_spr_addr    okd,lr
  95         set_fcc         0xd 0
  96         ftuge           fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  97         fail
  98 okd:
  99         set_psr_et      1
 100         set_spr_addr    oke,lr
 101         set_fcc         0xe 0
 102         ftuge           fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
 103         fail
 104 oke:
 105         set_psr_et      1
 106         set_spr_addr    okf,lr
 107         set_fcc         0xf 0
 108         ftuge           fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
 109         fail
 110 okf:
 111         pass
 112 bad:
 113         fail