sim/testsuite/sim/frv/interrupts/compound.cgs

   1 # frv testcase to generate compound exception
   2 # mach: fr500 frv
   3         .include "testutils.inc"
   4
   5         start
   6
   7         .global align
   8 align:
   9         and_spr_immed   -4081,tbr               ; clear tbr.tt
  10         set_gr_spr      tbr,gr17
  11         inc_gr_immed    0x200,gr17              ; address of exception handler
  12         set_bctrlr_0_0  gr17
  13         set_spr_immed   128,lcr
  14         set_spr_addr    ok1,lr
  15         or_spr_immed    0x04000000,fsr0         ; enabled div/0 fp_exception
  16         set_psr_et      1
  17
  18         set_gr_immed    0,gr15
  19         set_fr_iimmed   0x7f7f,0xffff,fr0
  20         set_fr_iimmed   0x0000,0x0000,fr1
  21
  22         and_spr_immed   0xfffffffe,isr          ; enable mem_address_not_aligned
  23         set_gr_addr     store,gr16
  24         set_gr_addr     dividei,gr17
  25         set_gr_immed    0xdeadbeef,gr8
  26         inc_gr_immed    2,sp                    ; misalign
  27 store:  sti.p           gr8,@(sp,0)             ; misaligned write
  28 dividef:fdivs.p         fr0,fr1,fr2             ; fp_exception
  29 dividei:sdiv            gr1,gr0,gr1             ; division exception
  30         test_gr_immed   1,gr15
  31
  32         pass
  33
  34 ; exception handler
  35 ok1:
  36         ; check interrupt on store
  37         test_spr_immed  0x102,esfr1             ; esr8 and esr1 are active
  38         test_spr_gr     epcr8,gr16
  39         test_spr_bits   0x0001,0,0x1,esr8       ; esr8 is valid
  40         test_spr_bits   0x003e,1,0xb,esr8       ; esr8.ec is set
  41         test_spr_bits   0x0800,11,0x1,esr8      ; esr8.eav is set
  42         test_spr_gr     ear8,sp
  43         test_spr_bits   0x01000,12,0x1,esr8     ; esr8.edv is set
  44         test_spr_bits   0x1e000,13,0x3,esr8     ; esr8.edn is 3
  45         test_spr_gr     edr3,gr8                ; edr3 is set
  46
  47         ; check on fp_exception
  48         test_spr_bits   0x100000,20,0x1,fsr0    ; fsr0.qne is set
  49         test_spr_bits   0xe0000,17,0x1,fsr0     ; fsr0.ftt is set
  50         test_spr_bits   0xfc00,10,0x0,fsr0      ; fsr0.aexc is clear
  51
  52         test_spr_bits   0x80000000,31,0x0,fqst2 ; fq2.miv is set
  53         test_spr_bits   0x18000,15,0x0,fqst2    ; fq2.sie is set
  54         test_spr_bits   0x380,7,0x1,fqst2       ; fq2.ftt is set
  55         test_spr_bits   0x7e,1,0x4,fqst2        ; fq2.cexc is set
  56         test_spr_bits   0x1,0,0x1,fqst2         ; fq2.valid is set
  57         test_spr_immed  0x05e40241,fqop2        ; fq2.opc
  58
  59         ; check interrupt on dividei
  60         test_spr_gr     epcr1,gr17
  61         test_spr_bits   0x0001,0,0x1,esr1       ; esr1 is valid
  62         test_spr_bits   0x003e,1,0x13,esr1      ; esr1.ec is set
  63
  64         inc_gr_immed    1,gr15
  65         rett            0
  66         fail