sim/testsuite/sim/frv/interrupts/fp_exception.cgs

   1 # frv testcase to generate fp_exception
   2 # mach: fr500
   3         .include "testutils.inc"
   4
   5         float_constants
   6         start
   7         load_float_constants
   8
   9         .global align
  10 align:
  11         ; clear the packing bit if the insn at 'pack:'. We can't simply use
  12         ; '.p' because the assembler will catch the error.
  13         set_gr_mem      pack,gr10
  14         and_gr_immed    0x7fffffff,gr10
  15         set_mem_gr      gr10,pack
  16         set_gr_addr     pack,gr10
  17         flush_data_cache gr10
  18
  19         and_spr_immed   -4081,tbr               ; clear tbr.tt
  20         set_gr_spr      tbr,gr17
  21         inc_gr_immed    0x070,gr17              ; address of exception handler
  22         set_bctrlr_0_0  gr17
  23         inc_gr_immed    0x060,gr17              ; address of exception handler
  24         set_bctrlr_0_0  gr17
  25         set_spr_immed   128,lcr
  26         set_spr_addr    ok1,lr
  27         set_psr_et      1
  28         inc_gr_immed    -4,sp           ; for alignment
  29
  30         set_gr_immed    0,gr20          ; PC increment
  31         set_gr_immed    0,gr15
  32
  33         set_spr_addr    ok3,lr
  34         stdfi           fr1,@(sp,0)     ; misaligned reg -- slot I0
  35         test_gr_immed   1,gr15
  36
  37         set_spr_addr    ok4,lr
  38         nop.p
  39         lddfi           @(sp,0),fr9     ; misaligned reg -- slot I1
  40         test_gr_immed   2,gr15
  41
  42         set_spr_addr    ok5,lr
  43         fnegs.p         fr9,fr9
  44 pack:   fnegs           fr10,fr10
  45         fnegs           fr10,fr11       ; packing violation
  46         test_gr_immed   3,gr15
  47
  48         set_spr_addr    ok1,lr
  49         set_gr_immed    4,gr20          ; PC increment
  50 bad:    fmadds          fr16,fr4,fr1    ; unimplemented
  51         test_gr_immed   4,gr15
  52
  53         and_spr_immed   0xfbffffff,fsr0         ; disable div/0 fp_exception
  54         set_fr_iimmed   0x7f7f,0xffff,fr0
  55         set_fr_iimmed   0x0000,0x0000,fr1
  56         fdivs           fr0,fr1,fr2             ; div/0 -- no exception
  57         test_spr_bits   0x100000,20,0x1,fsr0    ; fsr0.qne is still set
  58         test_spr_bits   0xfc00,10,0x4,fsr0      ; fsr0.aexc is still set
  59         test_spr_bits   0xe0000,17,0x0,fsr0     ; fsr0.ftt is clear
  60         and_spr_immed   0xffefffff,fsr0         ; Clear fsr0.qne
  61
  62         set_spr_addr    ok2,lr
  63         set_gr_immed    0,gr20                  ; PC increment
  64         or_spr_immed    0x04000000,fsr0         ; enable div/0 fp_exception
  65         set_fr_iimmed   0xdead,0xbeef,fr2
  66         fdivs           fr0,fr1,fr2             ; fp_exception - div/0
  67         test_fr_iimmed  0xdeadbeef,fr2          ; fr2 not updated
  68         test_gr_immed   5,gr15
  69
  70         and_spr_immed   0xfdffffff,fsr0         ; disable inexact fp_exception
  71         fsqrts          fr32,fr2                ; inexact -- no exception
  72         test_spr_bits   0x100000,20,0x1,fsr0    ; fsr0.qne is still set
  73         test_spr_bits   0xfc00,10,0x6,fsr0      ; fsr0.aexc is set
  74         test_spr_bits   0xe0000,17,0x0,fsr0     ; fsr0.ftt is clear
  75
  76         set_fr_fr       fr2,fr3                 ; sqrt 2
  77         set_fr_iimmed   0xdead,0xbeef,fr2
  78         set_spr_addr    ok6,lr
  79         or_spr_immed    0x02000000,fsr0         ; enable inexact fp_exception
  80         fsqrts          fr32,fr2                ; fp_exception - inexact
  81         test_gr_immed   6,gr15                  ; handler called
  82         test_fr_fr      fr2,fr3                 ; fr2 updated
  83
  84         set_fr_iimmed   0xdead,0xbeef,fr2
  85         set_spr_addr    ok7,lr
  86         fsqrts          fr32,fr2                ; fp_exception - inexact again
  87         test_gr_immed   7,gr15                  ; handler called
  88         test_fr_fr      fr2,fr3                 ; fr2 updated
  89
  90         pass
  91
  92 ; exception handler 1 -- bad insn
  93 ok1:
  94         test_spr_immed  1,esfr1                 ; esr0 active
  95         test_spr_bits   0x3e,1,0x5,esr0         ; esr0.ec is set
  96         test_spr_bits   0x1,0,0x1,esr0          ; esr0.valid is set
  97         test_spr_addr   bad,epcr0
  98         bra             ret
  99
 100 ; exception handler 2 - fp_exception: divide by 0
 101 ok2:
 102         test_spr_bits   0x100000,20,0x1,fsr0    ; fsr0.qne is set
 103         test_spr_bits   0xe0000,17,0x1,fsr0     ; fsr0.ftt is set
 104         test_spr_bits   0xfc00,10,0x4,fsr0      ; fsr0.aexc is still set
 105
 106         test_spr_bits   0x80000000,31,0x0,fqst2 ; fq2.miv is set
 107         test_spr_bits   0x18000,15,0x0,fqst2    ; fq2.sie is set
 108         test_spr_bits   0x380,7,0x1,fqst2       ; fq2.ftt is set
 109         test_spr_bits   0x7e,1,0x4,fqst2        ; fq2.cexc is set
 110         test_spr_bits   0x1,0,0x1,fqst2         ; fq2.valid is set
 111         test_spr_immed  0x85e40241,fqop2        ; fq2.opc
 112         bra             ret
 113
 114 ; exception handler 3 - fp_exception: register exception
 115 ok3:
 116         test_spr_bits   0x100000,20,0x1,fsr0    ; fsr0.qne is set
 117         test_spr_bits   0xe0000,17,0x6,fsr0     ; fsr0.ftt is set
 118         test_spr_bits   0xfc00,10,0x0,fsr0      ; fsr0.aexc is clear
 119
 120         test_spr_bits   0x80000000,31,0x0,fqst2 ; fq2.miv is set
 121         test_spr_bits   0x18000,15,0x0,fqst2    ; fq2.sie is set
 122         test_spr_bits   0x380,7,0x6,fqst2       ; fq2.ftt is set
 123         test_spr_bits   0x7e,1,0x0,fqst2        ; fq2.cexc is set
 124         test_spr_bits   0x1,0,0x1,fqst2         ; fq2.valid is set
 125         test_spr_immed  0x83581000,fqop2        ; fq2.opc
 126         bra             ret
 127
 128 ; exception handler 4 - fp_exception: another register exception
 129 ok4:
 130         test_spr_bits   0x100000,20,0x1,fsr0    ; fsr0.qne is set
 131         test_spr_bits   0xe0000,17,0x6,fsr0     ; fsr0.ftt is set
 132         test_spr_bits   0xfc00,10,0x0,fsr0      ; fsr0.aexc is still clear
 133
 134         test_spr_bits   0x80000000,31,0x0,fqst3 ; fq3.miv is set
 135         test_spr_bits   0x18000,15,0x0,fqst3    ; fq3.sie is set
 136         test_spr_bits   0x380,7,0x6,fqst3       ; fq3.ftt is set
 137         test_spr_bits   0x7e,1,0x0,fqst3        ; fq3.cexc is set
 138         test_spr_bits   0x1,0,0x1,fqst3         ; fq3.valid is set
 139         test_spr_immed  0x92ec1000,fqop3        ; fq3.opc
 140         bra             ret
 141
 142 ; exception handler 5 - fp_exception: sequence violation
 143 ok5:
 144         test_spr_bits   0x100000,20,0x1,fsr0    ; fsr0.qne is set
 145         test_spr_bits   0xe0000,17,0x4,fsr0     ; fsr0.ftt is set
 146         test_spr_bits   0xfc00,10,0x0,fsr0      ; fsr0.aexc is still clear
 147
 148         test_spr_bits   0x80000000,31,0x0,fqst3 ; fq3.miv is set
 149         test_spr_bits   0x18000,15,0x0,fqst3    ; fq3.sie is set
 150         test_spr_bits   0x380,7,0x4,fqst3       ; fq3.ftt is set
 151         test_spr_bits   0x7e,1,0x0,fqst3        ; fq3.cexc is set
 152         test_spr_bits   0x1,0,0x1,fqst3         ; fq3.valid is set
 153         test_spr_immed  0x97e400ca,fqop3        ; fq3.opc
 154         bra             ret
 155
 156 ; exception handler 6 - fp_exception: inexact
 157 ok6:
 158         test_spr_bits   0x100000,20,0x1,fsr0    ; fsr0.qne is set
 159         test_spr_bits   0xe0000,17,0x1,fsr0     ; fsr0.ftt is set
 160         test_spr_bits   0xfc00,10,0x6,fsr0      ; fsr0.aexc is still set
 161
 162         test_spr_bits   0x80000000,31,0x0,fqst0 ; fq0.miv is set
 163         test_spr_bits   0x18000,15,0x0,fqst0    ; fq0.sie is set
 164         test_spr_bits   0x380,7,0x1,fqst0       ; fq0.ftt is set
 165         test_spr_bits   0x7e,1,0x2,fqst0        ; fq0.cexc is set
 166         test_spr_bits   0x1,0,0x1,fqst0         ; fq0.valid is set
 167         test_spr_immed  0x85e40160,fqop0        ; fq0.opc
 168         bra             ret
 169
 170 ; exception handler 7 - fp_exception: inexact again
 171 ok7:
 172         test_spr_bits   0x100000,20,0x1,fsr0    ; fsr0.qne is set
 173         test_spr_bits   0xe0000,17,0x1,fsr0     ; fsr0.ftt is set
 174         test_spr_bits   0xfc00,10,0x6,fsr0      ; fsr0.aexc is still set
 175
 176         test_spr_bits   0x80000000,31,0x0,fqst1 ; fq1.miv is set
 177         test_spr_bits   0x18000,15,0x0,fqst1    ; fq1.sie is set
 178         test_spr_bits   0x380,7,0x1,fqst1       ; fq1.ftt is set
 179         test_spr_bits   0x7e,1,0x2,fqst1        ; fq1.cexc is set
 180         test_spr_bits   0x1,0,0x1,fqst1         ; fq1.valid is set
 181         test_spr_immed  0x85e40160,fqop1        ; fq1.opc
 182         bra             ret
 183
 184 ret:
 185         inc_gr_immed    1,gr15
 186         movsg           pcsr,gr60
 187         add             gr60,gr20,gr60
 188         movgs           gr60,pcsr
 189         rett            0
 190         fail
 191