sim/testsuite/sim/frv/interrupts/insn_access_error.cgs

   1 # frv testcase to generate insn_access_error interrupt
   2 # mach: fr500 fr400
   3 # sim: --memory-region 0xfeff0600,0x8000 --memory-region 0xfe800000,0x7f0040
   4         .include "testutils.inc"
   5
   6         start
   7
   8         .global dsr
   9 dsr:
  10         and_spr_immed   -4081,tbr               ; clear tbr.tt
  11         set_gr_spr      tbr,gr17
  12         inc_gr_immed    0x020,gr17              ; address of exception handler
  13         set_bctrlr_0_0  gr17
  14         set_spr_immed   128,lcr
  15         set_psr_et      1
  16
  17         set_spr_addr    handler,lr
  18         set_gr_immed    0,gr16
  19
  20         set_gr_addr     ok0,gr8
  21         set_gr_addr     0xfeff0600,gr17
  22         jmpl            @(gr17,gr0)             ; cause interrupt
  23 ok0:
  24         test_gr_immed   1,gr16
  25
  26         set_gr_addr     ok1,gr8
  27         set_gr_addr     0xfeff7ffc,gr17
  28         jmpl            @(gr17,gr0)             ; cause interrupt
  29 ok1:
  30         test_gr_immed   2,gr16
  31
  32         set_gr_addr     ok2,gr8
  33         set_gr_addr     0xfe800000,gr17
  34         jmpl            @(gr17,gr0)             ; cause interrupt
  35 ok2:
  36         test_gr_immed   3,gr16
  37
  38         set_gr_addr     ok3,gr8
  39         set_gr_addr     0xfefefffc,gr17
  40         jmpl            @(gr17,gr0)             ; cause interrupt
  41 ok3:
  42         test_gr_immed   4,gr16
  43
  44         pass
  45 handler:
  46         ; check interrupts
  47         test_spr_immed  0x1,esfr1               ; esr0 is active
  48         test_spr_gr     epcr0,gr17
  49         test_spr_bits   0x0001,0,0x1,esr0       ; esr0 is valid
  50         test_spr_bits   0x003e,1,0x2,esr0       ; esr0.ec is set
  51         test_spr_bits   0x0800,11,0x0,esr0      ; esr0.eav is not set
  52
  53         addi            gr16,1,gr16
  54         movgs           gr8,pcsr
  55         rett            0
  56         fail