sim/testsuite/sim/frv/interrupts/regalign.cgs

   1 # frv testcase to generate interrupts for bad register alignment
   2 # mach: frv
   3         .include "testutils.inc"
   4
   5         start
   6
   7         .global align
   8 align:
   9         and_spr_immed   -4081,tbr               ; clear tbr.tt
  10         set_gr_spr      tbr,gr17
  11         inc_gr_immed    0x080,gr17              ; address of exception handler
  12         set_bctrlr_0_0  gr17
  13         inc_gr_immed    0x050,gr17              ; address of exception handler
  14         set_bctrlr_0_0  gr17
  15         set_spr_immed   128,lcr
  16         set_spr_addr    ok1,lr
  17         set_psr_et      1
  18
  19         set_gr_immed    4,gr20          ; PC increment
  20         set_gr_immed    0,gr15
  21         inc_gr_immed    -12,sp          ; for memory alignment
  22
  23         set_gr_addr     bad1,gr17
  24 bad1:   stdi    gr1,@(sp,0)             ; misaligned reg
  25         test_gr_immed   1,gr15
  26
  27         set_gr_addr     bad2,gr17
  28 bad2:   lddi    @(sp,0),gr9             ; misaligned reg
  29         test_gr_immed   2,gr15
  30
  31         set_gr_addr     bad3,gr17
  32 bad3:   stdc    cpr1,@(sp,gr0)          ; misaligned reg
  33         test_gr_immed   3,gr15
  34
  35         set_gr_addr     bad4,gr17
  36 bad4:   lddc    @(sp,gr0),cpr9          ; misaligned reg
  37         test_gr_immed   4,gr15
  38
  39         set_gr_addr     bad5,gr17
  40 bad5:   stqi    gr2,@(sp,0)             ; misaligned reg
  41         test_gr_immed   5,gr15
  42
  43         set_gr_addr     bad6,gr17
  44 bad6:   ldqi    @(sp,0),gr10            ; misaligned reg
  45         test_gr_immed   6,gr15
  46
  47         set_gr_addr     bad7,gr17
  48 bad7:   stqc    cpr2,@(sp,gr0)          ; misaligned reg
  49         test_gr_immed   7,gr15
  50
  51         set_gr_addr     bad8,gr17
  52 bad8:   ldqc    @(sp,gr0),cpr10         ; misaligned reg
  53         test_gr_immed   8,gr15
  54
  55         set_gr_immed    0,gr20          ; PC increment
  56         set_gr_addr     bad9,gr17
  57 bad9:   stdfi   fr1,@(sp,0)             ; misaligned reg
  58         test_gr_immed   9,gr15
  59
  60         set_gr_addr     bada,gr17
  61 bada:   lddfi   @(sp,0),fr9             ; misaligned reg
  62         test_gr_immed   10,gr15
  63
  64         set_gr_addr     badb,gr17
  65 badb:   stqfi   fr2,@(sp,0)             ; misaligned reg
  66         test_gr_immed   11,gr15
  67
  68         set_gr_addr     badc,gr17
  69 badc:   ldqfi   @(sp,0),fr10            ; misaligned reg
  70         test_gr_immed   12,gr15
  71
  72         pass
  73
  74 ; exception handler
  75 ok1:
  76         cmpi            gr20,0,icc0
  77         beq             icc0,0,float
  78
  79         ; check register_exception
  80         test_spr_immed  0x1,esfr1               ; esr0 is active
  81         test_spr_gr     epcr0,gr17
  82         test_spr_bits   0x0001,0,0x1,esr0       ; esr0 is valid
  83         test_spr_bits   0x003e,1,0xc,esr0       ; esr0.ec is set
  84         test_spr_bits   0x00c0,6,0x1,esr0       ; esr0.rec is set
  85         test_spr_bits   0x0800,11,0x0,esr0      ; esr0.eav is not set
  86         movsg           pcsr,gr60
  87         add             gr60,gr20,gr60
  88         movgs           gr60,pcsr
  89         bra             ret
  90 float:
  91         ; check fp_exception
  92         test_spr_immed  0,esfr1                 ; no esr's active
  93 ret:
  94         inc_gr_immed    1,gr15
  95         rett            0
  96         fail