sim/testsuite/sim/frv/interrupts/reset.cgs

   1 # frv testcase to generate reset interrupts
   2 # mach: fr500 fr400
   3 # sim: --memory-region 0xff000000,64
   4
   5         .include "testutils.inc"
   6
   7         start
   8
   9         .global reset
  10 reset:
  11         and_spr_immed   0xfffffffb,psr  ; turn off PSR.S
  12         set_gr_immed    0xfeff0500,gr10 ; address of reset register
  13         set_spr_immed   0x7fffffff,lcr
  14         set_bctrlr_0_0  gr0
  15
  16 ; Can't recover from hardware interrupt with enough state intact to verify it
  17 ;       set_spr_addr    ok1,lr
  18 ;       set_mem_immed   0x3,gr10        ; cause hardware reset
  19 ;       dcf             @(gr10,gr0)     ; Wait for store to happen
  20 ;       fail
  21 ;
  22 ;ok1:   ; reset should branch to reset address which should then branch here
  23 ;       test_mem_immed  0x00000200,gr10
  24 ;       set_spr_addr    ok2,lr
  25 ;       set_mem_immed   0x2,gr10        ; cause hardware reset
  26 ;       dcf             @(gr10,gr0)     ; Wait for store to happen
  27 ;       fail
  28 ;
  29 ok2:    ; reset should branch to reset address which should then branch here
  30 ;       test_mem_immed  0x00000200,gr10
  31         set_spr_addr    ok3,lr
  32         set_mem_immed   0x1,gr10        ; cause software reset
  33         dcf             @(gr10,gr0)     ; Wait for store to happen
  34         fail
  35
  36 ok3:    ; reset should branch to reset address which should then branch here
  37         test_mem_immed  0x00000100,gr10
  38         test_spr_bits   0x4,2,1,psr     ; psr.s is set
  39         test_spr_bits   0x2,1,0,psr     ; psr.ps not set
  40         set_spr_addr    bad,lr
  41         set_mem_immed   0x0,gr10        ; no reset
  42         test_mem_immed  0x0,gr10
  43
  44         ; now retest with HSR0.SA set
  45         set_mem_immed   0,gr0
  46         set_gr_addr     0xff000000,gr11
  47         set_bctrlr_0_0  gr11
  48         or_spr_immed    0x00001000,hsr0 ; set HSR0.SA
  49
  50 ; Can't recover from hardware interrupt with enough state intact to verify it
  51 ;       set_spr_addr    ok4,lr
  52 ;       dcf             @(gr10,gr0)     ; Wait for store to happen
  53 ;       set_mem_immed   0x3,gr10        ; cause hardware reset
  54 ;       fail
  55 ;
  56 ;ok4:   ; reset should branch to reset address which should then branch here
  57 ;       test_mem_immed  0x00000200,gr10
  58 ;       set_spr_addr    ok5,lr
  59 ;       set_mem_immed   0x2,gr10        ; cause hardware reset
  60 ;       dcf             @(gr10,gr0)     ; Wait for store to happen
  61 ;       fail
  62 ;
  63 ok5:    ; reset should branch to reset address which should then branch here
  64 ;       test_mem_immed  0x00000200,gr10
  65         set_spr_addr    ok6,lr
  66         set_mem_immed   0x1,gr10        ; cause software reset
  67         dcf             @(gr10,gr0)     ; Wait for store to happen
  68         fail
  69
  70 ok6:    ; reset should branch to reset address which should then branch here
  71         test_mem_immed  0x00000100,gr10
  72         test_spr_bits   0x4,2,1,psr     ; psr.s is set
  73         test_spr_bits   0x2,1,1,psr     ; psr.ps is set
  74         set_spr_addr    bad,lr
  75         set_mem_immed   0x0,gr10        ; no reset
  76         test_mem_immed  0x0,gr10
  77
  78         pass
  79
  80 bad:    ; Should never get here
  81         fail