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New sim testsuite for Fujitsu FRV. Contributed by Red Hat.
[deliverable/binutils-gdb.git] / sim / testsuite / sim / frv / nfdcmps.cgs
1 # frv testcase for nfdcmps $FRi,$FRj,$FCCi_2
2 # mach: frv
3
4 .include "testutils.inc"
5
6 float_constants
7 start
8 load_float_constants
9 load_float_constants1
10
11 .global nfdcmps
12 nfdcmps:
13 set_fcc 0x7,0 ; Set mask opposite of expected
14 set_fcc 0x7,1 ; Set mask opposite of expected
15 nfdcmps fr0,fr0,fcc0
16 test_fcc 0x8,0
17 test_fcc 0x8,1
18 test_spr_immed 0,fner1
19 test_spr_immed 0,fner0
20
21 set_fcc 0xb,0 ; Set mask opposite of expected
22 set_fcc 0xb,1 ; Set mask opposite of expected
23 nfdcmps fr0,fr4,fcc0
24 test_fcc 0x4,0
25 test_fcc 0x4,1
26 test_spr_immed 0,fner1
27 test_spr_immed 0,fner0
28
29 set_fcc 0xb,0 ; Set mask opposite of expected
30 set_fcc 0xb,1 ; Set mask opposite of expected
31 nfdcmps fr0,fr8,fcc0
32 test_fcc 0x4,0
33 test_fcc 0x4,1
34 test_spr_immed 0,fner1
35 test_spr_immed 0,fner0
36
37 set_fcc 0xb,0 ; Set mask opposite of expected
38 set_fcc 0xb,1 ; Set mask opposite of expected
39 nfdcmps fr0,fr12,fcc0
40 test_fcc 0x4,0
41 test_fcc 0x4,1
42 test_spr_immed 0,fner1
43 test_spr_immed 0,fner0
44
45 set_fcc 0xb,0 ; Set mask opposite of expected
46 set_fcc 0xb,1 ; Set mask opposite of expected
47 nfdcmps fr0,fr16,fcc0
48 test_fcc 0x4,0
49 test_fcc 0x4,1
50 test_spr_immed 0,fner1
51 test_spr_immed 0,fner0
52
53 set_fcc 0xb,0 ; Set mask opposite of expected
54 set_fcc 0xb,1 ; Set mask opposite of expected
55 nfdcmps fr0,fr20,fcc0
56 test_fcc 0x4,0
57 test_fcc 0x4,1
58 test_spr_immed 0,fner1
59 test_spr_immed 0,fner0
60
61 set_fcc 0xb,0 ; Set mask opposite of expected
62 set_fcc 0xb,1 ; Set mask opposite of expected
63 nfdcmps fr0,fr24,fcc0
64 test_fcc 0x4,0
65 test_fcc 0x4,1
66 test_spr_immed 0,fner1
67 test_spr_immed 0,fner0
68
69 set_fcc 0xb,0 ; Set mask opposite of expected
70 set_fcc 0xb,1 ; Set mask opposite of expected
71 nfdcmps fr0,fr28,fcc0
72 test_fcc 0x4,0
73 test_fcc 0x4,1
74 test_spr_immed 0,fner1
75 test_spr_immed 0,fner0
76
77 set_fcc 0xb,0 ; Set mask opposite of expected
78 set_fcc 0xb,1 ; Set mask opposite of expected
79 nfdcmps fr0,fr32,fcc0
80 test_fcc 0x4,0
81 test_fcc 0x4,1
82 test_spr_immed 0,fner1
83 test_spr_immed 0,fner0
84
85 set_fcc 0xb,0 ; Set mask opposite of expected
86 set_fcc 0xb,1 ; Set mask opposite of expected
87 nfdcmps fr0,fr36,fcc0
88 test_fcc 0x4,0
89 test_fcc 0x4,1
90 test_spr_immed 0,fner1
91 test_spr_immed 0,fner0
92
93 set_fcc 0xb,0 ; Set mask opposite of expected
94 set_fcc 0xb,1 ; Set mask opposite of expected
95 nfdcmps fr0,fr40,fcc0
96 test_fcc 0x4,0
97 test_fcc 0x4,1
98 test_spr_immed 0,fner1
99 test_spr_immed 0,fner0
100
101 set_fcc 0xb,0 ; Set mask opposite of expected
102 set_fcc 0xb,1 ; Set mask opposite of expected
103 nfdcmps fr0,fr44,fcc0
104 test_fcc 0x4,0
105 test_fcc 0x4,1
106 test_spr_immed 0,fner1
107 test_spr_immed 0,fner0
108
109 set_fcc 0xb,0 ; Set mask opposite of expected
110 set_fcc 0xb,1 ; Set mask opposite of expected
111 nfdcmps fr0,fr48,fcc0
112 test_fcc 0x4,0
113 test_fcc 0x4,1
114 test_spr_immed 0,fner1
115 test_spr_immed 0,fner0
116
117 set_fcc 0xb,0 ; Set mask opposite of expected
118 set_fcc 0xb,1 ; Set mask opposite of expected
119 nfdcmps fr0,fr52,fcc0
120 test_fcc 0x4,0
121 test_fcc 0x4,1
122 test_spr_immed 0,fner1
123 test_spr_immed 0,fner0
124
125 set_fcc 0xe,0 ; Set mask opposite of expected
126 set_fcc 0xe,1 ; Set mask opposite of expected
127 nfdcmps fr0,fr56,fcc0
128 test_fcc 0x1,0
129 test_fcc 0x1,1
130 test_spr_immed 0,fner1
131 test_spr_immed 0,fner0
132
133 set_fcc 0xe,0 ; Set mask opposite of expected
134 set_fcc 0xe,1 ; Set mask opposite of expected
135 nfdcmps fr0,fr60,fcc0
136 test_fcc 0x1,0
137 test_fcc 0x1,1
138 test_spr_immed 0,fner1
139 test_spr_immed 0,fner0
140
141 set_fcc 0xd,0 ; Set mask opposite of expected
142 set_fcc 0xd,1 ; Set mask opposite of expected
143 nfdcmps fr4,fr0,fcc0
144 test_fcc 0x2,0
145 test_fcc 0x2,1
146 test_spr_immed 0,fner1
147 test_spr_immed 0,fner0
148
149 set_fcc 0x7,0 ; Set mask opposite of expected
150 set_fcc 0x7,1 ; Set mask opposite of expected
151 nfdcmps fr4,fr4,fcc0
152 test_fcc 0x8,0
153 test_fcc 0x8,1
154 test_spr_immed 0,fner1
155 test_spr_immed 0,fner0
156
157 set_fcc 0xb,0 ; Set mask opposite of expected
158 set_fcc 0xb,1 ; Set mask opposite of expected
159 nfdcmps fr4,fr8,fcc0
160 test_fcc 0x4,0
161 test_fcc 0x4,1
162 test_spr_immed 0,fner1
163 test_spr_immed 0,fner0
164
165 set_fcc 0xb,0 ; Set mask opposite of expected
166 set_fcc 0xb,1 ; Set mask opposite of expected
167 nfdcmps fr4,fr12,fcc0
168 test_fcc 0x4,0
169 test_fcc 0x4,1
170 test_spr_immed 0,fner1
171 test_spr_immed 0,fner0
172
173 set_fcc 0xb,0 ; Set mask opposite of expected
174 set_fcc 0xb,1 ; Set mask opposite of expected
175 nfdcmps fr4,fr16,fcc0
176 test_fcc 0x4,0
177 test_fcc 0x4,1
178 test_spr_immed 0,fner1
179 test_spr_immed 0,fner0
180
181 set_fcc 0xb,0 ; Set mask opposite of expected
182 set_fcc 0xb,1 ; Set mask opposite of expected
183 nfdcmps fr4,fr20,fcc0
184 test_fcc 0x4,0
185 test_fcc 0x4,1
186 test_spr_immed 0,fner1
187 test_spr_immed 0,fner0
188
189 set_fcc 0xb,0 ; Set mask opposite of expected
190 set_fcc 0xb,1 ; Set mask opposite of expected
191 nfdcmps fr4,fr24,fcc0
192 test_fcc 0x4,0
193 test_fcc 0x4,1
194 test_spr_immed 0,fner1
195 test_spr_immed 0,fner0
196
197 set_fcc 0xb,0 ; Set mask opposite of expected
198 set_fcc 0xb,1 ; Set mask opposite of expected
199 nfdcmps fr4,fr28,fcc0
200 test_fcc 0x4,0
201 test_fcc 0x4,1
202 test_spr_immed 0,fner1
203 test_spr_immed 0,fner0
204
205 set_fcc 0xb,0 ; Set mask opposite of expected
206 set_fcc 0xb,1 ; Set mask opposite of expected
207 nfdcmps fr4,fr32,fcc0
208 test_fcc 0x4,0
209 test_fcc 0x4,1
210 test_spr_immed 0,fner1
211 test_spr_immed 0,fner0
212
213 set_fcc 0xb,0 ; Set mask opposite of expected
214 set_fcc 0xb,1 ; Set mask opposite of expected
215 nfdcmps fr4,fr36,fcc0
216 test_fcc 0x4,0
217 test_fcc 0x4,1
218 test_spr_immed 0,fner1
219 test_spr_immed 0,fner0
220
221 set_fcc 0xb,0 ; Set mask opposite of expected
222 set_fcc 0xb,1 ; Set mask opposite of expected
223 nfdcmps fr4,fr40,fcc0
224 test_fcc 0x4,0
225 test_fcc 0x4,1
226 test_spr_immed 0,fner1
227 test_spr_immed 0,fner0
228
229 set_fcc 0xb,0 ; Set mask opposite of expected
230 set_fcc 0xb,1 ; Set mask opposite of expected
231 nfdcmps fr4,fr44,fcc0
232 test_fcc 0x4,0
233 test_fcc 0x4,1
234 test_spr_immed 0,fner1
235 test_spr_immed 0,fner0
236
237 set_fcc 0xb,0 ; Set mask opposite of expected
238 set_fcc 0xb,1 ; Set mask opposite of expected
239 nfdcmps fr4,fr48,fcc0
240 test_fcc 0x4,0
241 test_fcc 0x4,1
242 test_spr_immed 0,fner1
243 test_spr_immed 0,fner0
244
245 set_fcc 0xb,0 ; Set mask opposite of expected
246 set_fcc 0xb,1 ; Set mask opposite of expected
247 nfdcmps fr4,fr52,fcc0
248 test_fcc 0x4,0
249 test_fcc 0x4,1
250 test_spr_immed 0,fner1
251 test_spr_immed 0,fner0
252
253 set_fcc 0xe,0 ; Set mask opposite of expected
254 set_fcc 0xe,1 ; Set mask opposite of expected
255 nfdcmps fr4,fr56,fcc0
256 test_fcc 0x1,0
257 test_fcc 0x1,1
258 test_spr_immed 0,fner1
259 test_spr_immed 0,fner0
260
261 set_fcc 0xe,0 ; Set mask opposite of expected
262 set_fcc 0xe,1 ; Set mask opposite of expected
263 nfdcmps fr4,fr60,fcc0
264 test_fcc 0x1,0
265 test_fcc 0x1,1
266 test_spr_immed 0,fner1
267 test_spr_immed 0,fner0
268
269 set_fcc 0xd,0 ; Set mask opposite of expected
270 set_fcc 0xd,1 ; Set mask opposite of expected
271 nfdcmps fr8,fr0,fcc0
272 test_fcc 0x2,0
273 test_fcc 0x2,1
274 test_spr_immed 0,fner1
275 test_spr_immed 0,fner0
276
277 set_fcc 0xd,0 ; Set mask opposite of expected
278 set_fcc 0xd,1 ; Set mask opposite of expected
279 nfdcmps fr8,fr4,fcc0
280 test_fcc 0x2,0
281 test_fcc 0x2,1
282 test_spr_immed 0,fner1
283 test_spr_immed 0,fner0
284
285 set_fcc 0x7,0 ; Set mask opposite of expected
286 set_fcc 0x7,1 ; Set mask opposite of expected
287 nfdcmps fr8,fr8,fcc0
288 test_fcc 0x8,0
289 test_fcc 0x8,1
290 test_spr_immed 0,fner1
291 test_spr_immed 0,fner0
292
293 set_fcc 0xb,0 ; Set mask opposite of expected
294 set_fcc 0xb,1 ; Set mask opposite of expected
295 nfdcmps fr8,fr12,fcc0
296 test_fcc 0x4,0
297 test_fcc 0x4,1
298 test_spr_immed 0,fner1
299 test_spr_immed 0,fner0
300
301 set_fcc 0xb,0 ; Set mask opposite of expected
302 set_fcc 0xb,1 ; Set mask opposite of expected
303 nfdcmps fr8,fr16,fcc0
304 test_fcc 0x4,0
305 test_fcc 0x4,1
306 test_spr_immed 0,fner1
307 test_spr_immed 0,fner0
308
309 set_fcc 0xb,0 ; Set mask opposite of expected
310 set_fcc 0xb,1 ; Set mask opposite of expected
311 nfdcmps fr8,fr20,fcc0
312 test_fcc 0x4,0
313 test_fcc 0x4,1
314 test_spr_immed 0,fner1
315 test_spr_immed 0,fner0
316
317 set_fcc 0xb,0 ; Set mask opposite of expected
318 set_fcc 0xb,1 ; Set mask opposite of expected
319 nfdcmps fr8,fr24,fcc0
320 test_fcc 0x4,0
321 test_fcc 0x4,1
322 test_spr_immed 0,fner1
323 test_spr_immed 0,fner0
324
325 set_fcc 0xb,0 ; Set mask opposite of expected
326 set_fcc 0xb,1 ; Set mask opposite of expected
327 nfdcmps fr8,fr28,fcc0
328 test_fcc 0x4,0
329 test_fcc 0x4,1
330 test_spr_immed 0,fner1
331 test_spr_immed 0,fner0
332
333 set_fcc 0xb,0 ; Set mask opposite of expected
334 set_fcc 0xb,1 ; Set mask opposite of expected
335 nfdcmps fr8,fr32,fcc0
336 test_fcc 0x4,0
337 test_fcc 0x4,1
338 test_spr_immed 0,fner1
339 test_spr_immed 0,fner0
340
341 set_fcc 0xb,0 ; Set mask opposite of expected
342 set_fcc 0xb,1 ; Set mask opposite of expected
343 nfdcmps fr8,fr36,fcc0
344 test_fcc 0x4,0
345 test_fcc 0x4,1
346 test_spr_immed 0,fner1
347 test_spr_immed 0,fner0
348
349 set_fcc 0xb,0 ; Set mask opposite of expected
350 set_fcc 0xb,1 ; Set mask opposite of expected
351 nfdcmps fr8,fr40,fcc0
352 test_fcc 0x4,0
353 test_fcc 0x4,1
354 test_spr_immed 0,fner1
355 test_spr_immed 0,fner0
356
357 set_fcc 0xb,0 ; Set mask opposite of expected
358 set_fcc 0xb,1 ; Set mask opposite of expected
359 nfdcmps fr8,fr44,fcc0
360 test_fcc 0x4,0
361 test_fcc 0x4,1
362 test_spr_immed 0,fner1
363 test_spr_immed 0,fner0
364
365 set_fcc 0xb,0 ; Set mask opposite of expected
366 set_fcc 0xb,1 ; Set mask opposite of expected
367 nfdcmps fr8,fr48,fcc0
368 test_fcc 0x4,0
369 test_fcc 0x4,1
370 test_spr_immed 0,fner1
371 test_spr_immed 0,fner0
372
373 set_fcc 0xb,0 ; Set mask opposite of expected
374 set_fcc 0xb,1 ; Set mask opposite of expected
375 nfdcmps fr8,fr52,fcc0
376 test_fcc 0x4,0
377 test_fcc 0x4,1
378 test_spr_immed 0,fner1
379 test_spr_immed 0,fner0
380
381 set_fcc 0xe,0 ; Set mask opposite of expected
382 set_fcc 0xe,1 ; Set mask opposite of expected
383 nfdcmps fr8,fr56,fcc0
384 test_fcc 0x1,0
385 test_fcc 0x1,1
386 test_spr_immed 0,fner1
387 test_spr_immed 0,fner0
388
389 set_fcc 0xe,0 ; Set mask opposite of expected
390 set_fcc 0xe,1 ; Set mask opposite of expected
391 nfdcmps fr8,fr60,fcc0
392 test_fcc 0x1,0
393 test_fcc 0x1,1
394 test_spr_immed 0,fner1
395 test_spr_immed 0,fner0
396
397 set_fcc 0xd,0 ; Set mask opposite of expected
398 set_fcc 0xd,1 ; Set mask opposite of expected
399 nfdcmps fr12,fr0,fcc0
400 test_fcc 0x2,0
401 test_fcc 0x2,1
402 test_spr_immed 0,fner1
403 test_spr_immed 0,fner0
404
405 set_fcc 0xd,0 ; Set mask opposite of expected
406 set_fcc 0xd,1 ; Set mask opposite of expected
407 nfdcmps fr12,fr4,fcc0
408 test_fcc 0x2,0
409 test_fcc 0x2,1
410 test_spr_immed 0,fner1
411 test_spr_immed 0,fner0
412
413 set_fcc 0xd,0 ; Set mask opposite of expected
414 set_fcc 0xd,1 ; Set mask opposite of expected
415 nfdcmps fr12,fr8,fcc0
416 test_fcc 0x2,0
417 test_fcc 0x2,1
418 test_spr_immed 0,fner1
419 test_spr_immed 0,fner0
420
421 set_fcc 0x7,0 ; Set mask opposite of expected
422 set_fcc 0x7,1 ; Set mask opposite of expected
423 nfdcmps fr12,fr12,fcc0
424 test_fcc 0x8,0
425 test_fcc 0x8,1
426 test_spr_immed 0,fner1
427 test_spr_immed 0,fner0
428
429 set_fcc 0xb,0 ; Set mask opposite of expected
430 set_fcc 0xb,1 ; Set mask opposite of expected
431 nfdcmps fr12,fr16,fcc0
432 test_fcc 0x4,0
433 test_fcc 0x4,1
434 test_spr_immed 0,fner1
435 test_spr_immed 0,fner0
436
437 set_fcc 0xb,0 ; Set mask opposite of expected
438 set_fcc 0xb,1 ; Set mask opposite of expected
439 nfdcmps fr12,fr20,fcc0
440 test_fcc 0x4,0
441 test_fcc 0x4,1
442 test_spr_immed 0,fner1
443 test_spr_immed 0,fner0
444
445 set_fcc 0xb,0 ; Set mask opposite of expected
446 set_fcc 0xb,1 ; Set mask opposite of expected
447 nfdcmps fr12,fr24,fcc0
448 test_fcc 0x4,0
449 test_fcc 0x4,1
450 test_spr_immed 0,fner1
451 test_spr_immed 0,fner0
452
453 set_fcc 0xb,0 ; Set mask opposite of expected
454 set_fcc 0xb,1 ; Set mask opposite of expected
455 nfdcmps fr12,fr28,fcc0
456 test_fcc 0x4,0
457 test_fcc 0x4,1
458 test_spr_immed 0,fner1
459 test_spr_immed 0,fner0
460
461 set_fcc 0xb,0 ; Set mask opposite of expected
462 set_fcc 0xb,1 ; Set mask opposite of expected
463 nfdcmps fr12,fr32,fcc0
464 test_fcc 0x4,0
465 test_fcc 0x4,1
466 test_spr_immed 0,fner1
467 test_spr_immed 0,fner0
468
469 set_fcc 0xb,0 ; Set mask opposite of expected
470 set_fcc 0xb,1 ; Set mask opposite of expected
471 nfdcmps fr12,fr36,fcc0
472 test_fcc 0x4,0
473 test_fcc 0x4,1
474 test_spr_immed 0,fner1
475 test_spr_immed 0,fner0
476
477 set_fcc 0xb,0 ; Set mask opposite of expected
478 set_fcc 0xb,1 ; Set mask opposite of expected
479 nfdcmps fr12,fr40,fcc0
480 test_fcc 0x4,0
481 test_fcc 0x4,1
482 test_spr_immed 0,fner1
483 test_spr_immed 0,fner0
484
485 set_fcc 0xb,0 ; Set mask opposite of expected
486 set_fcc 0xb,1 ; Set mask opposite of expected
487 nfdcmps fr12,fr44,fcc0
488 test_fcc 0x4,0
489 test_fcc 0x4,1
490 test_spr_immed 0,fner1
491 test_spr_immed 0,fner0
492
493 set_fcc 0xb,0 ; Set mask opposite of expected
494 set_fcc 0xb,1 ; Set mask opposite of expected
495 nfdcmps fr12,fr48,fcc0
496 test_fcc 0x4,0
497 test_fcc 0x4,1
498 test_spr_immed 0,fner1
499 test_spr_immed 0,fner0
500
501 set_fcc 0xb,0 ; Set mask opposite of expected
502 set_fcc 0xb,1 ; Set mask opposite of expected
503 nfdcmps fr12,fr52,fcc0
504 test_fcc 0x4,0
505 test_fcc 0x4,1
506 test_spr_immed 0,fner1
507 test_spr_immed 0,fner0
508
509 set_fcc 0xe,0 ; Set mask opposite of expected
510 set_fcc 0xe,1 ; Set mask opposite of expected
511 nfdcmps fr12,fr56,fcc0
512 test_fcc 0x1,0
513 test_fcc 0x1,1
514 test_spr_immed 0,fner1
515 test_spr_immed 0,fner0
516
517 set_fcc 0xe,0 ; Set mask opposite of expected
518 set_fcc 0xe,1 ; Set mask opposite of expected
519 nfdcmps fr12,fr60,fcc0
520 test_fcc 0x1,0
521 test_fcc 0x1,1
522 test_spr_immed 0,fner1
523 test_spr_immed 0,fner0
524
525 set_fcc 0xd,0 ; Set mask opposite of expected
526 set_fcc 0xd,1 ; Set mask opposite of expected
527 nfdcmps fr16,fr0,fcc0
528 test_fcc 0x2,0
529 test_fcc 0x2,1
530 test_spr_immed 0,fner1
531 test_spr_immed 0,fner0
532
533 set_fcc 0xd,0 ; Set mask opposite of expected
534 set_fcc 0xd,1 ; Set mask opposite of expected
535 nfdcmps fr16,fr4,fcc0
536 test_fcc 0x2,0
537 test_fcc 0x2,1
538 test_spr_immed 0,fner1
539 test_spr_immed 0,fner0
540
541 set_fcc 0xd,0 ; Set mask opposite of expected
542 set_fcc 0xd,1 ; Set mask opposite of expected
543 nfdcmps fr16,fr8,fcc0
544 test_fcc 0x2,0
545 test_fcc 0x2,1
546 test_spr_immed 0,fner1
547 test_spr_immed 0,fner0
548
549 set_fcc 0xd,0 ; Set mask opposite of expected
550 set_fcc 0xd,1 ; Set mask opposite of expected
551 nfdcmps fr16,fr12,fcc0
552 test_fcc 0x2,0
553 test_fcc 0x2,1
554 test_spr_immed 0,fner1
555 test_spr_immed 0,fner0
556
557 set_fcc 0x7,0 ; Set mask opposite of expected
558 set_fcc 0x7,1 ; Set mask opposite of expected
559 nfdcmps fr16,fr16,fcc0
560 test_fcc 0x8,0
561 test_fcc 0x8,1
562 test_spr_immed 0,fner1
563 test_spr_immed 0,fner0
564
565 set_fcc 0x7,0 ; Set mask opposite of expected
566 set_fcc 0x7,1 ; Set mask opposite of expected
567 nfdcmps fr16,fr20,fcc0
568 test_fcc 0x8,0
569 test_fcc 0x8,1
570 test_spr_immed 0,fner1
571 test_spr_immed 0,fner0
572
573 set_fcc 0xb,0 ; Set mask opposite of expected
574 set_fcc 0xb,1 ; Set mask opposite of expected
575 nfdcmps fr16,fr24,fcc0
576 test_fcc 0x4,0
577 test_fcc 0x4,1
578 test_spr_immed 0,fner1
579 test_spr_immed 0,fner0
580
581 set_fcc 0xb,0 ; Set mask opposite of expected
582 set_fcc 0xb,1 ; Set mask opposite of expected
583 nfdcmps fr16,fr28,fcc0
584 test_fcc 0x4,0
585 test_fcc 0x4,1
586 test_spr_immed 0,fner1
587 test_spr_immed 0,fner0
588
589 set_fcc 0xb,0 ; Set mask opposite of expected
590 set_fcc 0xb,1 ; Set mask opposite of expected
591 nfdcmps fr16,fr32,fcc0
592 test_fcc 0x4,0
593 test_fcc 0x4,1
594 test_spr_immed 0,fner1
595 test_spr_immed 0,fner0
596
597 set_fcc 0xb,0 ; Set mask opposite of expected
598 set_fcc 0xb,1 ; Set mask opposite of expected
599 nfdcmps fr16,fr36,fcc0
600 test_fcc 0x4,0
601 test_fcc 0x4,1
602 test_spr_immed 0,fner1
603 test_spr_immed 0,fner0
604
605 set_fcc 0xb,0 ; Set mask opposite of expected
606 set_fcc 0xb,1 ; Set mask opposite of expected
607 nfdcmps fr16,fr40,fcc0
608 test_fcc 0x4,0
609 test_fcc 0x4,1
610 test_spr_immed 0,fner1
611 test_spr_immed 0,fner0
612
613 set_fcc 0xb,0 ; Set mask opposite of expected
614 set_fcc 0xb,1 ; Set mask opposite of expected
615 nfdcmps fr16,fr44,fcc0
616 test_fcc 0x4,0
617 test_fcc 0x4,1
618 test_spr_immed 0,fner1
619 test_spr_immed 0,fner0
620
621 set_fcc 0xb,0 ; Set mask opposite of expected
622 set_fcc 0xb,1 ; Set mask opposite of expected
623 nfdcmps fr16,fr48,fcc0
624 test_fcc 0x4,0
625 test_fcc 0x4,1
626 test_spr_immed 0,fner1
627 test_spr_immed 0,fner0
628
629 set_fcc 0xb,0 ; Set mask opposite of expected
630 set_fcc 0xb,1 ; Set mask opposite of expected
631 nfdcmps fr16,fr52,fcc0
632 test_fcc 0x4,0
633 test_fcc 0x4,1
634 test_spr_immed 0,fner1
635 test_spr_immed 0,fner0
636
637 set_fcc 0xe,0 ; Set mask opposite of expected
638 set_fcc 0xe,1 ; Set mask opposite of expected
639 nfdcmps fr16,fr56,fcc0
640 test_fcc 0x1,0
641 test_fcc 0x1,1
642 test_spr_immed 0,fner1
643 test_spr_immed 0,fner0
644
645 set_fcc 0xe,0 ; Set mask opposite of expected
646 set_fcc 0xe,1 ; Set mask opposite of expected
647 nfdcmps fr16,fr60,fcc0
648 test_fcc 0x1,0
649 test_fcc 0x1,1
650 test_spr_immed 0,fner1
651 test_spr_immed 0,fner0
652
653 set_fcc 0xd,0 ; Set mask opposite of expected
654 set_fcc 0xd,1 ; Set mask opposite of expected
655 nfdcmps fr20,fr0,fcc0
656 test_fcc 0x2,0
657 test_fcc 0x2,1
658 test_spr_immed 0,fner1
659 test_spr_immed 0,fner0
660
661 set_fcc 0xd,0 ; Set mask opposite of expected
662 set_fcc 0xd,1 ; Set mask opposite of expected
663 nfdcmps fr20,fr4,fcc0
664 test_fcc 0x2,0
665 test_fcc 0x2,1
666 test_spr_immed 0,fner1
667 test_spr_immed 0,fner0
668
669 set_fcc 0xd,0 ; Set mask opposite of expected
670 set_fcc 0xd,1 ; Set mask opposite of expected
671 nfdcmps fr20,fr8,fcc0
672 test_fcc 0x2,0
673 test_fcc 0x2,1
674 test_spr_immed 0,fner1
675 test_spr_immed 0,fner0
676
677 set_fcc 0xd,0 ; Set mask opposite of expected
678 set_fcc 0xd,1 ; Set mask opposite of expected
679 nfdcmps fr20,fr12,fcc0
680 test_fcc 0x2,0
681 test_fcc 0x2,1
682 test_spr_immed 0,fner1
683 test_spr_immed 0,fner0
684
685 set_fcc 0x7,0 ; Set mask opposite of expected
686 set_fcc 0x7,1 ; Set mask opposite of expected
687 nfdcmps fr20,fr16,fcc0
688 test_fcc 0x8,0
689 test_fcc 0x8,1
690 test_spr_immed 0,fner1
691 test_spr_immed 0,fner0
692
693 set_fcc 0x7,0 ; Set mask opposite of expected
694 set_fcc 0x7,1 ; Set mask opposite of expected
695 nfdcmps fr20,fr20,fcc0
696 test_fcc 0x8,0
697 test_fcc 0x8,1
698 test_spr_immed 0,fner1
699 test_spr_immed 0,fner0
700
701 set_fcc 0xb,0 ; Set mask opposite of expected
702 set_fcc 0xb,1 ; Set mask opposite of expected
703 nfdcmps fr20,fr24,fcc0
704 test_fcc 0x4,0
705 test_fcc 0x4,1
706 test_spr_immed 0,fner1
707 test_spr_immed 0,fner0
708
709 set_fcc 0xb,0 ; Set mask opposite of expected
710 set_fcc 0xb,1 ; Set mask opposite of expected
711 nfdcmps fr20,fr28,fcc0
712 test_fcc 0x4,0
713 test_fcc 0x4,1
714 test_spr_immed 0,fner1
715 test_spr_immed 0,fner0
716
717 set_fcc 0xb,0 ; Set mask opposite of expected
718 set_fcc 0xb,1 ; Set mask opposite of expected
719 nfdcmps fr20,fr32,fcc0
720 test_fcc 0x4,0
721 test_fcc 0x4,1
722 test_spr_immed 0,fner1
723 test_spr_immed 0,fner0
724
725 set_fcc 0xb,0 ; Set mask opposite of expected
726 set_fcc 0xb,1 ; Set mask opposite of expected
727 nfdcmps fr20,fr36,fcc0
728 test_fcc 0x4,0
729 test_fcc 0x4,1
730 test_spr_immed 0,fner1
731 test_spr_immed 0,fner0
732
733 set_fcc 0xb,0 ; Set mask opposite of expected
734 set_fcc 0xb,1 ; Set mask opposite of expected
735 nfdcmps fr20,fr40,fcc0
736 test_fcc 0x4,0
737 test_fcc 0x4,1
738 test_spr_immed 0,fner1
739 test_spr_immed 0,fner0
740
741 set_fcc 0xb,0 ; Set mask opposite of expected
742 set_fcc 0xb,1 ; Set mask opposite of expected
743 nfdcmps fr20,fr44,fcc0
744 test_fcc 0x4,0
745 test_fcc 0x4,1
746 test_spr_immed 0,fner1
747 test_spr_immed 0,fner0
748
749 set_fcc 0xb,0 ; Set mask opposite of expected
750 set_fcc 0xb,1 ; Set mask opposite of expected
751 nfdcmps fr20,fr48,fcc0
752 test_fcc 0x4,0
753 test_fcc 0x4,1
754 test_spr_immed 0,fner1
755 test_spr_immed 0,fner0
756
757 set_fcc 0xb,0 ; Set mask opposite of expected
758 set_fcc 0xb,1 ; Set mask opposite of expected
759 nfdcmps fr20,fr52,fcc0
760 test_fcc 0x4,0
761 test_fcc 0x4,1
762 test_spr_immed 0,fner1
763 test_spr_immed 0,fner0
764
765 set_fcc 0xe,0 ; Set mask opposite of expected
766 set_fcc 0xe,1 ; Set mask opposite of expected
767 nfdcmps fr20,fr56,fcc0
768 test_fcc 0x1,0
769 test_fcc 0x1,1
770 test_spr_immed 0,fner1
771 test_spr_immed 0,fner0
772
773 set_fcc 0xe,0 ; Set mask opposite of expected
774 set_fcc 0xe,1 ; Set mask opposite of expected
775 nfdcmps fr20,fr60,fcc0
776 test_fcc 0x1,0
777 test_fcc 0x1,1
778 test_spr_immed 0,fner1
779 test_spr_immed 0,fner0
780
781 set_fcc 0xd,0 ; Set mask opposite of expected
782 set_fcc 0xd,1 ; Set mask opposite of expected
783 nfdcmps fr24,fr0,fcc0
784 test_fcc 0x2,0
785 test_fcc 0x2,1
786 test_spr_immed 0,fner1
787 test_spr_immed 0,fner0
788
789 set_fcc 0xd,0 ; Set mask opposite of expected
790 set_fcc 0xd,1 ; Set mask opposite of expected
791 nfdcmps fr24,fr4,fcc0
792 test_fcc 0x2,0
793 test_fcc 0x2,1
794 test_spr_immed 0,fner1
795 test_spr_immed 0,fner0
796
797 set_fcc 0xd,0 ; Set mask opposite of expected
798 set_fcc 0xd,1 ; Set mask opposite of expected
799 nfdcmps fr24,fr8,fcc0
800 test_fcc 0x2,0
801 test_fcc 0x2,1
802 test_spr_immed 0,fner1
803 test_spr_immed 0,fner0
804
805 set_fcc 0xd,0 ; Set mask opposite of expected
806 set_fcc 0xd,1 ; Set mask opposite of expected
807 nfdcmps fr24,fr12,fcc0
808 test_fcc 0x2,0
809 test_fcc 0x2,1
810 test_spr_immed 0,fner1
811 test_spr_immed 0,fner0
812
813 set_fcc 0xd,0 ; Set mask opposite of expected
814 set_fcc 0xd,1 ; Set mask opposite of expected
815 nfdcmps fr24,fr16,fcc0
816 test_fcc 0x2,0
817 test_fcc 0x2,1
818 test_spr_immed 0,fner1
819 test_spr_immed 0,fner0
820
821 set_fcc 0xd,0 ; Set mask opposite of expected
822 set_fcc 0xd,1 ; Set mask opposite of expected
823 nfdcmps fr24,fr20,fcc0
824 test_fcc 0x2,0
825 test_fcc 0x2,1
826 test_spr_immed 0,fner1
827 test_spr_immed 0,fner0
828
829 set_fcc 0x7,0 ; Set mask opposite of expected
830 set_fcc 0x7,1 ; Set mask opposite of expected
831 nfdcmps fr24,fr24,fcc0
832 test_fcc 0x8,0
833 test_fcc 0x8,1
834 test_spr_immed 0,fner1
835 test_spr_immed 0,fner0
836
837 set_fcc 0xb,0 ; Set mask opposite of expected
838 set_fcc 0xb,1 ; Set mask opposite of expected
839 nfdcmps fr24,fr28,fcc0
840 test_fcc 0x4,0
841 test_fcc 0x4,1
842 test_spr_immed 0,fner1
843 test_spr_immed 0,fner0
844
845 set_fcc 0xb,0 ; Set mask opposite of expected
846 set_fcc 0xb,1 ; Set mask opposite of expected
847 nfdcmps fr24,fr32,fcc0
848 test_fcc 0x4,0
849 test_fcc 0x4,1
850 test_spr_immed 0,fner1
851 test_spr_immed 0,fner0
852
853 set_fcc 0xb,0 ; Set mask opposite of expected
854 set_fcc 0xb,1 ; Set mask opposite of expected
855 nfdcmps fr24,fr36,fcc0
856 test_fcc 0x4,0
857 test_fcc 0x4,1
858 test_spr_immed 0,fner1
859 test_spr_immed 0,fner0
860
861 set_fcc 0xb,0 ; Set mask opposite of expected
862 set_fcc 0xb,1 ; Set mask opposite of expected
863 nfdcmps fr24,fr40,fcc0
864 test_fcc 0x4,0
865 test_fcc 0x4,1
866 test_spr_immed 0,fner1
867 test_spr_immed 0,fner0
868
869 set_fcc 0xb,0 ; Set mask opposite of expected
870 set_fcc 0xb,1 ; Set mask opposite of expected
871 nfdcmps fr24,fr44,fcc0
872 test_fcc 0x4,0
873 test_fcc 0x4,1
874 test_spr_immed 0,fner1
875 test_spr_immed 0,fner0
876
877 set_fcc 0xb,0 ; Set mask opposite of expected
878 set_fcc 0xb,1 ; Set mask opposite of expected
879 nfdcmps fr24,fr48,fcc0
880 test_fcc 0x4,0
881 test_fcc 0x4,1
882 test_spr_immed 0,fner1
883 test_spr_immed 0,fner0
884
885 set_fcc 0xb,0 ; Set mask opposite of expected
886 set_fcc 0xb,1 ; Set mask opposite of expected
887 nfdcmps fr24,fr52,fcc0
888 test_fcc 0x4,0
889 test_fcc 0x4,1
890 test_spr_immed 0,fner1
891 test_spr_immed 0,fner0
892
893 set_fcc 0xe,0 ; Set mask opposite of expected
894 set_fcc 0xe,1 ; Set mask opposite of expected
895 nfdcmps fr24,fr56,fcc0
896 test_fcc 0x1,0
897 test_fcc 0x1,1
898 test_spr_immed 0,fner1
899 test_spr_immed 0,fner0
900
901 set_fcc 0xe,0 ; Set mask opposite of expected
902 set_fcc 0xe,1 ; Set mask opposite of expected
903 nfdcmps fr24,fr60,fcc0
904 test_fcc 0x1,0
905 test_fcc 0x1,1
906 test_spr_immed 0,fner1
907 test_spr_immed 0,fner0
908
909 set_fcc 0xd,0 ; Set mask opposite of expected
910 set_fcc 0xd,1 ; Set mask opposite of expected
911 nfdcmps fr28,fr0,fcc0
912 test_fcc 0x2,0
913 test_fcc 0x2,1
914 test_spr_immed 0,fner1
915 test_spr_immed 0,fner0
916
917 set_fcc 0xd,0 ; Set mask opposite of expected
918 set_fcc 0xd,1 ; Set mask opposite of expected
919 nfdcmps fr28,fr4,fcc0
920 test_fcc 0x2,0
921 test_fcc 0x2,1
922 test_spr_immed 0,fner1
923 test_spr_immed 0,fner0
924
925 set_fcc 0xd,0 ; Set mask opposite of expected
926 set_fcc 0xd,1 ; Set mask opposite of expected
927 nfdcmps fr28,fr8,fcc0
928 test_fcc 0x2,0
929 test_fcc 0x2,1
930 test_spr_immed 0,fner1
931 test_spr_immed 0,fner0
932
933 set_fcc 0xd,0 ; Set mask opposite of expected
934 set_fcc 0xd,1 ; Set mask opposite of expected
935 nfdcmps fr28,fr12,fcc0
936 test_fcc 0x2,0
937 test_fcc 0x2,1
938 test_spr_immed 0,fner1
939 test_spr_immed 0,fner0
940
941 set_fcc 0xd,0 ; Set mask opposite of expected
942 set_fcc 0xd,1 ; Set mask opposite of expected
943 nfdcmps fr28,fr16,fcc0
944 test_fcc 0x2,0
945 test_fcc 0x2,1
946 test_spr_immed 0,fner1
947 test_spr_immed 0,fner0
948
949 set_fcc 0xd,0 ; Set mask opposite of expected
950 set_fcc 0xd,1 ; Set mask opposite of expected
951 nfdcmps fr28,fr20,fcc0
952 test_fcc 0x2,0
953 test_fcc 0x2,1
954 test_spr_immed 0,fner1
955 test_spr_immed 0,fner0
956
957 set_fcc 0xd,0 ; Set mask opposite of expected
958 set_fcc 0xd,1 ; Set mask opposite of expected
959 nfdcmps fr28,fr24,fcc0
960 test_fcc 0x2,0
961 test_fcc 0x2,1
962 test_spr_immed 0,fner1
963 test_spr_immed 0,fner0
964
965 set_fcc 0x7,0 ; Set mask opposite of expected
966 set_fcc 0x7,1 ; Set mask opposite of expected
967 nfdcmps fr28,fr28,fcc0
968 test_fcc 0x8,0
969 test_fcc 0x8,1
970 test_spr_immed 0,fner1
971 test_spr_immed 0,fner0
972
973 set_fcc 0xb,0 ; Set mask opposite of expected
974 set_fcc 0xb,1 ; Set mask opposite of expected
975 nfdcmps fr28,fr32,fcc0
976 test_fcc 0x4,0
977 test_fcc 0x4,1
978 test_spr_immed 0,fner1
979 test_spr_immed 0,fner0
980
981 set_fcc 0xb,0 ; Set mask opposite of expected
982 set_fcc 0xb,1 ; Set mask opposite of expected
983 nfdcmps fr28,fr36,fcc0
984 test_fcc 0x4,0
985 test_fcc 0x4,1
986 test_spr_immed 0,fner1
987 test_spr_immed 0,fner0
988
989 set_fcc 0xb,0 ; Set mask opposite of expected
990 set_fcc 0xb,1 ; Set mask opposite of expected
991 nfdcmps fr28,fr40,fcc0
992 test_fcc 0x4,0
993 test_fcc 0x4,1
994 test_spr_immed 0,fner1
995 test_spr_immed 0,fner0
996
997 set_fcc 0xb,0 ; Set mask opposite of expected
998 set_fcc 0xb,1 ; Set mask opposite of expected
999 nfdcmps fr28,fr44,fcc0
1000 test_fcc 0x4,0
1001 test_fcc 0x4,1
1002 test_spr_immed 0,fner1
1003 test_spr_immed 0,fner0
1004
1005 set_fcc 0xb,0 ; Set mask opposite of expected
1006 set_fcc 0xb,1 ; Set mask opposite of expected
1007 nfdcmps fr28,fr48,fcc0
1008 test_fcc 0x4,0
1009 test_fcc 0x4,1
1010 test_spr_immed 0,fner1
1011 test_spr_immed 0,fner0
1012
1013 set_fcc 0xb,0 ; Set mask opposite of expected
1014 set_fcc 0xb,1 ; Set mask opposite of expected
1015 nfdcmps fr28,fr52,fcc0
1016 test_fcc 0x4,0
1017 test_fcc 0x4,1
1018 test_spr_immed 0,fner1
1019 test_spr_immed 0,fner0
1020
1021 set_fcc 0xe,0 ; Set mask opposite of expected
1022 set_fcc 0xe,1 ; Set mask opposite of expected
1023 nfdcmps fr28,fr56,fcc0
1024 test_fcc 0x1,0
1025 test_fcc 0x1,1
1026 test_spr_immed 0,fner1
1027 test_spr_immed 0,fner0
1028
1029 set_fcc 0xe,0 ; Set mask opposite of expected
1030 set_fcc 0xe,1 ; Set mask opposite of expected
1031 nfdcmps fr28,fr60,fcc0
1032 test_fcc 0x1,0
1033 test_fcc 0x1,1
1034 test_spr_immed 0,fner1
1035 test_spr_immed 0,fner0
1036
1037 set_fcc 0xd,0 ; Set mask opposite of expected
1038 set_fcc 0xd,1 ; Set mask opposite of expected
1039 nfdcmps fr48,fr0,fcc0
1040 test_fcc 0x2,0
1041 test_fcc 0x2,1
1042 test_spr_immed 0,fner1
1043 test_spr_immed 0,fner0
1044
1045 set_fcc 0xd,0 ; Set mask opposite of expected
1046 set_fcc 0xd,1 ; Set mask opposite of expected
1047 nfdcmps fr48,fr4,fcc0
1048 test_fcc 0x2,0
1049 test_fcc 0x2,1
1050 test_spr_immed 0,fner1
1051 test_spr_immed 0,fner0
1052
1053 set_fcc 0xd,0 ; Set mask opposite of expected
1054 set_fcc 0xd,1 ; Set mask opposite of expected
1055 nfdcmps fr48,fr8,fcc0
1056 test_fcc 0x2,0
1057 test_fcc 0x2,1
1058 test_spr_immed 0,fner1
1059 test_spr_immed 0,fner0
1060
1061 set_fcc 0xd,0 ; Set mask opposite of expected
1062 set_fcc 0xd,1 ; Set mask opposite of expected
1063 nfdcmps fr48,fr12,fcc0
1064 test_fcc 0x2,0
1065 test_fcc 0x2,1
1066 test_spr_immed 0,fner1
1067 test_spr_immed 0,fner0
1068
1069 set_fcc 0xd,0 ; Set mask opposite of expected
1070 set_fcc 0xd,1 ; Set mask opposite of expected
1071 nfdcmps fr48,fr16,fcc0
1072 test_fcc 0x2,0
1073 test_fcc 0x2,1
1074 test_spr_immed 0,fner1
1075 test_spr_immed 0,fner0
1076
1077 set_fcc 0xd,0 ; Set mask opposite of expected
1078 set_fcc 0xd,1 ; Set mask opposite of expected
1079 nfdcmps fr48,fr20,fcc0
1080 test_fcc 0x2,0
1081 test_fcc 0x2,1
1082 test_spr_immed 0,fner1
1083 test_spr_immed 0,fner0
1084
1085 set_fcc 0xd,0 ; Set mask opposite of expected
1086 set_fcc 0xd,1 ; Set mask opposite of expected
1087 nfdcmps fr48,fr24,fcc0
1088 test_fcc 0x2,0
1089 test_fcc 0x2,1
1090 test_spr_immed 0,fner1
1091 test_spr_immed 0,fner0
1092
1093 set_fcc 0xd,0 ; Set mask opposite of expected
1094 set_fcc 0xd,1 ; Set mask opposite of expected
1095 nfdcmps fr48,fr28,fcc0
1096 test_fcc 0x2,0
1097 test_fcc 0x2,1
1098 test_spr_immed 0,fner1
1099 test_spr_immed 0,fner0
1100
1101 set_fcc 0xd,0 ; Set mask opposite of expected
1102 set_fcc 0xd,1 ; Set mask opposite of expected
1103 nfdcmps fr48,fr32,fcc0
1104 test_fcc 0x2,0
1105 test_fcc 0x2,1
1106 test_spr_immed 0,fner1
1107 test_spr_immed 0,fner0
1108
1109 set_fcc 0xd,0 ; Set mask opposite of expected
1110 set_fcc 0xd,1 ; Set mask opposite of expected
1111 nfdcmps fr48,fr36,fcc0
1112 test_fcc 0x2,0
1113 test_fcc 0x2,1
1114 test_spr_immed 0,fner1
1115 test_spr_immed 0,fner0
1116
1117 set_fcc 0xd,0 ; Set mask opposite of expected
1118 set_fcc 0xd,1 ; Set mask opposite of expected
1119 nfdcmps fr48,fr40,fcc0
1120 test_fcc 0x2,0
1121 test_fcc 0x2,1
1122 test_spr_immed 0,fner1
1123 test_spr_immed 0,fner0
1124
1125 set_fcc 0xd,0 ; Set mask opposite of expected
1126 set_fcc 0xd,1 ; Set mask opposite of expected
1127 nfdcmps fr48,fr44,fcc0
1128 test_fcc 0x2,0
1129 test_fcc 0x2,1
1130 test_spr_immed 0,fner1
1131 test_spr_immed 0,fner0
1132
1133 set_fcc 0x7,0 ; Set mask opposite of expected
1134 set_fcc 0x7,1 ; Set mask opposite of expected
1135 nfdcmps fr48,fr48,fcc0
1136 test_fcc 0x8,0
1137 test_fcc 0x8,1
1138 test_spr_immed 0,fner1
1139 test_spr_immed 0,fner0
1140
1141 set_fcc 0xb,0 ; Set mask opposite of expected
1142 set_fcc 0xb,1 ; Set mask opposite of expected
1143 nfdcmps fr48,fr52,fcc0
1144 test_fcc 0x4,0
1145 test_fcc 0x4,1
1146 test_spr_immed 0,fner1
1147 test_spr_immed 0,fner0
1148
1149 set_fcc 0xe,0 ; Set mask opposite of expected
1150 set_fcc 0xe,1 ; Set mask opposite of expected
1151 nfdcmps fr48,fr56,fcc0
1152 test_fcc 0x1,0
1153 test_fcc 0x1,1
1154 test_spr_immed 0,fner1
1155 test_spr_immed 0,fner0
1156
1157 set_fcc 0xe,0 ; Set mask opposite of expected
1158 set_fcc 0xe,1 ; Set mask opposite of expected
1159 nfdcmps fr48,fr60,fcc0
1160 test_fcc 0x1,0
1161 test_fcc 0x1,1
1162 test_spr_immed 0,fner1
1163 test_spr_immed 0,fner0
1164
1165 set_fcc 0xd,0 ; Set mask opposite of expected
1166 set_fcc 0xd,1 ; Set mask opposite of expected
1167 nfdcmps fr52,fr0,fcc0
1168 test_fcc 0x2,0
1169 test_fcc 0x2,1
1170 test_spr_immed 0,fner1
1171 test_spr_immed 0,fner0
1172
1173 set_fcc 0xd,0 ; Set mask opposite of expected
1174 set_fcc 0xd,1 ; Set mask opposite of expected
1175 nfdcmps fr52,fr4,fcc0
1176 test_fcc 0x2,0
1177 test_fcc 0x2,1
1178 test_spr_immed 0,fner1
1179 test_spr_immed 0,fner0
1180
1181 set_fcc 0xd,0 ; Set mask opposite of expected
1182 set_fcc 0xd,1 ; Set mask opposite of expected
1183 nfdcmps fr52,fr8,fcc0
1184 test_fcc 0x2,0
1185 test_fcc 0x2,1
1186 test_spr_immed 0,fner1
1187 test_spr_immed 0,fner0
1188
1189 set_fcc 0xd,0 ; Set mask opposite of expected
1190 set_fcc 0xd,1 ; Set mask opposite of expected
1191 nfdcmps fr52,fr12,fcc0
1192 test_fcc 0x2,0
1193 test_fcc 0x2,1
1194 test_spr_immed 0,fner1
1195 test_spr_immed 0,fner0
1196
1197 set_fcc 0xd,0 ; Set mask opposite of expected
1198 set_fcc 0xd,1 ; Set mask opposite of expected
1199 nfdcmps fr52,fr16,fcc0
1200 test_fcc 0x2,0
1201 test_fcc 0x2,1
1202 test_spr_immed 0,fner1
1203 test_spr_immed 0,fner0
1204
1205 set_fcc 0xd,0 ; Set mask opposite of expected
1206 set_fcc 0xd,1 ; Set mask opposite of expected
1207 nfdcmps fr52,fr20,fcc0
1208 test_fcc 0x2,0
1209 test_fcc 0x2,1
1210 test_spr_immed 0,fner1
1211 test_spr_immed 0,fner0
1212
1213 set_fcc 0xd,0 ; Set mask opposite of expected
1214 set_fcc 0xd,1 ; Set mask opposite of expected
1215 nfdcmps fr52,fr24,fcc0
1216 test_fcc 0x2,0
1217 test_fcc 0x2,1
1218 test_spr_immed 0,fner1
1219 test_spr_immed 0,fner0
1220
1221 set_fcc 0xd,0 ; Set mask opposite of expected
1222 set_fcc 0xd,1 ; Set mask opposite of expected
1223 nfdcmps fr52,fr28,fcc0
1224 test_fcc 0x2,0
1225 test_fcc 0x2,1
1226 test_spr_immed 0,fner1
1227 test_spr_immed 0,fner0
1228
1229 set_fcc 0xd,0 ; Set mask opposite of expected
1230 set_fcc 0xd,1 ; Set mask opposite of expected
1231 nfdcmps fr52,fr32,fcc0
1232 test_fcc 0x2,0
1233 test_fcc 0x2,1
1234 test_spr_immed 0,fner1
1235 test_spr_immed 0,fner0
1236
1237 set_fcc 0xd,0 ; Set mask opposite of expected
1238 set_fcc 0xd,1 ; Set mask opposite of expected
1239 nfdcmps fr52,fr36,fcc0
1240 test_fcc 0x2,0
1241 test_fcc 0x2,1
1242 test_spr_immed 0,fner1
1243 test_spr_immed 0,fner0
1244
1245 set_fcc 0xd,0 ; Set mask opposite of expected
1246 set_fcc 0xd,1 ; Set mask opposite of expected
1247 nfdcmps fr52,fr40,fcc0
1248 test_fcc 0x2,0
1249 test_fcc 0x2,1
1250 test_spr_immed 0,fner1
1251 test_spr_immed 0,fner0
1252
1253 set_fcc 0xd,0 ; Set mask opposite of expected
1254 set_fcc 0xd,1 ; Set mask opposite of expected
1255 nfdcmps fr52,fr44,fcc0
1256 test_fcc 0x2,0
1257 test_fcc 0x2,1
1258 test_spr_immed 0,fner1
1259 test_spr_immed 0,fner0
1260
1261 set_fcc 0xd,0 ; Set mask opposite of expected
1262 set_fcc 0xd,1 ; Set mask opposite of expected
1263 nfdcmps fr52,fr48,fcc0
1264 test_fcc 0x2,0
1265 test_fcc 0x2,1
1266 test_spr_immed 0,fner1
1267 test_spr_immed 0,fner0
1268
1269 set_fcc 0x7,0 ; Set mask opposite of expected
1270 set_fcc 0x7,1 ; Set mask opposite of expected
1271 nfdcmps fr52,fr52,fcc0
1272 test_fcc 0x8,0
1273 test_fcc 0x8,1
1274 test_spr_immed 0,fner1
1275 test_spr_immed 0,fner0
1276
1277 set_fcc 0xe,0 ; Set mask opposite of expected
1278 set_fcc 0xe,1 ; Set mask opposite of expected
1279 nfdcmps fr52,fr56,fcc0
1280 test_fcc 0x1,0
1281 test_fcc 0x1,1
1282 test_spr_immed 0,fner1
1283 test_spr_immed 0,fner0
1284
1285 set_fcc 0xe,0 ; Set mask opposite of expected
1286 set_fcc 0xe,1 ; Set mask opposite of expected
1287 nfdcmps fr52,fr60,fcc0
1288 test_fcc 0x1,0
1289 test_fcc 0x1,1
1290 test_spr_immed 0,fner1
1291 test_spr_immed 0,fner0
1292
1293 set_fcc 0xe,0 ; Set mask opposite of expected
1294 set_fcc 0xe,1 ; Set mask opposite of expected
1295 nfdcmps fr56,fr0,fcc0
1296 test_fcc 0x1,0
1297 test_fcc 0x1,1
1298 test_spr_immed 0,fner1
1299 test_spr_immed 0,fner0
1300
1301 set_fcc 0xe,0 ; Set mask opposite of expected
1302 set_fcc 0xe,1 ; Set mask opposite of expected
1303 nfdcmps fr56,fr4,fcc0
1304 test_fcc 0x1,0
1305 test_fcc 0x1,1
1306 test_spr_immed 0,fner1
1307 test_spr_immed 0,fner0
1308
1309 set_fcc 0xe,0 ; Set mask opposite of expected
1310 set_fcc 0xe,1 ; Set mask opposite of expected
1311 nfdcmps fr56,fr8,fcc0
1312 test_fcc 0x1,0
1313 test_fcc 0x1,1
1314 test_spr_immed 0,fner1
1315 test_spr_immed 0,fner0
1316
1317 set_fcc 0xe,0 ; Set mask opposite of expected
1318 set_fcc 0xe,1 ; Set mask opposite of expected
1319 nfdcmps fr56,fr12,fcc0
1320 test_fcc 0x1,0
1321 test_fcc 0x1,1
1322 test_spr_immed 0,fner1
1323 test_spr_immed 0,fner0
1324
1325 set_fcc 0xe,0 ; Set mask opposite of expected
1326 set_fcc 0xe,1 ; Set mask opposite of expected
1327 nfdcmps fr56,fr16,fcc0
1328 test_fcc 0x1,0
1329 test_fcc 0x1,1
1330 test_spr_immed 0,fner1
1331 test_spr_immed 0,fner0
1332
1333 set_fcc 0xe,0 ; Set mask opposite of expected
1334 set_fcc 0xe,1 ; Set mask opposite of expected
1335 nfdcmps fr56,fr20,fcc0
1336 test_fcc 0x1,0
1337 test_fcc 0x1,1
1338 test_spr_immed 0,fner1
1339 test_spr_immed 0,fner0
1340
1341 set_fcc 0xe,0 ; Set mask opposite of expected
1342 set_fcc 0xe,1 ; Set mask opposite of expected
1343 nfdcmps fr56,fr24,fcc0
1344 test_fcc 0x1,0
1345 test_fcc 0x1,1
1346 test_spr_immed 0,fner1
1347 test_spr_immed 0,fner0
1348
1349 set_fcc 0xe,0 ; Set mask opposite of expected
1350 set_fcc 0xe,1 ; Set mask opposite of expected
1351 nfdcmps fr56,fr28,fcc0
1352 test_fcc 0x1,0
1353 test_fcc 0x1,1
1354 test_spr_immed 0,fner1
1355 test_spr_immed 0,fner0
1356
1357 set_fcc 0xe,0 ; Set mask opposite of expected
1358 set_fcc 0xe,1 ; Set mask opposite of expected
1359 nfdcmps fr56,fr32,fcc0
1360 test_fcc 0x1,0
1361 test_fcc 0x1,1
1362 test_spr_immed 0,fner1
1363 test_spr_immed 0,fner0
1364
1365 set_fcc 0xe,0 ; Set mask opposite of expected
1366 set_fcc 0xe,1 ; Set mask opposite of expected
1367 nfdcmps fr56,fr36,fcc0
1368 test_fcc 0x1,0
1369 test_fcc 0x1,1
1370 test_spr_immed 0,fner1
1371 test_spr_immed 0,fner0
1372
1373 set_fcc 0xe,0 ; Set mask opposite of expected
1374 set_fcc 0xe,1 ; Set mask opposite of expected
1375 nfdcmps fr56,fr40,fcc0
1376 test_fcc 0x1,0
1377 test_fcc 0x1,1
1378 test_spr_immed 0,fner1
1379 test_spr_immed 0,fner0
1380
1381 set_fcc 0xe,0 ; Set mask opposite of expected
1382 set_fcc 0xe,1 ; Set mask opposite of expected
1383 nfdcmps fr56,fr44,fcc0
1384 test_fcc 0x1,0
1385 test_fcc 0x1,1
1386 test_spr_immed 0,fner1
1387 test_spr_immed 0,fner0
1388
1389 set_fcc 0xe,0 ; Set mask opposite of expected
1390 set_fcc 0xe,1 ; Set mask opposite of expected
1391 nfdcmps fr56,fr48,fcc0
1392 test_fcc 0x1,0
1393 test_fcc 0x1,1
1394 test_spr_immed 0,fner1
1395 test_spr_immed 0,fner0
1396
1397 set_fcc 0xe,0 ; Set mask opposite of expected
1398 set_fcc 0xe,1 ; Set mask opposite of expected
1399 nfdcmps fr56,fr52,fcc0
1400 test_fcc 0x1,0
1401 test_fcc 0x1,1
1402 test_spr_immed 0,fner1
1403 test_spr_immed 0,fner0
1404
1405 set_fcc 0xe,0 ; Set mask opposite of expected
1406 set_fcc 0xe,1 ; Set mask opposite of expected
1407 nfdcmps fr56,fr56,fcc0
1408 test_fcc 0x1,0
1409 test_fcc 0x1,1
1410 test_spr_immed 0,fner1
1411 test_spr_immed 0,fner0
1412
1413 set_fcc 0xe,0 ; Set mask opposite of expected
1414 set_fcc 0xe,1 ; Set mask opposite of expected
1415 nfdcmps fr56,fr60,fcc0
1416 test_fcc 0x1,0
1417 test_fcc 0x1,1
1418 test_spr_immed 0,fner1
1419 test_spr_immed 0,fner0
1420
1421 set_fcc 0xe,0 ; Set mask opposite of expected
1422 set_fcc 0xe,1 ; Set mask opposite of expected
1423 nfdcmps fr60,fr0,fcc0
1424 test_fcc 0x1,0
1425 test_fcc 0x1,1
1426 test_spr_immed 0,fner1
1427 test_spr_immed 0,fner0
1428
1429 set_fcc 0xe,0 ; Set mask opposite of expected
1430 set_fcc 0xe,1 ; Set mask opposite of expected
1431 nfdcmps fr60,fr4,fcc0
1432 test_fcc 0x1,0
1433 test_fcc 0x1,1
1434 test_spr_immed 0,fner1
1435 test_spr_immed 0,fner0
1436
1437 set_fcc 0xe,0 ; Set mask opposite of expected
1438 set_fcc 0xe,1 ; Set mask opposite of expected
1439 nfdcmps fr60,fr8,fcc0
1440 test_fcc 0x1,0
1441 test_fcc 0x1,1
1442 test_spr_immed 0,fner1
1443 test_spr_immed 0,fner0
1444
1445 set_fcc 0xe,0 ; Set mask opposite of expected
1446 set_fcc 0xe,1 ; Set mask opposite of expected
1447 nfdcmps fr60,fr12,fcc0
1448 test_fcc 0x1,0
1449 test_fcc 0x1,1
1450 test_spr_immed 0,fner1
1451 test_spr_immed 0,fner0
1452
1453 set_fcc 0xe,0 ; Set mask opposite of expected
1454 set_fcc 0xe,1 ; Set mask opposite of expected
1455 nfdcmps fr60,fr16,fcc0
1456 test_fcc 0x1,0
1457 test_fcc 0x1,1
1458 test_spr_immed 0,fner1
1459 test_spr_immed 0,fner0
1460
1461 set_fcc 0xe,0 ; Set mask opposite of expected
1462 set_fcc 0xe,1 ; Set mask opposite of expected
1463 nfdcmps fr60,fr20,fcc0
1464 test_fcc 0x1,0
1465 test_fcc 0x1,1
1466 test_spr_immed 0,fner1
1467 test_spr_immed 0,fner0
1468
1469 set_fcc 0xe,0 ; Set mask opposite of expected
1470 set_fcc 0xe,1 ; Set mask opposite of expected
1471 nfdcmps fr60,fr24,fcc0
1472 test_fcc 0x1,0
1473 test_fcc 0x1,1
1474 test_spr_immed 0,fner1
1475 test_spr_immed 0,fner0
1476
1477 set_fcc 0xe,0 ; Set mask opposite of expected
1478 set_fcc 0xe,1 ; Set mask opposite of expected
1479 nfdcmps fr60,fr28,fcc0
1480 test_fcc 0x1,0
1481 test_fcc 0x1,1
1482 test_spr_immed 0,fner1
1483 test_spr_immed 0,fner0
1484
1485 set_fcc 0xe,0 ; Set mask opposite of expected
1486 set_fcc 0xe,1 ; Set mask opposite of expected
1487 nfdcmps fr60,fr32,fcc0
1488 test_fcc 0x1,0
1489 test_fcc 0x1,1
1490 test_spr_immed 0,fner1
1491 test_spr_immed 0,fner0
1492
1493 set_fcc 0xe,0 ; Set mask opposite of expected
1494 set_fcc 0xe,1 ; Set mask opposite of expected
1495 nfdcmps fr60,fr36,fcc0
1496 test_fcc 0x1,0
1497 test_fcc 0x1,1
1498 test_spr_immed 0,fner1
1499 test_spr_immed 0,fner0
1500
1501 set_fcc 0xe,0 ; Set mask opposite of expected
1502 set_fcc 0xe,1 ; Set mask opposite of expected
1503 nfdcmps fr60,fr40,fcc0
1504 test_fcc 0x1,0
1505 test_fcc 0x1,1
1506 test_spr_immed 0,fner1
1507 test_spr_immed 0,fner0
1508
1509 set_fcc 0xe,0 ; Set mask opposite of expected
1510 set_fcc 0xe,1 ; Set mask opposite of expected
1511 nfdcmps fr60,fr44,fcc0
1512 test_fcc 0x1,0
1513 test_fcc 0x1,1
1514 test_spr_immed 0,fner1
1515 test_spr_immed 0,fner0
1516
1517 set_fcc 0xe,0 ; Set mask opposite of expected
1518 set_fcc 0xe,1 ; Set mask opposite of expected
1519 nfdcmps fr60,fr48,fcc0
1520 test_fcc 0x1,0
1521 test_fcc 0x1,1
1522 test_spr_immed 0,fner1
1523 test_spr_immed 0,fner0
1524
1525 set_fcc 0xe,0 ; Set mask opposite of expected
1526 set_fcc 0xe,1 ; Set mask opposite of expected
1527 nfdcmps fr60,fr52,fcc0
1528 test_fcc 0x1,0
1529 test_fcc 0x1,1
1530 test_spr_immed 0,fner1
1531 test_spr_immed 0,fner0
1532
1533 set_fcc 0xe,0 ; Set mask opposite of expected
1534 set_fcc 0xe,1 ; Set mask opposite of expected
1535 nfdcmps fr60,fr56,fcc0
1536 test_fcc 0x1,0
1537 test_fcc 0x1,1
1538 test_spr_immed 0,fner1
1539 test_spr_immed 0,fner0
1540
1541 set_fcc 0xe,0 ; Set mask opposite of expected
1542 set_fcc 0xe,1 ; Set mask opposite of expected
1543 nfdcmps fr60,fr60,fcc0
1544 test_fcc 0x1,0
1545 test_fcc 0x1,1
1546 test_spr_immed 0,fner1
1547 test_spr_immed 0,fner0
1548
1549 pass
GDB Binutils - Deliverables
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