sim/testsuite/sim/frv/sdiv.cgs

   1 # frv testcase for sdiv $GRi,$GRj,$GRk
   2 # mach: all
   3
   4         .include "testutils.inc"
   5
   6         start
   7
   8         .global sdiv
   9 sdiv:
  10         ; simple division 12 / 3
  11         set_gr_immed    3,gr3
  12         set_gr_immed    12,gr1
  13         sdiv            gr1,gr3,gr2
  14         test_gr_immed   4,gr2
  15
  16         ; Random example
  17         set_gr_limmed   0x0123,0x4567,gr3
  18         set_gr_limmed   0xfedc,0xba98,gr1
  19         sdiv            gr1,gr3,gr2
  20         test_gr_immed   -1,gr2
  21
  22         ; Special case from the Arch Spec Vol 2
  23         or_spr_immed    0x20,isr        ; turn on isr.edem
  24         set_gr_immed    -1,gr3
  25         set_gr_limmed   0x8000,0x0000,gr1
  26         sdiv            gr1,gr3,gr2
  27         test_gr_limmed  0x7fff,0xffff,gr2
  28         test_spr_bits   0x4,2,1,isr     ; isr.aexc is set
  29
  30         and_spr_immed   -33,isr         ; turn off isr.edem
  31         ; set up exception handler
  32         set_psr_et      1
  33         and_spr_immed   -4081,tbr       ; clear tbr.tt
  34         set_gr_spr      tbr,gr17
  35         inc_gr_immed    0x170,gr17      ; address of exception handler
  36         set_bctrlr_0_0  gr17
  37         set_spr_immed   128,lcr
  38         set_gr_immed    0,gr15
  39
  40         ; divide will cause overflow
  41         set_spr_addr    ok1,lr
  42         set_gr_addr     e1,gr17
  43         set_gr_immed    -1,gr3
  44         set_gr_limmed   0x8000,0x0000,gr1
  45 e1:     sdiv            gr1,gr3,gr2     ; overflow
  46         test_gr_immed   1,gr15
  47         test_gr_limmed  0x8000,0x0000,gr2; gr2 updated
  48
  49         ; divide by zero
  50         set_spr_addr    ok2,lr
  51         set_gr_addr     e2,gr17
  52         set_gr_immed    0xdeadbeef,gr2
  53 e2:     sdiv            gr1,gr0,gr2     ; divide by zero
  54         test_gr_immed   2,gr15          ; handler called
  55         test_gr_immed   0xdeadbeef,gr2  ; gr2 not updated.
  56
  57         pass
  58
  59 ok1:    ; exception handler for overflow
  60         test_spr_bits   0x18,3,0x2,isr          ; isr.dtt is set
  61         test_spr_gr     epcr0,gr17              ; return address set
  62         test_spr_bits   0x0001,0,0x1,esr0       ; esr0 is valid
  63         test_spr_bits   0x003e,1,0x13,esr0      ; esr0.ec is set
  64         inc_gr_immed    1,gr15
  65         rett            0
  66         fail
  67
  68 ok2:    ; exception handler for divide by zero
  69         test_spr_bits   0x18,3,0x3,isr          ; isr.dtt is set
  70         test_spr_gr     epcr0,gr17              ; return address set
  71         test_spr_bits   0x0001,0,0x1,esr0       ; esr0 is valid
  72         test_spr_bits   0x003e,1,0x13,esr0      ; esr0.ec is set
  73         inc_gr_immed    1,gr15
  74         rett            0
  75         fail