sim/testsuite/sim/frv/sdivi.cgs

   1 # frv testcase for sdivi $GRi,$s12,$GRk
   2 # mach: all
   3
   4         .include "testutils.inc"
   5
   6         start
   7
   8         .global sdivi
   9 sdivi:
  10         ; simple division 12 / 3
  11         set_gr_immed    12,gr1
  12         sdivi           gr1,3,gr2
  13         test_gr_immed   4,gr2
  14
  15         ; Random example
  16         set_gr_limmed   0xfedc,0xba98,gr1
  17         sdivi           gr1,0x7ff,gr2
  18         test_gr_limmed  0xffff,0xdb93,gr2
  19
  20         ; Random negative example
  21         set_gr_limmed   0xfedc,0xba98,gr1
  22         sdivi           gr1,-2048,gr2
  23         test_gr_immed   0x2468,gr2
  24
  25         ; Special case from the Arch Spec Vol 2
  26         or_spr_immed    0x20,isr        ; turn on isr.edem
  27         set_gr_limmed   0x8000,0x0000,gr1
  28         sdivi           gr1,-1,gr2
  29         test_gr_limmed  0x7fff,0xffff,gr2
  30         test_spr_bits   0x4,2,1,isr     ; isr.aexc is set
  31
  32         and_spr_immed   -33,isr         ; turn off isr.edem
  33         ; set up exception handler
  34         set_psr_et      1
  35         and_spr_immed   -4081,tbr       ; clear tbr.tt
  36         set_gr_spr      tbr,gr17
  37         inc_gr_immed    0x170,gr17      ; address of exception handler
  38         set_bctrlr_0_0  gr17
  39         set_spr_immed   128,lcr
  40         set_gr_immed    0,gr15
  41
  42         ; divide will cause overflow
  43         set_spr_addr    ok1,lr
  44         set_gr_addr     e1,gr17
  45         set_gr_limmed   0x8000,0x0000,gr1
  46 e1:     sdivi           gr1,-1,gr2
  47         test_gr_immed   1,gr15
  48         test_gr_limmed  0x8000,0x0000,gr2
  49
  50         ; divide by zero
  51         set_spr_addr    ok2,lr
  52         set_gr_addr     e2,gr17
  53 e2:     sdivi           gr1,0,gr2       ; divide by zero
  54         test_gr_immed   2,gr15
  55
  56         pass
  57
  58 ok1:    ; exception handler for overflow
  59         test_spr_bits   0x18,3,0x2,isr          ; isr.dtt is set
  60         test_spr_gr     epcr0,gr17              ; return address set
  61         test_spr_bits   0x0001,0,0x1,esr0       ; esr0 is valid
  62         test_spr_bits   0x003e,1,0x13,esr0      ; esr0.ec is set
  63         inc_gr_immed    1,gr15
  64         rett            0
  65         fail
  66
  67 ok2:    ; exception handler for divide by zero
  68         test_spr_bits   0x18,3,0x3,isr          ; isr.dtt is set
  69         test_spr_gr     epcr0,gr17              ; return address set
  70         test_spr_bits   0x0001,0,0x1,esr0       ; esr0 is valid
  71         test_spr_bits   0x003e,1,0x13,esr0      ; esr0.ec is set
  72         inc_gr_immed    1,gr15
  73         rett            0
  74         fail