sim/testsuite/sim/frv/tge.cgs

   1 # frv testcase for tge $ICCi_2,$GRi,$GRj
   2 # mach: all
   3
   4         .include "testutils.inc"
   5
   6         start
   7
   8         .global tge
   9 tge:
  10         and_spr_immed   -4081,tbr               ; clear tbr.tt
  11         set_gr_spr      tbr,gr7
  12         inc_gr_immed    2112,gr7                ; address of exception handler
  13         set_bctrlr_0_0  gr7     ; bctrlr 0,0
  14
  15         set_spr_immed   128,lcr
  16         set_gr_immed    0,gr7
  17         set_gr_immed    4,gr8
  18
  19         set_psr_et      1
  20         set_spr_addr    ok0,lr
  21         set_icc         0x0 0
  22         tge             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  23         fail
  24 ok0:
  25         set_psr_et      1
  26         set_spr_addr    ok1,lr
  27         set_icc         0x1 0
  28         tge             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  29         fail
  30 ok1:
  31         set_spr_addr    bad,lr
  32         set_icc         0x2 0
  33         tge             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  34
  35         set_spr_addr    bad,lr
  36         set_icc         0x3 0
  37         tge             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  38
  39         set_psr_et      1
  40         set_spr_addr    ok4,lr
  41         set_icc         0x4 0
  42         tge             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  43         fail
  44 ok4:
  45         set_psr_et      1
  46         set_spr_addr    ok5,lr
  47         set_icc         0x5 0
  48         tge             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  49         fail
  50 ok5:
  51         set_spr_addr    bad,lr
  52         set_icc         0x6 0
  53         tge             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  54
  55         set_spr_addr    bad,lr
  56         set_icc         0x7 0
  57         tge             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  58
  59         set_spr_addr    bad,lr
  60         set_icc         0x8 0
  61         tge             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  62
  63         set_spr_addr    bad,lr
  64         set_icc         0x9 0
  65         tge             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  66
  67         set_psr_et      1
  68         set_spr_addr    oka,lr
  69         set_icc         0xa 0
  70         tge             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  71         fail
  72 oka:
  73         set_psr_et      1
  74         set_spr_addr    okb,lr
  75         set_icc         0xb 0
  76         tge             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  77         fail
  78 okb:
  79         set_spr_addr    bad,lr
  80         set_icc         0xc 0
  81         tge             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  82
  83         set_spr_addr    bad,lr
  84         set_icc         0xd 0
  85         tge             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  86
  87         set_psr_et      1
  88         set_spr_addr    oke,lr
  89         set_icc         0xe 0
  90         tge             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  91         fail
  92 oke:
  93         set_psr_et      1
  94         set_spr_addr    okf,lr
  95         set_icc         0xf 0
  96         tge             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
  97         fail
  98 okf:
  99         pass
 100 bad:
 101         fail