1 # Hitachi H8 testcase 'rotxr'
3 # as(h8300): --defsym sim_cpu=0
4 # as(h8300h): --defsym sim_cpu=1
5 # as(h8300s): --defsym sim_cpu=2
6 # as(h8sx): --defsym sim_cpu=3
7 # ld(h8300h): -m h8300helf
8 # ld(h8300s): -m h8300self
9 # ld(h8sx): -m h8300sxelf
11 .include "testutils.inc"
18 word_dest: .word 0xa5a5
20 long_dest: .long 0xa5a5a5a5
25 set_grs_a5a5 ; Fill all general regs with a fixed pattern
28 rotxr.b r0l ; shift right arithmetic by one
31 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
36 test_h_gr16 0xa552 r0 ; 1010 0101 -> 0101 0010
38 test_h_gr32 0xa5a5a552 er0
40 test_gr_a5a5 1 ; Make sure other general regs not disturbed
50 set_grs_a5a5 ; Fill all general regs with a fixed pattern
54 rotxr.b @er0 ; shift right arithmetic by one, indirect
58 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
63 test_h_gr32 byte_dest er0
64 test_gr_a5a5 1 ; Make sure other general regs not disturbed
71 ; 1010 0101 -> 0101 0010
72 cmp.b #0x52, @byte_dest
76 mov #0xa5a5a5a5, @byte_dest
79 set_grs_a5a5 ; Fill all general regs with a fixed pattern
83 rotxr.b @er0+ ; shift right arithmetic by one, postinc
88 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
93 test_h_gr32 byte_dest+1 er0
94 test_gr_a5a5 1 ; Make sure other general regs not disturbed
101 ; 1010 0101 -> 0101 0010
102 cmp.b #0x52, @byte_dest
106 mov #0xa5a5a5a5, @byte_dest
109 set_grs_a5a5 ; Fill all general regs with a fixed pattern
113 rotxr.b @er0- ; shift right arithmetic by one, postdec
118 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
123 test_h_gr32 byte_dest-1 er0
124 test_gr_a5a5 1 ; Make sure other general regs not disturbed
131 ; 1010 0101 -> 0101 0010
132 cmp.b #0x52, @byte_dest
136 mov #0xa5a5a5a5, @byte_dest
139 set_grs_a5a5 ; Fill all general regs with a fixed pattern
142 mov #byte_dest-1, er0
143 rotxr.b @+er0 ; shift right arithmetic by one, preinc
148 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
153 test_h_gr32 byte_dest er0
154 test_gr_a5a5 1 ; Make sure other general regs not disturbed
161 ; 1010 0101 -> 0101 0010
162 cmp.b #0x52, @byte_dest
166 mov #0xa5a5a5a5, @byte_dest
169 set_grs_a5a5 ; Fill all general regs with a fixed pattern
172 mov #byte_dest+1, er0
173 rotxr.b @-er0 ; shift right arithmetic by one, predec
178 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
183 test_h_gr32 byte_dest er0
184 test_gr_a5a5 1 ; Make sure other general regs not disturbed
191 ; 1010 0101 -> 0101 0010
192 cmp.b #0x52, @byte_dest
196 mov #0xa5a5a5a5, @byte_dest
199 set_grs_a5a5 ; Fill all general regs with a fixed pattern
202 mov #byte_dest-2, er0
203 rotxr.b @(2:2, er0) ; shift right arithmetic by one, disp2
208 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
213 test_h_gr32 byte_dest-2 er0
214 test_gr_a5a5 1 ; Make sure other general regs not disturbed
221 ; 1010 0101 -> 0101 0010
222 cmp.b #0x52, @byte_dest
226 mov #0xa5a5a5a5, @byte_dest
229 set_grs_a5a5 ; Fill all general regs with a fixed pattern
232 mov #byte_dest-44, er0
233 rotxr.b @(44:16, er0) ; shift right arithmetic by one, disp16
239 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
244 test_h_gr32 byte_dest-44 er0
245 test_gr_a5a5 1 ; Make sure other general regs not disturbed
252 ; 1010 0101 -> 0101 0010
253 cmp.b #0x52, @byte_dest
257 mov #0xa5a5a5a5, @byte_dest
260 set_grs_a5a5 ; Fill all general regs with a fixed pattern
263 mov #byte_dest-666, er0
264 rotxr.b @(666:32, er0) ; shift right arithmetic by one, disp32
270 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
275 test_h_gr32 byte_dest-666 er0
276 test_gr_a5a5 1 ; Make sure other general regs not disturbed
283 ; 1010 0101 -> 0101 0010
284 cmp.b #0x52, @byte_dest
288 mov #0xa5a5a5a5, @byte_dest
291 set_grs_a5a5 ; Fill all general regs with a fixed pattern
294 rotxr.b @byte_dest:16 ; shift right arithmetic by one, abs16
299 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
304 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
312 ; 1010 0101 -> 0101 0010
313 cmp.b #0x52, @byte_dest
317 mov #0xa5a5a5a5, @byte_dest
320 set_grs_a5a5 ; Fill all general regs with a fixed pattern
323 rotxr.b @byte_dest:32 ; shift right arithmetic by one, abs32
328 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
333 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
341 ; 1010 0101 -> 0101 0010
342 cmp.b #0x52, @byte_dest
346 mov #0xa5a5a5a5, @byte_dest
350 set_grs_a5a5 ; Fill all general regs with a fixed pattern
353 rotxr.b #2, r0l ; shift right arithmetic by two
356 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
361 test_h_gr16 0xa5a9 r0 ; 1010 0101 -> 1010 1001
363 test_h_gr32 0xa5a5a5a9 er0
365 test_gr_a5a5 1 ; Make sure other general regs not disturbed
373 .if (sim_cpu == h8sx)
375 set_grs_a5a5 ; Fill all general regs with a fixed pattern
379 rotxr.b #2, @er0 ; shift right arithmetic by two, indirect
383 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
388 test_h_gr32 byte_dest er0
389 test_gr_a5a5 1 ; Make sure other general regs not disturbed
396 ; 1010 0101 -> 1010 1001
397 cmp.b #0xa9, @byte_dest
401 mov #0xa5a5a5a5, @byte_dest
404 set_grs_a5a5 ; Fill all general regs with a fixed pattern
408 rotxr.b #2, @er0+ ; shift right arithmetic by two, postinc
413 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
418 test_h_gr32 byte_dest+1 er0
419 test_gr_a5a5 1 ; Make sure other general regs not disturbed
426 ; 1010 0101 -> 1010 1001
427 cmp.b #0xa9, @byte_dest
431 mov #0xa5a5a5a5, @byte_dest
434 set_grs_a5a5 ; Fill all general regs with a fixed pattern
438 rotxr.b #2, @er0- ; shift right arithmetic by two, postdec
443 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
448 test_h_gr32 byte_dest-1 er0
449 test_gr_a5a5 1 ; Make sure other general regs not disturbed
456 ; 1010 0101 -> 1010 1001
457 cmp.b #0xa9, @byte_dest
461 mov #0xa5a5a5a5, @byte_dest
464 set_grs_a5a5 ; Fill all general regs with a fixed pattern
467 mov #byte_dest-1, er0
468 rotxr.b #2, @+er0 ; shift right arithmetic by two, preinc
473 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
478 test_h_gr32 byte_dest er0
479 test_gr_a5a5 1 ; Make sure other general regs not disturbed
486 ; 1010 0101 -> 1010 1001
487 cmp.b #0xa9, @byte_dest
491 mov #0xa5a5a5a5, @byte_dest
494 set_grs_a5a5 ; Fill all general regs with a fixed pattern
497 mov #byte_dest+1, er0
498 rotxr.b #2, @-er0 ; shift right arithmetic by two, predec
503 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
508 test_h_gr32 byte_dest er0
509 test_gr_a5a5 1 ; Make sure other general regs not disturbed
516 ; 1010 0101 -> 1010 1001
517 cmp.b #0xa9, @byte_dest
521 mov #0xa5a5a5a5, @byte_dest
524 set_grs_a5a5 ; Fill all general regs with a fixed pattern
527 mov #byte_dest-2, er0
528 rotxr.b #2, @(2:2, er0) ; shift right arithmetic by two, disp2
533 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
538 test_h_gr32 byte_dest-2 er0
539 test_gr_a5a5 1 ; Make sure other general regs not disturbed
546 ; 1010 0101 -> 1010 1001
547 cmp.b #0xa9, @byte_dest
551 mov #0xa5a5a5a5, @byte_dest
554 set_grs_a5a5 ; Fill all general regs with a fixed pattern
557 mov #byte_dest-44, er0
558 rotxr.b #2, @(44:16, er0) ; shift right arithmetic by two, disp16
564 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
569 test_h_gr32 byte_dest-44 er0
570 test_gr_a5a5 1 ; Make sure other general regs not disturbed
577 ; 1010 0101 -> 1010 1001
578 cmp.b #0xa9, @byte_dest
582 mov #0xa5a5a5a5, @byte_dest
585 set_grs_a5a5 ; Fill all general regs with a fixed pattern
588 mov #byte_dest-666, er0
589 rotxr.b #2, @(666:32, er0) ; shift right arithmetic by two, disp32
595 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
600 test_h_gr32 byte_dest-666 er0
601 test_gr_a5a5 1 ; Make sure other general regs not disturbed
608 ; 1010 0101 -> 1010 1001
609 cmp.b #0xa9, @byte_dest
613 mov #0xa5a5a5a5, @byte_dest
616 set_grs_a5a5 ; Fill all general regs with a fixed pattern
619 rotxr.b #2, @byte_dest:16 ; shift right arithmetic by two, abs16
624 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
629 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
637 ; 1010 0101 -> 1010 1001
638 cmp.b #0xa9, @byte_dest
642 mov #0xa5a5a5a5, @byte_dest
645 set_grs_a5a5 ; Fill all general regs with a fixed pattern
648 rotxr.b #2, @byte_dest:32 ; shift right arithmetic by two, abs32
653 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
658 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
666 ; 1010 0101 -> 1010 1001
667 cmp.b #0xa9, @byte_dest
671 mov #0xa5a5a5a5, @byte_dest
674 .if (sim_cpu) ; Not available in h8300 mode
676 set_grs_a5a5 ; Fill all general regs with a fixed pattern
679 rotxr.w r0 ; shift right arithmetic by one
682 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
687 test_h_gr16 0x52d2 r0 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
688 test_h_gr32 0xa5a552d2 er0
690 test_gr_a5a5 1 ; Make sure other general regs not disturbed
698 .if (sim_cpu == h8sx)
700 set_grs_a5a5 ; Fill all general regs with a fixed pattern
704 rotxr.w @er0 ; shift right arithmetic by one, indirect
708 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
713 test_h_gr32 word_dest er0
714 test_gr_a5a5 1 ; Make sure other general regs not disturbed
721 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
722 cmp.w #0x52d2, @word_dest
726 mov #0xa5a5a5a5, @word_dest
729 set_grs_a5a5 ; Fill all general regs with a fixed pattern
733 rotxr.w @er0+ ; shift right arithmetic by one, postinc
738 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
743 test_h_gr32 word_dest+2 er0
744 test_gr_a5a5 1 ; Make sure other general regs not disturbed
751 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
752 cmp.w #0x52d2, @word_dest
756 mov #0xa5a5a5a5, @word_dest
759 set_grs_a5a5 ; Fill all general regs with a fixed pattern
763 rotxr.w @er0- ; shift right arithmetic by one, postdec
768 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
773 test_h_gr32 word_dest-2 er0
774 test_gr_a5a5 1 ; Make sure other general regs not disturbed
781 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
782 cmp.w #0x52d2, @word_dest
786 mov #0xa5a5a5a5, @word_dest
789 set_grs_a5a5 ; Fill all general regs with a fixed pattern
792 mov #word_dest-2, er0
793 rotxr.w @+er0 ; shift right arithmetic by one, preinc
798 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
803 test_h_gr32 word_dest er0
804 test_gr_a5a5 1 ; Make sure other general regs not disturbed
811 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
812 cmp.w #0x52d2, @word_dest
816 mov #0xa5a5a5a5, @word_dest
819 set_grs_a5a5 ; Fill all general regs with a fixed pattern
822 mov #word_dest+2, er0
823 rotxr.w @-er0 ; shift right arithmetic by one, predec
828 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
833 test_h_gr32 word_dest er0
834 test_gr_a5a5 1 ; Make sure other general regs not disturbed
841 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
842 cmp.w #0x52d2, @word_dest
846 mov #0xa5a5a5a5, @word_dest
849 set_grs_a5a5 ; Fill all general regs with a fixed pattern
852 mov #word_dest-4, er0
853 rotxr.w @(4:2, er0) ; shift right arithmetic by one, disp2
858 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
863 test_h_gr32 word_dest-4 er0
864 test_gr_a5a5 1 ; Make sure other general regs not disturbed
871 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
872 cmp.w #0x52d2, @word_dest
876 mov #0xa5a5a5a5, @word_dest
879 set_grs_a5a5 ; Fill all general regs with a fixed pattern
882 mov #word_dest-44, er0
883 rotxr.w @(44:16, er0) ; shift right arithmetic by one, disp16
889 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
894 test_h_gr32 word_dest-44 er0
895 test_gr_a5a5 1 ; Make sure other general regs not disturbed
902 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
903 cmp.w #0x52d2, @word_dest
907 mov #0xa5a5a5a5, @word_dest
910 set_grs_a5a5 ; Fill all general regs with a fixed pattern
913 mov #word_dest-666, er0
914 rotxr.w @(666:32, er0) ; shift right arithmetic by one, disp32
920 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
925 test_h_gr32 word_dest-666 er0
926 test_gr_a5a5 1 ; Make sure other general regs not disturbed
933 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
934 cmp.w #0x52d2, @word_dest
938 mov #0xa5a5a5a5, @word_dest
941 set_grs_a5a5 ; Fill all general regs with a fixed pattern
944 rotxr.w @word_dest:16 ; shift right arithmetic by one, abs16
949 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
954 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
962 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
963 cmp.w #0x52d2, @word_dest
967 mov #0xa5a5a5a5, @word_dest
970 set_grs_a5a5 ; Fill all general regs with a fixed pattern
973 rotxr.w @word_dest:32 ; shift right arithmetic by one, abs32
978 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
983 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
991 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
992 cmp.w #0x52d2, @word_dest
996 mov #0xa5a5a5a5, @word_dest
1000 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1003 rotxr.w #2, r0 ; shift right arithmetic by two
1006 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1011 test_h_gr16 0xa969 r0 ; 1010 0101 1010 0101 -> 1010 1001 0110 1001
1012 test_h_gr32 0xa5a5a969 er0
1013 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1021 .if (sim_cpu == h8sx)
1023 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1027 rotxr.w #2, @er0 ; shift right arithmetic by two, indirect
1031 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1036 test_h_gr32 word_dest er0
1037 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1044 ; 1010 0101 1010 0101 -> 1010 1001 0110 1001
1045 cmp.w #0xa969, @word_dest
1049 mov #0xa5a5a5a5, @word_dest
1052 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1056 rotxr.w #2, @er0+ ; shift right arithmetic by two, postinc
1061 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1066 test_h_gr32 word_dest+2 er0
1067 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1074 ; 1010 0101 1010 0101 -> 1010 1001 0110 1001
1075 cmp.w #0xa969, @word_dest
1079 mov #0xa5a5a5a5, @word_dest
1082 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1086 rotxr.w #2, @er0- ; shift right arithmetic by two, postdec
1091 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1096 test_h_gr32 word_dest-2 er0
1097 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1104 ; 1010 0101 1010 0101 -> 1010 1001 0110 1001
1105 cmp.w #0xa969, @word_dest
1109 mov #0xa5a5a5a5, @word_dest
1112 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1115 mov #word_dest-2, er0
1116 rotxr.w #2, @+er0 ; shift right arithmetic by two, preinc
1121 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1126 test_h_gr32 word_dest er0
1127 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1134 ; 1010 0101 1010 0101 -> 1010 1001 0110 1001
1135 cmp.w #0xa969, @word_dest
1139 mov #0xa5a5a5a5, @word_dest
1142 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1145 mov #word_dest+2, er0
1146 rotxr.w #2, @-er0 ; shift right arithmetic by two, predec
1151 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1156 test_h_gr32 word_dest er0
1157 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1164 ; 1010 0101 1010 0101 -> 1010 1001 0110 1001
1165 cmp.w #0xa969, @word_dest
1169 mov #0xa5a5a5a5, @word_dest
1172 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1175 mov #word_dest-4, er0
1176 rotxr.w #2, @(4:2, er0) ; shift right arithmetic by two, disp2
1181 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1186 test_h_gr32 word_dest-4 er0
1187 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1194 ; 1010 0101 1010 0101 -> 1010 1001 0110 1001
1195 cmp.w #0xa969, @word_dest
1199 mov #0xa5a5a5a5, @word_dest
1202 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1205 mov #word_dest-44, er0
1206 rotxr.w #2, @(44:16, er0) ; shift right arithmetic by two, disp16
1212 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1217 test_h_gr32 word_dest-44 er0
1218 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1225 ; 1010 0101 1010 0101 -> 1010 1001 0110 1001
1226 cmp.w #0xa969, @word_dest
1230 mov #0xa5a5a5a5, @word_dest
1233 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1236 mov #word_dest-666, er0
1237 rotxr.w #2, @(666:32, er0) ; shift right arithmetic by two, disp32
1243 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1248 test_h_gr32 word_dest-666 er0
1249 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1256 ; 1010 0101 1010 0101 -> 1010 1001 0110 1001
1257 cmp.w #0xa969, @word_dest
1261 mov #0xa5a5a5a5, @word_dest
1264 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1267 rotxr.w #2, @word_dest:16 ; shift right arithmetic by two, abs16
1272 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1277 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
1285 ; 1010 0101 1010 0101 -> 1010 1001 0110 1001
1286 cmp.w #0xa969, @word_dest
1290 mov #0xa5a5a5a5, @word_dest
1293 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1296 rotxr.w #2, @word_dest:32 ; shift right arithmetic by two, abs32
1301 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1306 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
1314 ; 1010 0101 1010 0101 -> 1010 1001 0110 1001
1315 cmp.w #0xa969, @word_dest
1319 mov #0xa5a5a5a5, @word_dest
1323 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1326 rotxr.l er0 ; shift right arithmetic by one, register
1329 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
1334 ; 1010 0101 1010 0101 1010 0101 1010 0101
1335 ; -> 0101 0010 1101 0010 1101 0010 1101 0010
1336 test_h_gr32 0x52d2d2d2 er0
1338 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1346 .if (sim_cpu == h8sx)
1348 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1352 rotxr.l @er0 ; shift right arithmetic by one, indirect
1357 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
1362 test_h_gr32 long_dest er0
1363 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1370 ; 1010 0101 1010 0101 1010 0101 1010 0101
1371 ;; -> 0101 0010 1101 0010 1101 0010 1101 0010
1372 cmp.l #0x52d2d2d2, @long_dest
1376 mov #0xa5a5a5a5, @long_dest
1379 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1383 rotxr.l @er0+ ; shift right arithmetic by one, postinc
1388 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
1393 test_h_gr32 long_dest+4 er0
1394 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1401 ; 1010 0101 1010 0101 1010 0101 1010 0101
1402 ;; -> 0101 0010 1101 0010 1101 0010 1101 0010
1403 cmp.l #0x52d2d2d2, @long_dest
1407 mov #0xa5a5a5a5, @long_dest
1410 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1414 rotxr.l @er0- ; shift right arithmetic by one, postdec
1419 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
1424 test_h_gr32 long_dest-4 er0
1425 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1432 ; 1010 0101 1010 0101 1010 0101 1010 0101
1433 ;; -> 0101 0010 1101 0010 1101 0010 1101 0010
1434 cmp.l #0x52d2d2d2, @long_dest
1438 mov #0xa5a5a5a5, @long_dest
1441 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1444 mov #long_dest-4, er0
1445 rotxr.l @+er0 ; shift right arithmetic by one, preinc
1450 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
1455 test_h_gr32 long_dest er0
1456 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1463 ; 1010 0101 1010 0101 1010 0101 1010 0101
1464 ;; -> 0101 0010 1101 0010 1101 0010 1101 0010
1465 cmp.l #0x52d2d2d2, @long_dest
1469 mov #0xa5a5a5a5, @long_dest
1472 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1475 mov #long_dest+4, er0
1476 rotxr.l @-er0 ; shift right arithmetic by one, predec
1481 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
1486 test_h_gr32 long_dest er0
1487 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1494 ; 1010 0101 1010 0101 1010 0101 1010 0101
1495 ;; -> 0101 0010 1101 0010 1101 0010 1101 0010
1496 cmp.l #0x52d2d2d2, @long_dest
1500 mov #0xa5a5a5a5, @long_dest
1503 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1506 mov #long_dest-8, er0
1507 rotxr.l @(8:2, er0) ; shift right arithmetic by one, disp2
1512 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
1517 test_h_gr32 long_dest-8 er0
1518 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1525 ; 1010 0101 1010 0101 1010 0101 1010 0101
1526 ;; -> 0101 0010 1101 0010 1101 0010 1101 0010
1527 cmp.l #0x52d2d2d2, @long_dest
1531 mov #0xa5a5a5a5, @long_dest
1534 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1537 mov #long_dest-44, er0
1538 rotxr.l @(44:16, er0) ; shift right arithmetic by one, disp16
1544 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
1549 test_h_gr32 long_dest-44 er0
1550 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1557 ; 1010 0101 1010 0101 1010 0101 1010 0101
1558 ;; -> 0101 0010 1101 0010 1101 0010 1101 0010
1559 cmp.l #0x52d2d2d2, @long_dest
1563 mov #0xa5a5a5a5, @long_dest
1566 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1569 mov #long_dest-666, er0
1570 rotxr.l @(666:32, er0) ; shift right arithmetic by one, disp32
1576 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
1581 test_h_gr32 long_dest-666 er0
1582 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1589 ; 1010 0101 1010 0101 1010 0101 1010 0101
1590 ;; -> 0101 0010 1101 0010 1101 0010 1101 0010
1591 cmp.l #0x52d2d2d2, @long_dest
1595 mov #0xa5a5a5a5, @long_dest
1598 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1601 rotxr.l @long_dest:16 ; shift right arithmetic by one, abs16
1607 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
1612 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
1620 ; 1010 0101 1010 0101 1010 0101 1010 0101
1621 ;; -> 0101 0010 1101 0010 1101 0010 1101 0010
1622 cmp.l #0x52d2d2d2, @long_dest
1626 mov #0xa5a5a5a5, @long_dest
1629 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1632 rotxr.l @long_dest:32 ; shift right arithmetic by one, abs32
1638 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
1643 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
1651 ; 1010 0101 1010 0101 1010 0101 1010 0101
1652 ;; -> 0101 0010 1101 0010 1101 0010 1101 0010
1653 cmp.l #0x52d2d2d2, @long_dest
1657 mov #0xa5a5a5a5, @long_dest
1661 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1664 rotxr.l #2, er0 ; shift right arithmetic by two, register
1667 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1671 ; 1010 0101 1010 0101 1010 0101 1010 0101
1672 ; -> 1010 1001 0110 1001 0110 1001 0110 1001
1673 test_h_gr32 0xa9696969 er0
1675 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1683 .if (sim_cpu == h8sx)
1686 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1690 rotxr.l #2, @er0 ; shift right arithmetic by two, indirect
1695 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1700 test_h_gr32 long_dest er0
1701 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1708 ; 1010 0101 1010 0101 1010 0101 1010 0101
1709 ;; -> 1010 1001 0110 1001 0110 1001 0110 1001
1710 cmp.l #0xa9696969, @long_dest
1714 mov #0xa5a5a5a5, @long_dest
1717 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1721 rotxr.l #2, @er0+ ; shift right arithmetic by two, postinc
1726 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1731 test_h_gr32 long_dest+4 er0
1732 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1739 ; 1010 0101 1010 0101 1010 0101 1010 0101
1740 ;; -> 1010 1001 0110 1001 0110 1001 0110 1001
1741 cmp.l #0xa9696969, @long_dest
1745 mov #0xa5a5a5a5, @long_dest
1748 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1752 rotxr.l #2, @er0- ; shift right arithmetic by two, postdec
1757 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1762 test_h_gr32 long_dest-4 er0
1763 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1770 ; 1010 0101 1010 0101 1010 0101 1010 0101
1771 ;; -> 1010 1001 0110 1001 0110 1001 0110 1001
1772 cmp.l #0xa9696969, @long_dest
1776 mov #0xa5a5a5a5, @long_dest
1779 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1782 mov #long_dest-4, er0
1783 rotxr.l #2, @+er0 ; shift right arithmetic by two, preinc
1788 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1793 test_h_gr32 long_dest er0
1794 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1801 ; 1010 0101 1010 0101 1010 0101 1010 0101
1802 ;; -> 1010 1001 0110 1001 0110 1001 0110 1001
1803 cmp.l #0xa9696969, @long_dest
1807 mov #0xa5a5a5a5, @long_dest
1810 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1813 mov #long_dest+4, er0
1814 rotxr.l #2, @-er0 ; shift right arithmetic by two, predec
1819 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1824 test_h_gr32 long_dest er0
1825 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1832 ; 1010 0101 1010 0101 1010 0101 1010 0101
1833 ;; -> 1010 1001 0110 1001 0110 1001 0110 1001
1834 cmp.l #0xa9696969, @long_dest
1838 mov #0xa5a5a5a5, @long_dest
1841 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1844 mov #long_dest-8, er0
1845 rotxr.l #2, @(8:2, er0) ; shift right arithmetic by two, disp2
1850 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1855 test_h_gr32 long_dest-8 er0
1856 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1863 ; 1010 0101 1010 0101 1010 0101 1010 0101
1864 ;; -> 1010 1001 0110 1001 0110 1001 0110 1001
1865 cmp.l #0xa9696969, @long_dest
1869 mov #0xa5a5a5a5, @long_dest
1872 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1875 mov #long_dest-44, er0
1876 rotxr.l #2, @(44:16, er0) ; shift right arithmetic by two, disp16
1882 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1887 test_h_gr32 long_dest-44 er0
1888 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1895 ; 1010 0101 1010 0101 1010 0101 1010 0101
1896 ;; -> 1010 1001 0110 1001 0110 1001 0110 1001
1897 cmp.l #0xa9696969, @long_dest
1901 mov #0xa5a5a5a5, @long_dest
1904 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1907 mov #long_dest-666, er0
1908 rotxr.l #2, @(666:32, er0) ; shift right arithmetic by two, disp32
1914 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1919 test_h_gr32 long_dest-666 er0
1920 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1927 ; 1010 0101 1010 0101 1010 0101 1010 0101
1928 ;; -> 1010 1001 0110 1001 0110 1001 0110 1001
1929 cmp.l #0xa9696969, @long_dest
1933 mov #0xa5a5a5a5, @long_dest
1936 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1939 rotxr.l #2, @long_dest:16 ; shift right arithmetic by two, abs16
1945 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1950 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
1958 ; 1010 0101 1010 0101 1010 0101 1010 0101
1959 ;; -> 1010 1001 0110 1001 0110 1001 0110 1001
1960 cmp.l #0xa9696969, @long_dest
1964 mov #0xa5a5a5a5, @long_dest
1967 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1970 rotxr.l #2, @long_dest:32 ; shift right arithmetic by two, abs32
1976 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1981 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
1989 ; 1010 0101 1010 0101 1010 0101 1010 0101
1990 ;; -> 1010 1001 0110 1001 0110 1001 0110 1001
1991 cmp.l #0xa9696969, @long_dest
1995 mov #0xa5a5a5a5, @long_dest