1 # Hitachi H8 testcase 'sub.w'
3 # as(h8300): --defsym sim_cpu=0
4 # as(h8300h): --defsym sim_cpu=1
5 # as(h8300s): --defsym sim_cpu=2
6 # as(h8sx): --defsym sim_cpu=3
7 # ld(h8300h): -m h8300helf
8 # ld(h8300s): -m h8300self
9 # ld(h8sx): -m h8300sxelf
11 .include "testutils.inc"
14 .if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx
15 sub_w_imm3: ; sub.w immediate not available in h8300 mode.
16 set_grs_a5a5 ; Fill all general regs with a fixed pattern
19 ;; sub.w #xx:3,Rd ; Immediate 3-bit operand
22 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
23 test_h_gr16 0xa59e r0 ; sub result: a5a5 - 7
24 test_h_gr32 0xa5a5a59e er0 ; sub result: a5a5 - 7
25 test_gr_a5a5 1 ; Make sure other general regs not disturbed
34 .if (sim_cpu) ; non-zero means h8300h, s, or sx
35 sub_w_imm16: ; sub.w immediate not available in h8300 mode.
36 set_grs_a5a5 ; Fill all general regs with a fixed pattern
40 sub.w #0x111, r0 ; Immediate 16-bit operand
42 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
43 test_h_gr16 0xa494 r0 ; sub result: a5a5 - 111
44 test_h_gr32 0xa5a5a494 er0 ; sub result: a5a5 - 111
45 test_gr_a5a5 1 ; Make sure other general regs not disturbed
55 set_grs_a5a5 ; Fill all general regs with a fixed pattern
60 sub.w r1, r0 ; Register operand
62 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
63 test_h_gr16 0xa494 r0 ; sub result: a5a5 - 111
65 .if (sim_cpu) ; non-zero means h8300h, s, or sx
66 test_h_gr32 0xa5a5a494 er0 ; sub result: a5a5 - 111
67 test_h_gr32 0xa5a50111 er1
69 test_gr_a5a5 2 ; Make sure other general regs not disturbed