1 Tue May 20 09:33:31 1997 Andrew Cagney <cagney@b1.cygnus.com>
3 * sim-calls.c (sim_set_callback): Delete.
4 (sim_open): Add/install callback argument.
6 Mon May 19 18:59:33 1997 Mike Meissner <meissner@cygnus.com>
8 * configure.in: Check for getpid, kill functions.
9 * config{.in,ure}: Regenerate.
11 * insns (do_trap): Add support for kill, getpid system calls.
13 * sim-main.h (errno.h): Include.
14 (getpid,kill): Define as NOPs if the host doesn't have them.
16 Mon May 19 14:58:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
18 * sim-calls.c (sim_open): Set the simulator base magic number.
19 (sim_load): Delete prototype of sim_load_file.
20 (sim_open): Define sd to be &simulation.
22 Fri May 16 14:35:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
24 * insns (illegal, fp_unavailable): Halt instead of abort the
27 * insns: Replace calls to engine_error with sim_engine_abort.
28 Ditto for engine_halt V sim_engine_halt.
30 Tue May 13 15:24:12 1997 Andrew Cagney <cagney@b2.cygnus.com>
32 * interp.c (engine_run_until_stop): Delete. Moved to common.
36 (engine_restart): Ditto.
38 (engine_error): Ditto.
40 * sim-calls.c (sim_stop): Delete. Moved to common.
41 (sim_stop_reason): Ditto.
44 * Makefile.in (SIM_OBJS): Link in generic sim-engine, sim-run,
45 sim-resume, sim-reason, sim-stop modules.
47 Fri May 16 11:57:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
49 * ic (compute): Drop check for REG == 0, now always forced to
52 * cpu.h (GPR_SET): New macro update the gpr.
53 * insns (do_add): Use GPR_SET to update the GPR register.
55 * sim-calls.c (sim_fetch_register): Pretend that r0 is zero.
57 * Makefile.in (tmp-igen): Specify zero-r0 so that every
58 instruction clears r0.
60 * interp.c (engine_run_until_stop): Igen now generates code to
64 Thu May 15 11:45:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
66 * insns (do_shift): When rot==0 and zero/sign merge treat it as
68 (set_fp_reg): For interger conversion, use sim-fpu fpu2i
70 (do_fmpy): Perform iii and uuu using integer arithmetic.
72 * Makefile.in (ENGINE_H): Assume everything depends on the fpu.
74 * insns (get_fp_reg): Use sim_fpu_u32to to perform unsigned
76 (do_fcmp): Update to use new fp compare functions. Make reg nr arg
77 instead of reg. Stops fp overflow.
78 (get_fp_reg): Assume val is valid when reg == 0.
79 (set_fp_reg): Fix double conversion.
81 * misc.c (tic80_trace_fpu1): New function, trace simple fp op.
83 * insns (do_frnd): Add tracing.
85 * cpu.h (TRACE_FPU1): Ditto.
87 * insns (do_trap): Printf formatting.
89 Wed May 14 18:05:50 1997 Mike Meissner <meissner@cygnus.com>
91 * misc.c (tic80_trace_fpu{3,2,2i}): Align columns with other
92 insns. Use %g to print floating point instead of %f in case the
93 numbers are real large.
95 Tue May 13 18:00:10 1997 Mike Meissner <meissner@cygnus.com>
97 * insns (do_trap): For system calls that are defined, but not
98 provided return EINVAL. Temporarily add traps 74-79 to just print
101 * interp.c (engine_{run_until_stop,step}): Before executing
102 instructions, make sure r0 == 0.
104 Tue May 13 16:39:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
106 * alu.h (IMEM): Take full cia not just IP as argument.
108 * interp.c (engine_run_until_stop): Delete handling of annuled
110 (engine_step): Ditto.
112 * insn (do_branch): New function.
113 (do_bbo, do_bbz, do_bcnd, do_bsr, do_jsr): Use do_branch to handle
116 Mon May 12 17:15:52 1997 Mike Meissner <meissner@cygnus.com>
118 * insns (do_{ld,st}): Fix tracing for ld/st.
120 Mon May 12 11:12:24 1997 Andrew Cagney <cagney@b1.cygnus.com>
122 * sim-calls.c (sim_stop_reason): Restore keep_running after a
123 CNTRL-C, don't re-clear it.
125 * interp.c (engine_error): stop rather than signal with SIGABRT
128 * insns (do_ld): For 64bit loads, always store LSW in rDest, MSW in
129 rDest + 1. Also done by Michael Meissner <meissner@cygnus.com>
130 (do_st): Converse for store.
132 * misc.c (tic80_trace_fpu2i): Correct printf format for int type.
134 Sun May 11 11:02:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
136 * sim-calls.c (sim_stop_reason): Return a SIGINT if keep_running
139 * interp.c (engine_step): New function. Single step the simulator
140 taking care of cntrl-c during a step.
142 * sim-calls.c (sim_resume): Differentiate between stepping and
143 running so that a cntrl-c during a step is reported.
145 Sun May 11 10:54:31 1997 Mark Alexander <marka@cygnus.com>
147 * sim-calls.c (sim_fetch_register): Use correct reg base.
148 (sim_store_register): Ditto.
150 Sun May 11 10:25:14 1997 Michael Meissner <meissner@cygnus.com>
152 * cpu.h (tic80_trace_shift): Add declaration.
153 (TRACE_SHIFT): New macro to trace shift instructions.
155 * misc.c (tic80_trace_alu2): Align spacing.
156 (tic80_trace_shift): New function to trace shifts.
158 * insns (lmo): Add missing 0b prefix to bits.
159 (do_shift): Use ~ (unsigned32)0, instead of -1. Use TRACE_SHIFT
160 instead of TRACE_ALU2.
161 (sl r): Use EndMask as is, instead of using Source+1 register.
162 (subu): Operands are unsigned, not signed.
163 (do_{ld,st}): Fix endian problems with ld.d/st.d.
165 Sat May 10 12:35:47 1997 Michael Meissner <meissner@cygnus.com>
167 * insns (and{.tt,.tf,.ft,.ff}): Immediate values are unsigned, not
170 Fri May 9 15:47:36 1997 Mike Meissner <meissner@cygnus.com>
172 * insns (cmp_vals,do_cmp): Produce the correct bits as specified
174 (xor): Fix xor immediate patterns to use the correct bits.
176 Fri May 9 09:55:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
178 * alu.h (long_immediate): Adjust the CIA delay-pointer as well as
179 the NIA when a 64bit insn.
181 Thu May 8 11:57:47 1997 Michael Meissner <meissner@cygnus.com>
183 * insns (jsr,bsr): For non-allulled calls, set r31 so that the
184 return address does not reexecute the instruction in the delay
186 (bbo,bbz): Complement bit number to reverse the one's complement
187 that the assembler is required to do.
189 * misc.c (tic80_trace_*): Change format slightly to accomidate
190 real large decimal values.
192 Thu May 8 14:07:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
194 * sim-calls.c (sim_do_command): Implement.
195 (sim_store_register): Fix typo T2H v H2T.
197 Wed May 7 11:48:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
199 * cpu.h (TRACE_FPU2, TRACE_FPU3, TRACE_FPU2I): Add.
200 * insn: Clean up fpu tracing.
202 * sim-calls.c (sim_create_inferior): Start out with interrupts
205 * cpu.h (TRACE_SINK3), misc.c (tic80_trace_sink3): Three argument
208 * insns (rdcr, swcr, wrcr, brcr, rmo, lmo): Implement.
210 * insns (do_*): Remove MY_INDEX/indx argument from support functions,
211 igen now handles this.
213 * cpu.h (CR): New macro - access TIc80 control registers.
216 (tic80_cr2index): New function, map control register opcode index
217 into the internal CR enum.
220 (tic80_trace_{alu{2,3},nop,sink{1,2},{,u}cond_br,ldst}): Move from
224 * Makefile.in (SIM_OBJS): Add misc.o.
226 Tue May 6 15:22:58 1997 Mike Meissner <meissner@cygnus.com>
228 * cpu.h ({,v}{S,D}P_FPR): Delete unused macros that won't work on
230 (tic80_trace_{alu{2,3},nop,sink{1,2},{,u}cond_br,ldst}): Declare
232 (TRACE_{ALU{2,3},NOP,SINK{1,2},{,U}COND_BR,LD,ST}): New macros to
233 trace various instruction types.
235 * insns: Modify all instructions to support semantic tracing.
237 * interp.c (toplevel): Include itable.h.
238 (tic80_trace_{alu{2,3},nop,sink{1,2},{,u}cond_br,ldst}): New
239 functions to provide semantic level tracing information.
241 Mon May 5 11:50:43 1997 Andrew Cagney <cagney@b1.cygnus.com>
243 * alu.h: Update usage of core object to reflect recent changes in
245 * sim-calls.c (sim_open): Ditto.
247 Mon May 5 14:10:17 1997 Andrew Cagney <cagney@b1.cygnus.com>
249 * insn (cmnd): No-op cache flushes.
251 * insns (do_trap): Allow writes to STDERR.
253 * Makefile.in (SIM_OBJS): Link in sim-fpu.o.
254 (SIM_EXTRA_LIBS): Link in the math library.
256 * alu.h: Add support for floating point unit using sim-alu.
258 * insns (fadd, fsub, fmpy, fdiv, fcmp, frnd*): Implement.
260 Fri May 2 14:57:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
262 * sim-calls.c: Include sim-utils.h and sim-options.h.
264 * sim-main.h (sim_state): Drop sim_events and sim_core members,
265 moved to simulator base type.
267 * alu.h (IMEM, MEM, STORE): Update track changes in common
270 * insns: Drop cia argument from functions, igen now handles this.
272 * interp.c (engine_init): Include string.h/strings.h to define
275 * sim-main.h (sim_cia): Delcare, tracking common dir changes.
277 * cpu.h (sim_cpu): Update instruction_address with sim_cia.
279 Wed Apr 30 11:26:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
281 * sim-main.h (signal.h): Include so that SIG* available to all
284 * insns (do_shift): New function, implement shift operations.
285 (do_trap): Add handler for trap 73 - SIGTRAP.
287 Tue Apr 29 10:58:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
289 * alu.h (MEM, STORE): Force addresses to be correctly aligned.
291 * insns (do_jsr): Fix.
292 (do_st, do_ld): Handle 64bit transfers.
293 (do_trap): Match libgloss.
294 (rdcr): Implement nop - Dest == r0 - variant.
296 * sim-calls.c (sim_create_inferior): Initialize SP.
298 * Makefile.in (ENGINE_H): Everything now depends on sim-options.h.
299 (support.o): Depends on ENGINE_H.
301 * cpu.h: Four accumulators.
303 * Makefile.in (tmp-igen): Include line number information in
306 * insns (dld, dst): Fill in.
308 Mon Apr 28 13:02:26 1997 Andrew Cagney <cagney@b1.cygnus.com>
310 * insns (vld): Fix instruction format wrong.
312 Thu Apr 24 16:43:09 1997 Andrew Cagney <cagney@b1.cygnus.com>
314 * dc: Add additional rules so that minor opcode files are
316 * insns: Enable more instructions.
318 * sim-calls.c (sim_fetch_register,sim_store_register, sim_write):
321 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
323 * configure: Regenerated to track ../common/aclocal.m4 changes.
324 * Makefile.in (SIM_OBJS): Add sim-module.o, sim-profile.o.
325 * sim-calls.c (sim_open): Call sim_module_uninstall if argument
326 parsing fails. Call sim_post_argv_init.
327 (sim_close): Call sim_module_uninstall.
329 Wed Apr 23 20:05:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
331 * insns (and, bbo, bcnd, bsr, dcache, jsr, or, xor, nor): Enable.
332 * ic: Add fields for enabled instructions.