1 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3 * configure: Regenerated to track ../common/aclocal.m4 changes.
6 Wed Aug 27 13:41:24 1997 Andrew Cagney <cagney@b1.cygnus.com>
8 * insns (do_st): Use U8_4 instead of V4_L8.
10 * sim-calls.c (sim_open): Add call to sim_analyze_program, update
13 * sim-calls.c (sim_kill): Delete.
14 (sim_create_inferior): Add ABFD argument. Initialize PC from ABFD
16 (sim_load): Delete, use sim-hload.c.
18 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
20 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
22 * configure: Regenerated to track ../common/aclocal.m4 changes.
25 Mon Aug 25 16:33:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
27 * sim-calls.c (sim_open): Add ABFD argument.
28 (sim_open): Move sim_config call to just after argument
29 parsing. Check return status.
31 Fri Aug 8 21:52:27 1997 Mark Alexander <marka@cygnus.com>
33 * sim-calls.c (sim_store_register): Allow accumulators
34 other than A0 to be modified. Correct error message.
36 Thu May 29 14:02:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
38 * misc.c (tic80_trace_fpu3, tic80_trace_fpu2, tic80_trace_fpu1,
39 tic80_trace_fpu2i): Pass in function prefix.
40 (tic80_trace_ldst): Rewrite so it calls print_one_insn directly.
42 * Makefile.in (SIM_OBJS): Include sim-watch.o module.
44 * sim-main.h (WITH_WATCHPOINTS): Enable watchpoints.
46 * ic (bitnum): Compute bitnum from BITNUM.
47 * insn (bbo, bbz): Use.
49 * insn: Convert long immediate instructions to igen long immediate
51 * insn: Add disasembler information.
53 Thu May 29 12:09:13 1997 Andrew Cagney <cagney@b2.cygnus.com>
55 * alu.h (IMEM_IMMED): New macro, fetch 32bit immediate operand N.
57 * insns (subu i): Immediate is signed not unsigned.
59 Tue May 27 13:22:13 1997 Andrew Cagney <cagney@b1.cygnus.com>
61 * sim-calls.c (sim_read): Pass NULL cpu to sim_core_read_buffer.
62 (sim_write): Ditto for write.
64 Tue May 20 09:33:31 1997 Andrew Cagney <cagney@b1.cygnus.com>
66 * sim-calls.c (sim_load): Set STATE_LOADED_P.
68 * sim-main.h: Include <unistd.h>.
70 * sim-calls.c (sim_set_callback): Delete.
71 (sim_open): Add/install callback argument.
74 Mon May 19 18:59:33 1997 Mike Meissner <meissner@cygnus.com>
76 * configure.in: Check for getpid, kill functions.
77 * config{.in,ure}: Regenerate.
79 * insns (do_trap): Add support for kill, getpid system calls.
81 * sim-main.h (errno.h): Include.
82 (getpid,kill): Define as NOPs if the host doesn't have them.
84 Mon May 19 14:58:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
86 * sim-calls.c (sim_open): Set the simulator base magic number.
87 (sim_load): Delete prototype of sim_load_file.
88 (sim_open): Define sd to be &simulation.
90 Fri May 16 14:35:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
92 * insns (illegal, fp_unavailable): Halt instead of abort the
95 * insns: Replace calls to engine_error with sim_engine_abort.
96 Ditto for engine_halt V sim_engine_halt.
98 Tue May 13 15:24:12 1997 Andrew Cagney <cagney@b2.cygnus.com>
100 * interp.c (engine_run_until_stop): Delete. Moved to common.
101 (engine_step): Ditto.
102 (engine_step): Ditto.
103 (engine_halt): Ditto.
104 (engine_restart): Ditto.
105 (engine_halt): Ditto.
106 (engine_error): Ditto.
108 * sim-calls.c (sim_stop): Delete. Moved to common.
109 (sim_stop_reason): Ditto.
112 * Makefile.in (SIM_OBJS): Link in generic sim-engine, sim-run,
113 sim-resume, sim-reason, sim-stop modules.
115 Fri May 16 11:57:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
117 * ic (compute): Drop check for REG == 0, now always forced to
120 * cpu.h (GPR_SET): New macro update the gpr.
121 * insns (do_add): Use GPR_SET to update the GPR register.
123 * sim-calls.c (sim_fetch_register): Pretend that r0 is zero.
125 * Makefile.in (tmp-igen): Specify zero-r0 so that every
126 instruction clears r0.
128 * interp.c (engine_run_until_stop): Igen now generates code to
130 (engine_step): Ditto.
132 Thu May 15 11:45:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
134 * insns (do_shift): When rot==0 and zero/sign merge treat it as
136 (set_fp_reg): For interger conversion, use sim-fpu fpu2i
138 (do_fmpy): Perform iii and uuu using integer arithmetic.
140 * Makefile.in (ENGINE_H): Assume everything depends on the fpu.
142 * insns (get_fp_reg): Use sim_fpu_u32to to perform unsigned
144 (do_fcmp): Update to use new fp compare functions. Make reg nr arg
145 instead of reg. Stops fp overflow.
146 (get_fp_reg): Assume val is valid when reg == 0.
147 (set_fp_reg): Fix double conversion.
149 * misc.c (tic80_trace_fpu1): New function, trace simple fp op.
151 * insns (do_frnd): Add tracing.
153 * cpu.h (TRACE_FPU1): Ditto.
155 * insns (do_trap): Printf formatting.
157 Wed May 14 18:05:50 1997 Mike Meissner <meissner@cygnus.com>
159 * misc.c (tic80_trace_fpu{3,2,2i}): Align columns with other
160 insns. Use %g to print floating point instead of %f in case the
161 numbers are real large.
163 Tue May 13 18:00:10 1997 Mike Meissner <meissner@cygnus.com>
165 * insns (do_trap): For system calls that are defined, but not
166 provided return EINVAL. Temporarily add traps 74-79 to just print
169 * interp.c (engine_{run_until_stop,step}): Before executing
170 instructions, make sure r0 == 0.
172 Tue May 13 16:39:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
174 * alu.h (IMEM): Take full cia not just IP as argument.
176 * interp.c (engine_run_until_stop): Delete handling of annuled
178 (engine_step): Ditto.
180 * insn (do_branch): New function.
181 (do_bbo, do_bbz, do_bcnd, do_bsr, do_jsr): Use do_branch to handle
184 Mon May 12 17:15:52 1997 Mike Meissner <meissner@cygnus.com>
186 * insns (do_{ld,st}): Fix tracing for ld/st.
188 Mon May 12 11:12:24 1997 Andrew Cagney <cagney@b1.cygnus.com>
190 * sim-calls.c (sim_stop_reason): Restore keep_running after a
191 CNTRL-C, don't re-clear it.
193 * interp.c (engine_error): stop rather than signal with SIGABRT
196 * insns (do_ld): For 64bit loads, always store LSW in rDest, MSW in
197 rDest + 1. Also done by Michael Meissner <meissner@cygnus.com>
198 (do_st): Converse for store.
200 * misc.c (tic80_trace_fpu2i): Correct printf format for int type.
202 Sun May 11 11:02:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
204 * sim-calls.c (sim_stop_reason): Return a SIGINT if keep_running
207 * interp.c (engine_step): New function. Single step the simulator
208 taking care of cntrl-c during a step.
210 * sim-calls.c (sim_resume): Differentiate between stepping and
211 running so that a cntrl-c during a step is reported.
213 Sun May 11 10:54:31 1997 Mark Alexander <marka@cygnus.com>
215 * sim-calls.c (sim_fetch_register): Use correct reg base.
216 (sim_store_register): Ditto.
218 Sun May 11 10:25:14 1997 Michael Meissner <meissner@cygnus.com>
220 * cpu.h (tic80_trace_shift): Add declaration.
221 (TRACE_SHIFT): New macro to trace shift instructions.
223 * misc.c (tic80_trace_alu2): Align spacing.
224 (tic80_trace_shift): New function to trace shifts.
226 * insns (lmo): Add missing 0b prefix to bits.
227 (do_shift): Use ~ (unsigned32)0, instead of -1. Use TRACE_SHIFT
228 instead of TRACE_ALU2.
229 (sl r): Use EndMask as is, instead of using Source+1 register.
230 (subu): Operands are unsigned, not signed.
231 (do_{ld,st}): Fix endian problems with ld.d/st.d.
233 Sat May 10 12:35:47 1997 Michael Meissner <meissner@cygnus.com>
235 * insns (and{.tt,.tf,.ft,.ff}): Immediate values are unsigned, not
238 Fri May 9 15:47:36 1997 Mike Meissner <meissner@cygnus.com>
240 * insns (cmp_vals,do_cmp): Produce the correct bits as specified
242 (xor): Fix xor immediate patterns to use the correct bits.
244 Fri May 9 09:55:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
246 * alu.h (long_immediate): Adjust the CIA delay-pointer as well as
247 the NIA when a 64bit insn.
249 Thu May 8 11:57:47 1997 Michael Meissner <meissner@cygnus.com>
251 * insns (jsr,bsr): For non-allulled calls, set r31 so that the
252 return address does not reexecute the instruction in the delay
254 (bbo,bbz): Complement bit number to reverse the one's complement
255 that the assembler is required to do.
257 * misc.c (tic80_trace_*): Change format slightly to accomidate
258 real large decimal values.
260 Thu May 8 14:07:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
262 * sim-calls.c (sim_do_command): Implement.
263 (sim_store_register): Fix typo T2H v H2T.
265 Wed May 7 11:48:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
267 * cpu.h (TRACE_FPU2, TRACE_FPU3, TRACE_FPU2I): Add.
268 * insn: Clean up fpu tracing.
270 * sim-calls.c (sim_create_inferior): Start out with interrupts
273 * cpu.h (TRACE_SINK3), misc.c (tic80_trace_sink3): Three argument
276 * insns (rdcr, swcr, wrcr, brcr, rmo, lmo): Implement.
278 * insns (do_*): Remove MY_INDEX/indx argument from support functions,
279 igen now handles this.
281 * cpu.h (CR): New macro - access TIc80 control registers.
284 (tic80_cr2index): New function, map control register opcode index
285 into the internal CR enum.
288 (tic80_trace_{alu{2,3},nop,sink{1,2},{,u}cond_br,ldst}): Move from
292 * Makefile.in (SIM_OBJS): Add misc.o.
294 Tue May 6 15:22:58 1997 Mike Meissner <meissner@cygnus.com>
296 * cpu.h ({,v}{S,D}P_FPR): Delete unused macros that won't work on
298 (tic80_trace_{alu{2,3},nop,sink{1,2},{,u}cond_br,ldst}): Declare
300 (TRACE_{ALU{2,3},NOP,SINK{1,2},{,U}COND_BR,LD,ST}): New macros to
301 trace various instruction types.
303 * insns: Modify all instructions to support semantic tracing.
305 * interp.c (toplevel): Include itable.h.
306 (tic80_trace_{alu{2,3},nop,sink{1,2},{,u}cond_br,ldst}): New
307 functions to provide semantic level tracing information.
309 Mon May 5 11:50:43 1997 Andrew Cagney <cagney@b1.cygnus.com>
311 * alu.h: Update usage of core object to reflect recent changes in
313 * sim-calls.c (sim_open): Ditto.
315 Mon May 5 14:10:17 1997 Andrew Cagney <cagney@b1.cygnus.com>
317 * insn (cmnd): No-op cache flushes.
319 * insns (do_trap): Allow writes to STDERR.
321 * Makefile.in (SIM_OBJS): Link in sim-fpu.o.
322 (SIM_EXTRA_LIBS): Link in the math library.
324 * alu.h: Add support for floating point unit using sim-alu.
326 * insns (fadd, fsub, fmpy, fdiv, fcmp, frnd*): Implement.
328 Fri May 2 14:57:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
330 * sim-calls.c: Include sim-utils.h and sim-options.h.
332 * sim-main.h (sim_state): Drop sim_events and sim_core members,
333 moved to simulator base type.
335 * alu.h (IMEM, MEM, STORE): Update track changes in common
338 * insns: Drop cia argument from functions, igen now handles this.
340 * interp.c (engine_init): Include string.h/strings.h to define
343 * sim-main.h (sim_cia): Delcare, tracking common dir changes.
345 * cpu.h (sim_cpu): Update instruction_address with sim_cia.
347 Wed Apr 30 11:26:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
349 * sim-main.h (signal.h): Include so that SIG* available to all
352 * insns (do_shift): New function, implement shift operations.
353 (do_trap): Add handler for trap 73 - SIGTRAP.
355 Tue Apr 29 10:58:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
357 * alu.h (MEM, STORE): Force addresses to be correctly aligned.
359 * insns (do_jsr): Fix.
360 (do_st, do_ld): Handle 64bit transfers.
361 (do_trap): Match libgloss.
362 (rdcr): Implement nop - Dest == r0 - variant.
364 * sim-calls.c (sim_create_inferior): Initialize SP.
366 * Makefile.in (ENGINE_H): Everything now depends on sim-options.h.
367 (support.o): Depends on ENGINE_H.
369 * cpu.h: Four accumulators.
371 * Makefile.in (tmp-igen): Include line number information in
374 * insns (dld, dst): Fill in.
376 Mon Apr 28 13:02:26 1997 Andrew Cagney <cagney@b1.cygnus.com>
378 * insns (vld): Fix instruction format wrong.
380 Thu Apr 24 16:43:09 1997 Andrew Cagney <cagney@b1.cygnus.com>
382 * dc: Add additional rules so that minor opcode files are
384 * insns: Enable more instructions.
386 * sim-calls.c (sim_fetch_register,sim_store_register, sim_write):
389 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
391 * configure: Regenerated to track ../common/aclocal.m4 changes.
392 * Makefile.in (SIM_OBJS): Add sim-module.o, sim-profile.o.
393 * sim-calls.c (sim_open): Call sim_module_uninstall if argument
394 parsing fails. Call sim_post_argv_init.
395 (sim_close): Call sim_module_uninstall.
397 Wed Apr 23 20:05:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
399 * insns (and, bbo, bcnd, bsr, dcache, jsr, or, xor, nor): Enable.
400 * ic: Add fields for enabled instructions.