sim/tic80/ChangeLog

   1 Wed May 14 18:05:50 1997  Mike Meissner  <meissner@cygnus.com>
   2
   3         * misc.c (tic80_trace_fpu{3,2,2i}): Align columns with other
   4         insns.  Use %g to print floating point instead of %f in case the
   5         numbers are real large.
   6
   7 Tue May 13 18:00:10 1997  Mike Meissner  <meissner@cygnus.com>
   8
   9         * insns (do_trap): For system calls that are defined, but not
  10         provided return EINVAL. Temporarily add traps 74-79 to just print
  11         the register state.
  12
  13         * interp.c (engine_{run_until_stop,step}): Before executing
  14         instructions, make sure r0 == 0.
  15
  16 Tue May 13 16:39:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
  17
  18         * alu.h (IMEM): Take full cia not just IP as argument.
  19
  20         * interp.c (engine_run_until_stop): Delete handling of annuled
  21         instructions.
  22         (engine_step): Ditto.
  23
  24         * insn (do_branch): New function.
  25         (do_bbo, do_bbz, do_bcnd, do_bsr, do_jsr): Use do_branch to handle
  26         annuled branches.
  27
  28 Mon May 12 17:15:52 1997  Mike Meissner  <meissner@cygnus.com>
  29
  30         * insns (do_{ld,st}): Fix tracing for ld/st.
  31
  32 Mon May 12 11:12:24 1997  Andrew Cagney  <cagney@b1.cygnus.com>
  33
  34         * sim-calls.c (sim_stop_reason): Restore keep_running after a
  35         CNTRL-C, don't re-clear it.
  36
  37         * interp.c (engine_error): stop rather than signal with SIGABRT
  38         when an error.
  39
  40         * insns (do_ld): For 64bit loads, always store LSW in rDest, MSW in
  41         rDest + 1. Also done by Michael Meissner  <meissner@cygnus.com>
  42         (do_st): Converse for store.
  43
  44         * misc.c (tic80_trace_fpu2i): Correct printf format for int type.
  45
  46 Sun May 11 11:02:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
  47
  48         * sim-calls.c (sim_stop_reason): Return a SIGINT if keep_running
  49         was cleared.
  50
  51         * interp.c (engine_step): New function.  Single step the simulator
  52         taking care of cntrl-c during a step.
  53
  54         * sim-calls.c (sim_resume): Differentiate between stepping and
  55         running so that a cntrl-c during a step is reported.
  56
  57 Sun May 11 10:54:31 1997  Mark Alexander    <marka@cygnus.com>
  58
  59         * sim-calls.c (sim_fetch_register): Use correct reg base.
  60         (sim_store_register): Ditto.
  61
  62 Sun May 11 10:25:14 1997  Michael Meissner  <meissner@cygnus.com>
  63
  64         * cpu.h (tic80_trace_shift): Add declaration.
  65         (TRACE_SHIFT): New macro to trace shift instructions.
  66
  67         * misc.c (tic80_trace_alu2): Align spacing.
  68         (tic80_trace_shift): New function to trace shifts.
  69
  70         * insns (lmo): Add missing 0b prefix to bits.
  71         (do_shift): Use ~ (unsigned32)0, instead of -1.  Use TRACE_SHIFT
  72         instead of TRACE_ALU2.
  73         (sl r): Use EndMask as is, instead of using Source+1 register.
  74         (subu): Operands are unsigned, not signed.
  75         (do_{ld,st}): Fix endian problems with ld.d/st.d.
  76
  77 Sat May 10 12:35:47 1997  Michael Meissner  <meissner@cygnus.com>
  78
  79         * insns (and{.tt,.tf,.ft,.ff}): Immediate values are unsigned, not
  80         signed.
  81
  82 Fri May  9 15:47:36 1997  Mike Meissner  <meissner@cygnus.com>
  83
  84         * insns (cmp_vals,do_cmp): Produce the correct bits as specified
  85         by the architecture.
  86         (xor): Fix xor immediate patterns to use the correct bits.
  87
  88 Fri May  9 09:55:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
  89
  90         * alu.h (long_immediate): Adjust the CIA delay-pointer as well as
  91         the NIA when a 64bit insn.
  92
  93 Thu May  8 11:57:47 1997  Michael Meissner  <meissner@cygnus.com>
  94
  95         * insns (jsr,bsr): For non-allulled calls, set r31 so that the
  96         return address does not reexecute the instruction in the delay
  97         slot.
  98         (bbo,bbz): Complement bit number to reverse the one's complement
  99         that the assembler is required to do.
 100
 101         * misc.c (tic80_trace_*): Change format slightly to accomidate
 102         real large decimal values.
 103
 104 Thu May  8 14:07:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 105
 106         * sim-calls.c (sim_do_command): Implement.
 107         (sim_store_register): Fix typo T2H v H2T.
 108
 109 Wed May  7 11:48:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 110
 111         * cpu.h (TRACE_FPU2, TRACE_FPU3, TRACE_FPU2I): Add.
 112         * insn: Clean up fpu tracing.
 113
 114         * sim-calls.c (sim_create_inferior): Start out with interrupts
 115         enabled.
 116
 117         * cpu.h (TRACE_SINK3), misc.c (tic80_trace_sink3): Three argument
 118         sink
 119
 120         * insns (rdcr, swcr, wrcr, brcr, rmo, lmo): Implement.
 121
 122         * insns (do_*): Remove MY_INDEX/indx argument from support functions,
 123         igen now handles this.
 124
 125         * cpu.h (CR): New macro - access TIc80 control registers.
 126
 127         * misc.c: New file.
 128         (tic80_cr2index): New function, map control register opcode index
 129         into the internal CR enum.
 130
 131         * interp.c
 132         (tic80_trace_{alu{2,3},nop,sink{1,2},{,u}cond_br,ldst}): Move from
 133         here
 134         * misc.c: to here.
 135
 136         * Makefile.in (SIM_OBJS): Add misc.o.
 137
 138 Tue May  6 15:22:58 1997  Mike Meissner  <meissner@cygnus.com>
 139
 140         * cpu.h ({,v}{S,D}P_FPR): Delete unused macros that won't work on
 141         big endian hosts.
 142         (tic80_trace_{alu{2,3},nop,sink{1,2},{,u}cond_br,ldst}): Declare
 143         new functions.
 144         (TRACE_{ALU{2,3},NOP,SINK{1,2},{,U}COND_BR,LD,ST}): New macros to
 145         trace various instruction types.
 146
 147         * insns: Modify all instructions to support semantic tracing.
 148
 149         * interp.c (toplevel): Include itable.h.
 150         (tic80_trace_{alu{2,3},nop,sink{1,2},{,u}cond_br,ldst}): New
 151         functions to provide semantic level tracing information.
 152
 153 Mon May  5 11:50:43 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 154
 155         * alu.h: Update usage of core object to reflect recent changes in
 156         ../common/sim-*core.
 157         * sim-calls.c (sim_open): Ditto.
 158
 159 Mon May  5 14:10:17 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 160
 161         * insn (cmnd): No-op cache flushes.
 162
 163         * insns (do_trap): Allow writes to STDERR.
 164
 165         * Makefile.in (SIM_OBJS): Link in sim-fpu.o.
 166         (SIM_EXTRA_LIBS): Link in the math library.
 167
 168         * alu.h: Add support for floating point unit using sim-alu.
 169
 170         * insns (fadd, fsub, fmpy, fdiv, fcmp, frnd*): Implement.
 171
 172 Fri May  2 14:57:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 173
 174         * sim-calls.c: Include sim-utils.h and sim-options.h.
 175
 176         * sim-main.h (sim_state): Drop sim_events and sim_core members,
 177         moved to simulator base type.
 178
 179         * alu.h (IMEM, MEM, STORE): Update track changes in common
 180         directory.
 181
 182         * insns: Drop cia argument from functions, igen now handles this.
 183
 184         * interp.c (engine_init): Include string.h/strings.h to define
 185         memset et.al.
 186
 187         * sim-main.h (sim_cia): Delcare, tracking common dir changes.
 188
 189         * cpu.h (sim_cpu): Update instruction_address with sim_cia.
 190
 191 Wed Apr 30 11:26:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 192
 193         * sim-main.h (signal.h): Include so that SIG* available to all
 194         callers of sig_halt.
 195
 196         * insns (do_shift): New function, implement shift operations.
 197         (do_trap): Add handler for trap 73 - SIGTRAP.
 198
 199 Tue Apr 29 10:58:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 200
 201         * alu.h (MEM, STORE): Force addresses to be correctly aligned.
 202
 203         * insns (do_jsr): Fix.
 204         (do_st, do_ld): Handle 64bit transfers.
 205         (do_trap): Match libgloss.
 206         (rdcr): Implement nop - Dest == r0 - variant.
 207
 208         * sim-calls.c (sim_create_inferior): Initialize SP.
 209
 210         * Makefile.in (ENGINE_H): Everything now depends on sim-options.h.
 211         (support.o): Depends on ENGINE_H.
 212
 213         * cpu.h: Four accumulators.
 214
 215         * Makefile.in (tmp-igen): Include line number information in
 216         generated files.
 217
 218         * insns (dld, dst): Fill in.
 219
 220 Mon Apr 28 13:02:26 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 221
 222         * insns (vld): Fix instruction format wrong.
 223
 224 Thu Apr 24 16:43:09 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 225
 226         * dc: Add additional rules so that minor opcode files are
 227         detected.
 228         * insns: Enable more instructions.
 229
 230         * sim-calls.c (sim_fetch_register,sim_store_register, sim_write):
 231         Implement.
 232
 233 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
 234
 235         * configure: Regenerated to track ../common/aclocal.m4 changes.
 236         * Makefile.in (SIM_OBJS): Add sim-module.o, sim-profile.o.
 237         * sim-calls.c (sim_open): Call sim_module_uninstall if argument
 238         parsing fails.  Call sim_post_argv_init.
 239         (sim_close): Call sim_module_uninstall.
 240
 241 Wed Apr 23 20:05:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 242
 243         * insns (and, bbo, bcnd, bsr, dcache, jsr, or, xor, nor): Enable.
 244         * ic: Add fields for enabled instructions.
 245