sim/tic80/ChangeLog

   1 Mon May 12 11:12:24 1997  Andrew Cagney  <cagney@b1.cygnus.com>
   2
   3         * insns (do_ld): For 64bit loads, always store LSW in rDest, MSW in
   4         rDest + 1. Also done by Michael Meissner  <meissner@cygnus.com>
   5         (do_st): Converse for store.
   6
   7         * misc.c (tic80_trace_fpu2i): Correct printf format for int type.
   8
   9 Sun May 11 11:02:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
  10
  11         * sim-calls.c (sim_stop_reason): Return a SIGINT if keep_running
  12         was cleared.
  13
  14         * interp.c (engine_step): New function.  Single step the simulator
  15         taking care of cntrl-c during a step.
  16
  17         * sim-calls.c (sim_resume): Differentiate between stepping and
  18         running so that a cntrl-c during a step is reported.
  19
  20 Sun May 11 10:54:31 1997  Mark Alexander    <marka@cygnus.com>
  21
  22         * sim-calls.c (sim_fetch_register): Use correct reg base.
  23         (sim_store_register): Ditto.
  24
  25 Sun May 11 10:25:14 1997  Michael Meissner  <meissner@cygnus.com>
  26
  27         * cpu.h (tic80_trace_shift): Add declaration.
  28         (TRACE_SHIFT): New macro to trace shift instructions.
  29
  30         * misc.c (tic80_trace_alu2): Align spacing.
  31         (tic80_trace_shift): New function to trace shifts.
  32
  33         * insns (lmo): Add missing 0b prefix to bits.
  34         (do_shift): Use ~ (unsigned32)0, instead of -1.  Use TRACE_SHIFT
  35         instead of TRACE_ALU2.
  36         (sl r): Use EndMask as is, instead of using Source+1 register.
  37         (subu): Operands are unsigned, not signed.
  38         (do_{ld,st}): Fix endian problems with ld.d/st.d.
  39
  40 Sat May 10 12:35:47 1997  Michael Meissner  <meissner@cygnus.com>
  41
  42         * insns (and{.tt,.tf,.ft,.ff}): Immediate values are unsigned, not
  43         signed.
  44
  45 Fri May  9 15:47:36 1997  Mike Meissner  <meissner@cygnus.com>
  46
  47         * insns (cmp_vals,do_cmp): Produce the correct bits as specified
  48         by the architecture.
  49         (xor): Fix xor immediate patterns to use the correct bits.
  50
  51 Fri May  9 09:55:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
  52
  53         * alu.h (long_immediate): Adjust the CIA delay-pointer as well as
  54         the NIA when a 64bit insn.
  55
  56 Thu May  8 11:57:47 1997  Michael Meissner  <meissner@cygnus.com>
  57
  58         * insns (jsr,bsr): For non-allulled calls, set r31 so that the
  59         return address does not reexecute the instruction in the delay
  60         slot.
  61         (bbo,bbz): Complement bit number to reverse the one's complement
  62         that the assembler is required to do.
  63
  64         * misc.c (tic80_trace_*): Change format slightly to accomidate
  65         real large decimal values.
  66
  67 Thu May  8 14:07:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
  68
  69         * sim-calls.c (sim_do_command): Implement.
  70         (sim_store_register): Fix typo T2H v H2T.
  71
  72 Wed May  7 11:48:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
  73
  74         * cpu.h (TRACE_FPU2, TRACE_FPU3, TRACE_FPU2I): Add.
  75         * insn: Clean up fpu tracing.
  76
  77         * sim-calls.c (sim_create_inferior): Start out with interrupts
  78         enabled.
  79
  80         * cpu.h (TRACE_SINK3), misc.c (tic80_trace_sink3): Three argument
  81         sink
  82
  83         * insns (rdcr, swcr, wrcr, brcr, rmo, lmo): Implement.
  84
  85         * insns (do_*): Remove MY_INDEX/indx argument from support functions,
  86         igen now handles this.
  87
  88         * cpu.h (CR): New macro - access TIc80 control registers.
  89
  90         * misc.c: New file.
  91         (tic80_cr2index): New function, map control register opcode index
  92         into the internal CR enum.
  93
  94         * interp.c
  95         (tic80_trace_{alu{2,3},nop,sink{1,2},{,u}cond_br,ldst}): Move from
  96         here
  97         * misc.c: to here.
  98
  99         * Makefile.in (SIM_OBJS): Add misc.o.
 100
 101 Tue May  6 15:22:58 1997  Mike Meissner  <meissner@cygnus.com>
 102
 103         * cpu.h ({,v}{S,D}P_FPR): Delete unused macros that won't work on
 104         big endian hosts.
 105         (tic80_trace_{alu{2,3},nop,sink{1,2},{,u}cond_br,ldst}): Declare
 106         new functions.
 107         (TRACE_{ALU{2,3},NOP,SINK{1,2},{,U}COND_BR,LD,ST}): New macros to
 108         trace various instruction types.
 109
 110         * insns: Modify all instructions to support semantic tracing.
 111
 112         * interp.c (toplevel): Include itable.h.
 113         (tic80_trace_{alu{2,3},nop,sink{1,2},{,u}cond_br,ldst}): New
 114         functions to provide semantic level tracing information.
 115
 116 Mon May  5 11:50:43 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 117
 118         * alu.h: Update usage of core object to reflect recent changes in
 119         ../common/sim-*core.
 120         * sim-calls.c (sim_open): Ditto.
 121
 122 Mon May  5 14:10:17 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 123
 124         * insn (cmnd): No-op cache flushes.
 125
 126         * insns (do_trap): Allow writes to STDERR.
 127
 128         * Makefile.in (SIM_OBJS): Link in sim-fpu.o.
 129         (SIM_EXTRA_LIBS): Link in the math library.
 130
 131         * alu.h: Add support for floating point unit using sim-alu.
 132
 133         * insns (fadd, fsub, fmpy, fdiv, fcmp, frnd*): Implement.
 134
 135 Fri May  2 14:57:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 136
 137         * sim-calls.c: Include sim-utils.h and sim-options.h.
 138
 139         * sim-main.h (sim_state): Drop sim_events and sim_core members,
 140         moved to simulator base type.
 141
 142         * alu.h (IMEM, MEM, STORE): Update track changes in common
 143         directory.
 144
 145         * insns: Drop cia argument from functions, igen now handles this.
 146
 147         * interp.c (engine_init): Include string.h/strings.h to define
 148         memset et.al.
 149
 150         * sim-main.h (sim_cia): Delcare, tracking common dir changes.
 151
 152         * cpu.h (sim_cpu): Update instruction_address with sim_cia.
 153
 154 Wed Apr 30 11:26:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 155
 156         * sim-main.h (signal.h): Include so that SIG* available to all
 157         callers of sig_halt.
 158
 159         * insns (do_shift): New function, implement shift operations.
 160         (do_trap): Add handler for trap 73 - SIGTRAP.
 161
 162 Tue Apr 29 10:58:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 163
 164         * alu.h (MEM, STORE): Force addresses to be correctly aligned.
 165
 166         * insns (do_jsr): Fix.
 167         (do_st, do_ld): Handle 64bit transfers.
 168         (do_trap): Match libgloss.
 169         (rdcr): Implement nop - Dest == r0 - variant.
 170
 171         * sim-calls.c (sim_create_inferior): Initialize SP.
 172
 173         * Makefile.in (ENGINE_H): Everything now depends on sim-options.h.
 174         (support.o): Depends on ENGINE_H.
 175
 176         * cpu.h: Four accumulators.
 177
 178         * Makefile.in (tmp-igen): Include line number information in
 179         generated files.
 180
 181         * insns (dld, dst): Fill in.
 182
 183 Mon Apr 28 13:02:26 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 184
 185         * insns (vld): Fix instruction format wrong.
 186
 187 Thu Apr 24 16:43:09 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 188
 189         * dc: Add additional rules so that minor opcode files are
 190         detected.
 191         * insns: Enable more instructions.
 192
 193         * sim-calls.c (sim_fetch_register,sim_store_register, sim_write):
 194         Implement.
 195
 196 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
 197
 198         * configure: Regenerated to track ../common/aclocal.m4 changes.
 199         * Makefile.in (SIM_OBJS): Add sim-module.o, sim-profile.o.
 200         * sim-calls.c (sim_open): Call sim_module_uninstall if argument
 201         parsing fails.  Call sim_post_argv_init.
 202         (sim_close): Call sim_module_uninstall.
 203
 204 Wed Apr 23 20:05:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 205
 206         * insns (and, bbo, bcnd, bsr, dcache, jsr, or, xor, nor): Enable.
 207         * ic: Add fields for enabled instructions.
 208