2 Copyright (C) 1997, 1998 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23 /* TI C80 control registers */
98 nr_tic80_control_regs
,
101 /* extern int tic80_cr2index (tic80_control_regs reg); */
103 /* Map an instruction CR index onto the corresponding internal cr enum
104 or SCRATCH_CR if the index is invalid */
106 extern tic80_control_regs
tic80_index2cr (int index
);
109 /* TIc80 interrupt register bits */
112 IE_CR_PE
= BIT32(31),
113 IE_CR_X4
= BIT32(30),
114 IE_CR_X3
= BIT32(29),
115 IE_CR_BP
= BIT32(28),
116 IE_CR_PB
= BIT32(27),
117 IE_CR_PC
= BIT32(26),
118 IE_CR_MI
= BIT32(25),
120 IE_CR_P3
= BIT32(19),
121 IE_CR_P2
= BIT32(18),
122 IE_CR_P1
= BIT32(17),
123 IE_CR_P0
= BIT32(16),
124 IE_CR_IO
= BIT32(15),
125 IE_CR_MF
= BIT32(14),
127 IE_CR_X2
= BIT32(12),
128 IE_CR_X1
= BIT32(11),
129 IE_CR_TI
= BIT32(10),
148 unsigned32 cr
[nr_tic80_control_regs
];
149 int is_user_mode
; /* hidden mode latch */
154 #define CIA_GET(CPU) ((CPU)->cia)
155 #define CIA_SET(CPU,VAL) ((CPU)->cia = (VAL))
157 #define GPR(N) ((CPU)->reg[N])
158 #define GPR_CLEAR(N) (GPR((N)) = 0)
159 #define ACC(N) ((CPU)->acc[N])
160 #define CR(N) ((CPU)->cr[tic80_index2cr ((N))])
164 #if defined(WITH_TRACE)
165 extern char *tic80_trace_alu3
PARAMS ((int, unsigned32
, unsigned32
, unsigned32
));
166 extern char *tic80_trace_cmp
PARAMS ((int, unsigned32
, unsigned32
, unsigned32
));
167 extern char *tic80_trace_alu2
PARAMS ((int, unsigned32
, unsigned32
));
168 extern char *tic80_trace_shift
PARAMS ((int, unsigned32
, unsigned32
, int, int, int, int, int));
169 extern void tic80_trace_fpu3
PARAMS ((SIM_DESC
, sim_cpu
*, sim_cia
, int, sim_fpu
*, sim_fpu
*, sim_fpu
*));
170 extern void tic80_trace_fpu2
PARAMS ((SIM_DESC
, sim_cpu
*, sim_cia
, int, sim_fpu
*, sim_fpu
*));
171 extern void tic80_trace_fpu1
PARAMS ((SIM_DESC
, sim_cpu
*, sim_cia
, int, sim_fpu
*));
172 extern void tic80_trace_fpu2i
PARAMS ((SIM_DESC
, sim_cpu
*, sim_cia
, int, unsigned32
, sim_fpu
*, sim_fpu
*));
173 extern void tic80_trace_fpu2cmp
PARAMS ((SIM_DESC
, sim_cpu
*, sim_cia
, int, unsigned32
, sim_fpu
*, sim_fpu
*));
174 extern char *tic80_trace_nop
PARAMS ((int));
175 extern char *tic80_trace_sink1
PARAMS ((int, unsigned32
));
176 extern char *tic80_trace_sink2
PARAMS ((int, unsigned32
, unsigned32
));
177 extern char *tic80_trace_sink3
PARAMS ((int, unsigned32
, unsigned32
, unsigned32
));
178 extern char *tic80_trace_cond_br
PARAMS ((int, int, unsigned32
, unsigned32
, int, int));
179 extern char *tic80_trace_ucond_br
PARAMS ((int, unsigned32
));
180 extern void tic80_trace_ldst
PARAMS ((SIM_DESC
, sim_cpu
*, sim_cia
, int, int, int, int, unsigned32
, unsigned32
, unsigned32
));
182 #define TRACE_ALU3(indx, result, input1, input2) \
184 if (TRACE_ALU_P (CPU)) { \
185 trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
186 itable[indx].line_nr, "alu", \
187 tic80_trace_alu3 (indx, result, input1, input2)); \
191 #define TRACE_CMP(indx, result, input1, input2) \
193 if (TRACE_ALU_P (CPU)) { \
194 trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
195 itable[indx].line_nr, "alu", \
196 tic80_trace_cmp (indx, result, input1, input2)); \
200 #define TRACE_ALU2(indx, result, input) \
202 if (TRACE_ALU_P (CPU)) { \
203 trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
204 itable[indx].line_nr, "alu", \
205 tic80_trace_alu2 (indx, result, input)); \
209 #define TRACE_SHIFT(indx, result, input, i, n, merge, endmask, rotate) \
211 if (TRACE_ALU_P (CPU)) { \
212 trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
213 itable[indx].line_nr, "shift", \
214 tic80_trace_shift (indx, result, input, i, n, \
215 merge, endmask, rotate)); \
219 #define TRACE_FPU3(result, input1, input2) \
221 if (TRACE_FPU_P (CPU)) { \
222 tic80_trace_fpu3 (SD, CPU, cia, MY_INDEX, \
223 &result, &input1, &input2); \
227 #define TRACE_FPU2(result, input) \
229 if (TRACE_FPU_P (CPU)) { \
230 tic80_trace_fpu2 (SD, CPU, cia, MY_INDEX, \
235 #define TRACE_FPU1(result) \
237 if (TRACE_FPU_P (CPU)) { \
238 tic80_trace_fpu1 (SD, CPU, cia, MY_INDEX, \
243 #define TRACE_FPU2I(result, input1, input2) \
245 if (TRACE_FPU_P (CPU)) { \
246 tic80_trace_fpu2i (SD, CPU, cia, MY_INDEX, \
247 result, &input1, &input2); \
251 #define TRACE_FPU2CMP(result, input1, input2) \
253 if (TRACE_FPU_P (CPU)) { \
254 tic80_trace_fpu2cmp (SD, CPU, cia, MY_INDEX, \
255 result, &input1, &input2); \
259 #define TRACE_NOP(indx) \
261 if (TRACE_ALU_P (CPU)) { \
262 trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
263 itable[indx].line_nr, "nop", \
264 tic80_trace_nop (indx)); \
268 #define TRACE_SINK1(indx, input) \
270 if (TRACE_ALU_P (CPU)) { \
271 trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
272 itable[indx].line_nr, "nop", \
273 tic80_trace_sink1 (indx, input)); \
277 #define TRACE_SINK2(indx, input1, input2) \
279 if (TRACE_ALU_P (CPU)) { \
280 trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
281 itable[indx].line_nr, "nop", \
282 tic80_trace_sink2 (indx, input1, input2)); \
286 #define TRACE_SINK3(indx, input1, input2, input3) \
288 if (TRACE_ALU_P (CPU)) { \
289 trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
290 itable[indx].line_nr, "nop", \
291 tic80_trace_sink3 (indx, input1, input2, input3)); \
295 #define TRACE_COND_BR(indx, jump_p, cond, target, size, code) \
297 if (TRACE_BRANCH_P (CPU)) { \
298 trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
299 itable[indx].line_nr, "branch", \
300 tic80_trace_cond_br (indx, jump_p, cond, target, \
305 #define TRACE_UCOND_BR(indx, target) \
307 if (TRACE_BRANCH_P (CPU)) { \
308 trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
309 itable[indx].line_nr, "branch", \
310 tic80_trace_ucond_br (indx, target)); \
314 #define TRACE_LD(result, m, s, addr1, addr2) \
316 if (TRACE_MEMORY_P (CPU)) { \
317 tic80_trace_ldst (SD, CPU, cia, MY_INDEX, \
318 0, m, s, result, addr1, addr2); \
322 #define TRACE_ST(value, m, s, addr1, addr2) \
324 if (TRACE_MEMORY_P (CPU)) { \
325 tic80_trace_ldst (SD, CPU, cia, MY_INDEX, \
326 1, m, s, value, addr1, addr2); \
331 #define TRACE_ALU3(indx, result, input1, input2)
332 #define TRACE_ALU2(indx, result, input)
333 #define TRACE_FPU3(result, input1, input2)
334 #define TRACE_FPU2(result, input)
335 #define TRACE_FPU1(result)
336 #define TRACE_FPU2I(result, input1, input2)
337 #define TRACE_NOP(indx)
338 #define TRACE_SINK1(indx, input)
339 #define TRACE_SINK2(indx, input1, input2)
340 #define TRACE_SINK3(indx, input1, input2, input3)
341 #define TRACE_COND_BR(indx, jump_p, cond, target, size, code)
342 #define TRACE_UCOND_BR(indx, target)
343 #define TRACE_LD(m, s, result, addr1, addr2)
344 #define TRACE_ST(m, s, value, addr1, addr2)
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