sim/tic80/insns

   1 // Texas Instruments TMS320C80 (MVP) Simulator.
   2 // Copyright (C) 1997 Free Software Foundation, Inc.
   3 // Contributed by Cygnus Support.
   4 //
   5 // This file is part of GDB, the GNU debugger.
   6 //
   7 // This program is free software; you can redistribute it and/or modify
   8 // it under the terms of the GNU General Public License as published by
   9 // the Free Software Foundation; either version 2, or (at your option)
  10 // any later version.
  11 //
  12 // This program is distributed in the hope that it will be useful,
  13 // but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 // GNU General Public License for more details.
  16 //
  17 // You should have received a copy of the GNU General Public License along
  18 // with this program; if not, write to the Free Software Foundation, Inc.,
  19 // 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21
  22 // The following is called when ever an illegal instruction is encountered.
  23 ::internal::illegal
  24         engine_error (SD, CPU, cia,
  25                       "illegal instruction at 0x%lx", cia.ip);
  26 // The following is called when ever an FP op is attempted with FPU disabled.
  27 ::internal::fp_unavailable
  28         engine_error (SD, CPU, cia,
  29                       "floating-point unavailable at 0x%lx", cia.ip);
  30
  31 // Handle a branch instruction
  32 instruction_address::function::do_branch:int annul, address_word target, int rLink_p, unsigned32 *rLink
  33         instruction_address nia;
  34         if (annul)
  35           {
  36             if (rLink_p)
  37               *rLink = cia.dp;
  38             nia.ip = target;
  39             nia.dp = target + 4;
  40           }
  41         else
  42           {
  43             if (rLink_p)
  44               *rLink = cia.dp + sizeof (instruction_word);
  45             nia.ip = cia.dp;
  46             nia.dp = target;
  47           }
  48         return nia;
  49
  50 // Signed Integer Add - add source1, source2, dest
  51 void::function::do_add:signed32 *rDest, signed32 Source1, signed32 Source2
  52         ALU_BEGIN (Source1);
  53         ALU_ADD (Source2);
  54         ALU_END (*rDest);
  55         TRACE_ALU3 (MY_INDEX, *rDest, Source1, Source2);
  56         /* FIXME - a signed add may cause an exception */
  57 31.Dest,26.Source2,21.0b101100,15.0,14.SignedImmediate::::add i
  58         do_add (_SD, rDest, vSource1, rSource2);
  59 31.Dest,26.Source2,21.0b11101100,13.0,12.0,11./,4.Source1::::add r
  60         do_add (_SD, rDest, rSource1, rSource2);
  61 31.Dest,26.Source2,21.0b11101100,13.0,12.1,11./::::add l
  62         long_immediate (LongSignedImmediate);
  63         do_add (_SD, rDest, LongSignedImmediate, rSource2);
  64
  65
  66 // Unsigned Integer Add - addu source1, source2, dest
  67 void::function::do_addu:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
  68         unsigned32 result = Source1 + Source2;
  69         TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
  70         *rDest = result;
  71
  72 31.Dest,26.Source2,21.0b101100,15.1,14.SignedImmediate::::addu i
  73         do_addu (_SD, rDest, vSource1, rSource2);
  74 31.Dest,26.Source2,21.0b11101100,13.1,12.0,11./,4.Source1::::addu r
  75         do_addu (_SD, rDest, rSource1, rSource2);
  76 31.Dest,26.Source2,21.0b11101100,13.1,12.1,11./::::addu l
  77         long_immediate (LongSignedImmediate);
  78         do_addu (_SD, rDest, LongSignedImmediate, rSource2);
  79
  80
  81 void::function::do_and:signed32 *rDest, signed32 Source1, signed32 Source2
  82         unsigned32 result = Source1 & Source2;
  83         TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
  84         *rDest = result;
  85
  86
  87 // and, and.tt
  88 31.Dest,26.Source2,21.0b0010001,14.UnsignedImmediate::::and.tt i
  89         do_and (_SD, rDest, vSource1, rSource2);
  90 31.Dest,26.Source2,21.0b110010001,12.0,11./,4.Source1::::and.tt r
  91         do_and (_SD, rDest, rSource1, rSource2);
  92 31.Dest,26.Source2,21.0b110010001,12.1,11./::::and.tt l
  93         long_immediate (LongSignedImmediate);
  94         do_and (_SD, rDest, LongSignedImmediate, rSource2);
  95
  96
  97 // and.ff
  98 31.Dest,26.Source2,21.0b0011000,14.UnsignedImmediate::::and.ff i
  99         do_and (_SD, rDest, ~vSource1, ~rSource2);
 100 31.Dest,26.Source2,21.0b110011000,12.0,11./,4.Source1::::and.ff r
 101         do_and (_SD, rDest, ~rSource1, ~rSource2);
 102 31.Dest,26.Source2,21.0b110011000,12.1,11./::::and.ff l
 103         long_immediate (LongSignedImmediate);
 104         do_and (_SD, rDest, ~LongSignedImmediate, ~rSource2);
 105
 106
 107 // and.ft
 108 31.Dest,26.Source2,21.0b0010100,14.UnsignedImmediate::::and.ft i
 109         do_and (_SD, rDest, ~vSource1, rSource2);
 110 31.Dest,26.Source2,21.0b110010100,12.0,11./,4.Source1::::and.ft r
 111         do_and (_SD, rDest, ~rSource1, rSource2);
 112 31.Dest,26.Source2,21.0b110010100,12.1,11./::::and.ft l
 113         long_immediate (LongSignedImmediate);
 114         do_and (_SD, rDest, ~LongSignedImmediate, rSource2);
 115
 116
 117 // and.tf
 118 31.Dest,26.Source2,21.0b0010010,14.UnsignedImmediate::::and.tf i
 119         do_and (_SD, rDest, vSource1, ~rSource2);
 120 31.Dest,26.Source2,21.0b110010010,12.0,11./,4.Source1::::and.tf r
 121         do_and (_SD, rDest, rSource1, ~rSource2);
 122 31.Dest,26.Source2,21.0b110010010,12.1,11./::::and.tf l
 123         long_immediate (LongSignedImmediate);
 124         do_and (_SD, rDest, LongSignedImmediate, ~rSource2);
 125
 126
 127 // bbo.[a]
 128 instruction_address::function::do_bbo:instruction_address nia, int bitnum, unsigned32 source, int annul, unsigned32 offset
 129         int jump_p;
 130         address_word target = cia.ip + 4 * offset;
 131         bitnum = (~ bitnum) & 0x1f;
 132         if (MASKED32 (source, bitnum, bitnum))
 133           {
 134             nia = do_branch (_SD, annul, target, 0, NULL);
 135             jump_p = 1;
 136           }
 137         else
 138           jump_p = 0;
 139         TRACE_COND_BR(MY_INDEX, jump_p, bitnum, target);
 140         return nia;
 141 31.BITNUM,26.Source,21.0b100101,15.A,14.SignedOffset::::bbo i
 142         nia = do_bbo (_SD, nia, BITNUM, rSource, A, vSignedOffset);
 143 31.BITNUM,26.Source,21.0b11100101,13.A,12.0,11./,4.IndOff::::bbo r
 144         nia = do_bbo (_SD, nia, BITNUM, rSource, A, rIndOff);
 145 31.BITNUM,26.Source,21.0b11100101,13.A,12.1,11./::::bbo l
 146         long_immediate (LongSignedImmediate);
 147         nia = do_bbo (_SD, nia, BITNUM, rSource, A, LongSignedImmediate);
 148
 149
 150 // bbz[.a]
 151 instruction_address::function::do_bbz:instruction_address nia, int bitnum, unsigned32 source, int annul, unsigned32 offset
 152         int jump_p;
 153         address_word target = cia.ip + 4 * offset;
 154         bitnum = (~ bitnum) & 0x1f;
 155         if (!MASKED32 (source, bitnum, bitnum))
 156           {
 157             nia = do_branch (_SD, annul, target, 0, NULL);
 158             jump_p = 1;
 159           }
 160         else
 161           jump_p = 0;
 162         TRACE_COND_BR(MY_INDEX, jump_p, bitnum, target);
 163         return nia;
 164 31.BITNUM,26.Source,21.0b100100,15.A,14.SignedOffset::::bbz i
 165         nia = do_bbz (_SD, nia, BITNUM, rSource, A, vSignedOffset);
 166 31.BITNUM,26.Source,21.0b11100100,13.A,12.0,11./,4.IndOff::::bbz r
 167         nia = do_bbz (_SD, nia, BITNUM, rSource, A, rIndOff);
 168 31.BITNUM,26.Source,21.0b11100100,13.A,12.1,11./::::bbz l
 169         long_immediate (LongSignedImmediate);
 170         nia = do_bbz (_SD, nia, BITNUM, rSource, A, LongSignedImmediate);
 171
 172
 173 // bcnd[.a]
 174 instruction_address::function::do_bcnd:instruction_address nia, int Cond, unsigned32 source, int annul, unsigned32 offset
 175         int condition;
 176         int size = EXTRACTED32 (Cond, 31 - 27, 30 - 27);
 177         int code = EXTRACTED32 (Cond, 29 - 27, 27 - 27);
 178         signed32 val = 0;
 179         address_word target = cia.ip + 4 * offset;
 180         switch (size)
 181           {
 182           case 0: val = SEXT32 (source, 7); break;
 183           case 1: val = SEXT32 (source, 15); break;
 184           case 2: val = source; break;
 185           default: engine_error (SD, CPU, cia, "bcnd - reserved size");
 186           }
 187         switch (code)
 188           {
 189           case 0: condition = 0; break;
 190           case 1: condition = val > 0; break;
 191           case 2: condition = val == 0; break;
 192           case 3: condition = val >= 0; break;
 193           case 4: condition = val < 0; break;
 194           case 5: condition = val != 0; break;
 195           case 6: condition = val <= 0; break;
 196           default: condition = 1; break;
 197           }
 198         if (condition)
 199           {
 200             nia = do_branch (_SD, annul, target, 0, NULL);
 201           }
 202         TRACE_COND_BR(MY_INDEX, condition, source, target);
 203         return nia;
 204 31.Code,26.Source,21.0b100110,15.A,14.SignedOffset::::bcnd i
 205         nia = do_bcnd (_SD, nia, Code, rSource, A, vSignedOffset);
 206 31.Code,26.Source,21.0b11100110,13.A,12.0,11./,4.IndOff::::bcnd r
 207         nia = do_bcnd (_SD, nia, Code, rSource, A, rIndOff);
 208 31.Code,26.Source,21.0b11100110,13.A,12.1,11./::::bcnd l
 209         long_immediate (LongSignedImmediate);
 210         nia = do_bcnd (_SD, nia, Code, rSource, A, LongSignedImmediate);
 211
 212
 213 // br[.a] - see bbz[.a]
 214
 215
 216 // brcr
 217 sim_cia::function::do_brcr:instruction_address nia, int cr
 218         if (cr >= 0x4000 || !(CPU)->is_user_mode)
 219           {
 220             unsigned32 control = CR (cr);
 221             unsigned32 ie = control & 0x00000001;
 222             unsigned32 pc = control & 0xfffffffc;
 223             unsigned32 is_user_mode = control & 0x00000002;
 224             (CPU)->is_user_mode = is_user_mode;
 225             nia.dp = pc;
 226             if (ie)
 227               (CPU)->cr[IE_CR] |= IE_CR_IE;
 228             else
 229               (CPU)->cr[IE_CR] &= ~IE_CR_IE;
 230           }
 231         TRACE_UCOND_BR (MY_INDEX, nia.dp);
 232         return nia;
 233 31.//,27.0,26.//,21.0b0000110,14.UCRN::::brcr i
 234         nia = do_brcr (_SD, nia, UCRN);
 235 31.//,27.0,26.//,21.0b110000110,12.0,11./,4.INDCR::::brcr r
 236         nia = do_brcr (_SD, nia, UCRN);
 237 31.//,27.0,26.//,21.0b110000110,12.1,11./::::brcr l
 238         long_immediate (UnsignedControlRegisterNumber)
 239         nia = do_brcr (_SD, nia, UnsignedControlRegisterNumber);
 240
 241
 242 // bsr[.a]
 243 instruction_address::function::do_bsr:instruction_address nia, signed32 *rLink, int annul, unsigned32 offset
 244         address_word target = cia.ip + 4 * offset;
 245         nia = do_branch (_SD, annul, target, 1, rLink);
 246         TRACE_UCOND_BR (MY_INDEX, target);
 247         return nia;
 248 31.Link,26./,21.0b100000,15.A,14.SignedOffset::::bsr i
 249         nia = do_bsr (_SD, nia, rLink, A, vSignedOffset);
 250 31.Link,26./,21.0b11100000,13.A,12.0,11./,4.IndOff::::bsr r
 251         nia = do_bsr (_SD, nia, rLink, A, rIndOff);
 252 31.Link,26./,21.0b11100000,13.A,12.1,11./::::bsr l
 253         long_immediate (LongSignedImmediate);
 254         nia = do_bsr (_SD, nia, rLink, A, LongSignedImmediate);
 255
 256
 257 // cmnd
 258 void::function::do_cmnd:signed32 source
 259         int Reset = EXTRACTED32 (source, 31, 31);
 260         int Halt = EXTRACTED32 (source, 30, 30);
 261         int Unhalt = EXTRACTED32 (source, 29, 29);
 262         /* int ICR = EXTRACTED32 (source, 28, 28); */
 263         /* int DCR = EXTRACTED32 (source, 27, 27); */
 264         int Task = EXTRACTED32 (source, 14, 14);
 265         int Msg = EXTRACTED32 (source, 13, 13);
 266         int VC = EXTRACTED32 (source, 10, 10);
 267         int TC = EXTRACTED32 (source, 9, 9);
 268         int MP = EXTRACTED32 (source, 8, 8);
 269         int PP = EXTRACTED32 (source, 3, 0);
 270         /* what is implemented? */
 271         if (PP != 0)
 272           engine_error (SD, CPU, cia, "0x%lx: cmnd - PPs not supported",
 273                         (unsigned long) cia.ip);
 274         if (VC != 0)
 275           engine_error (SD, CPU, cia, "0x%lx: cmnd - VC not supported",
 276                         (unsigned long) cia.ip);
 277         if (TC != 0)
 278           engine_error (SD, CPU, cia, "0x%lx: cmnd - TC not supported",
 279                         (unsigned long) cia.ip);
 280         if (MP)
 281           {
 282             if (Reset || Halt)
 283               engine_halt (SD, CPU, cia, sim_exited, 0);
 284             if (Unhalt)
 285               engine_error (SD, CPU, cia, "0x%lx: cmnd - Can not unhalt the MP",
 286                             (unsigned long) cia.ip);
 287             /* if (ICR || DCR); */
 288             if (Task)
 289               engine_error (SD, CPU, cia, "0x%lx: cmnd - Can not Task the MP",
 290                             (unsigned long) cia.ip);
 291             if (Msg)
 292               engine_error (SD, CPU, cia, "0x%lx: cmnd - Msg to MP not suported",
 293                             (unsigned long) cia.ip);
 294           }
 295         TRACE_SINK1 (MY_INDEX, source);
 296 31./,21.0b0000010,14.UI::::cmnd i
 297         do_cmnd (_SD, UI);
 298 31./,21.0b110000010,12.0,11./,4.Source::::cmnd r
 299         do_cmnd (_SD, rSource);
 300 31./,21.0b110000010,12.1,11./::::cmnd l
 301         long_immediate (LongUnsignedImmediate);
 302         do_cmnd (_SD, LongUnsignedImmediate);
 303
 304 // cmp
 305 unsigned32::function::cmp_vals:signed32 s1, unsigned32 u1, signed32 s2, unsigned32 u2
 306         unsigned32 field = 0;
 307         if (s1 == s2) field |= 0x001;
 308         if (s1 != s2) field |= 0x002;
 309         if (s1 >  s2) field |= 0x004;
 310         if (s1 <= s2) field |= 0x008;
 311         if (s1 <  s2) field |= 0x010;
 312         if (s1 >= s2) field |= 0x020;
 313         if (u1 >  u2) field |= 0x040;
 314         if (u1 <= u2) field |= 0x080;
 315         if (u1 <  u2) field |= 0x100;
 316         if (u1 >= u2) field |= 0x200;
 317         return field;
 318 void::function::do_cmp:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
 319         unsigned32 field = 0;
 320         field |= cmp_vals (_SD, Source1, Source1, Source2, Source2) << 20;
 321         field |= cmp_vals (_SD, (signed16)Source1, (unsigned16)Source1,
 322                            (signed16)Source2, (unsigned16)Source2) << 10;
 323         field |= cmp_vals (_SD, (signed8)Source1, (unsigned8)Source1,
 324                             (signed8)Source2, (unsigned8)Source2);
 325         TRACE_ALU3 (MY_INDEX, field, Source1, Source2);
 326         *rDest = field;
 327 31.Dest,26.Source2,21.0b1010000,14.SignedImmediate::::cmp i
 328         do_cmp (_SD, rDest, vSource1, rSource2);
 329 31.Dest,26.Source2,21.0b111010000,12.0,11./,4.Source1::::cmp r
 330         do_cmp (_SD, rDest, rSource1, rSource2);
 331 31.Dest,26.Source2,21.0b111010000,12.1,11./::::cmp l
 332         long_immediate (LongSignedImmediate);
 333         do_cmp (_SD, rDest, LongSignedImmediate, rSource2);
 334
 335
 336 // dcache
 337 31./,27.F,26.Source2,21.0b0111,17.M,16.0b00,14.SignedOffset::::dcache i
 338         TRACE_NOP (MY_INDEX);
 339         /* NOP */
 340 31./,27.F,26.Source2,21.0b110111,15.M,14.0b00,12.0,11./,4.Source1::::dcache r
 341         TRACE_NOP (MY_INDEX);
 342         /* NOP */
 343 31./,27.F,26.Source2,21.0b110111,15.M,14.0b00,12.1,11./::::dcache l
 344         long_immediate (LongSignedImmediate);
 345         LongSignedImmediate++;
 346         TRACE_NOP (MY_INDEX);
 347         /* NOP */
 348
 349
 350 // dld[{.b|.h|.d}]
 351 void::function::do_dld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
 352         do_ld (_SD, Dest, Base, rBase, m, sz, S, Offset);
 353 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dld r
 354         do_dld (_SD, Dest, rBase, &GPR(Base), m, sz, S, rIndOff);
 355 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.1,9./::::dld l
 356         long_immediate (LongSignedImmediateOffset);
 357         do_dld (_SD, Dest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
 358
 359
 360 // dld.u[{.b|.h|.d}]
 361 void::function::do_dld_u:unsigned32 *rDest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
 362         do_ld_u (_SD, rDest, Base, rBase, m, sz, S, Offset);
 363 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dld.u r
 364         do_dld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, rIndOff);
 365 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.1,9./::::dld.u l
 366         long_immediate (LongSignedImmediateOffset);
 367         do_dld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
 368
 369
 370 // dst[{.b|.h|.d}]
 371 void::function::do_dst:int Source, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
 372         do_st (_SD, Source, Base, rBase, m, sz, S, Offset);
 373 31.Source,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dst r
 374         do_dst (_SD, Source, rBase, &GPR(Base), m, sz, S, rIndOff);
 375 31.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.1,9./::::dst l
 376         long_immediate (LongSignedImmediateOffset);
 377         do_dst (_SD, Source, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
 378
 379
 380 // estop
 381 31./,21.0b1111111,14.1,13.0,12.0,11./::::estop
 382
 383 // etrap
 384 31./,27.1,26./,21.0b0000001,14.UTN::::etrap i
 385 31./,27.1,26./,21.0b110000001,12.0,11./,4.iUTN::::etrap r
 386 31./,27.1,26./,21.0b110000001,12.1,11./::::etrap l
 387
 388
 389 // exts - see shift.ds
 390
 391
 392 // extu - see shift.dz
 393
 394
 395 sim_fpu::function::get_fp_reg:int reg, unsigned32 val, int precision
 396         switch (precision)
 397           {
 398           case 0: /* single */
 399             return sim_fpu_32to (val);
 400           case 1: /* double */
 401             if (reg < 0)
 402               engine_error (SD, CPU, cia, "DP immediate invalid");
 403             if (reg & 1)
 404               engine_error (SD, CPU, cia, "DP FP register must be even");
 405             if (reg <= 1)
 406               engine_error (SD, CPU, cia, "DP FP register must be >= 2");
 407             return sim_fpu_64to (INSERTED64 (GPR(reg + 1), 63, 32)
 408                                  | INSERTED64 (GPR(reg), 31, 0));
 409           case 2: /* 32 bit signed integer */
 410             return sim_fpu_i32to (val);
 411           case 3: /* 32 bit unsigned integer */
 412             return sim_fpu_u32to (val);
 413           default:
 414             engine_error (SD, CPU, cia, "Unsupported FP precision");
 415           }
 416         return sim_fpu_i32to (0);
 417 void::function::set_fp_reg:int Dest, sim_fpu val, int PD
 418         switch (PD)
 419           {
 420           case 0: /* single */
 421             {
 422               GPR (Dest) = sim_fpu_to32 (val);
 423               break;
 424             }
 425           case 1: /* double */
 426             {
 427               unsigned64 v = sim_fpu_to64 (val);
 428               if (Dest & 1)
 429                 engine_error (SD, CPU, cia, "DP FP Dest register must be even");
 430               if (Dest <= 1)
 431                 engine_error (SD, CPU, cia, "DP FP Dest register must be >= 2");
 432               GPR (Dest + 0) = VL4_8 (v);
 433               GPR (Dest + 1) = VH4_8 (v);
 434               break;
 435             }
 436           case 2: /* signed */
 437             {
 438               GPR (Dest) = sim_fpu_to32i (val);
 439               break;
 440             }
 441           case 3: /* unsigned */
 442             {
 443               GPR (Dest) = sim_fpu_to32u (val);
 444               break;
 445             }
 446           default:
 447             engine_error (SD, CPU, cia, "Unsupported FP precision");
 448           }
 449
 450 // fadd.{s|d}{s|d}{s|d}
 451 void::function::do_fadd:int Dest, int PD, sim_fpu s1, sim_fpu s2
 452         sim_fpu ans = sim_fpu_add (s1, s2);
 453         TRACE_FPU3 (MY_INDEX, ans, s1, s2);
 454         set_fp_reg (_SD, Dest, ans, PD);
 455 31.Dest,26.Source2,21.0b111110000,12.0,11.r,10.PD,8.P2,6.P1,4.Source1::f::fadd r
 456         do_fadd (_SD, Dest, PD,
 457                  get_fp_reg (_SD, Source1, rSource1, P1),
 458                  get_fp_reg (_SD, Source2, rSource2, P2));
 459 31.Dest,26.Source2,21.0b111110000,12.1,11.r,10.PD,8.P2,6.P1,4./::f::fadd l
 460         long_immediate (SinglePrecisionFloatingPoint);
 461         do_fadd (_SD, Dest, PD,
 462                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
 463                  get_fp_reg (_SD, Source2, rSource2, P2));
 464
 465
 466 // fcmp.{s|d}{s|d}{s|d}
 467 void::function::do_fcmp:int Dest, sim_fpu s1, sim_fpu s2
 468         unsigned32 result = 0;
 469         if (sim_fpu_is_nan (s1) || sim_fpu_is_nan (s2))
 470           result |= BIT32 (30);
 471         else
 472           {
 473             result |= BIT32 (31);
 474             if (sim_fpu_is_eq (s1, s2)) result |= BIT32(20);
 475             if (sim_fpu_is_ne (s1, s2)) result |= BIT32(21);
 476             if (sim_fpu_is_gt (s1, s2)) result |= BIT32(22);
 477             if (sim_fpu_is_le (s1, s2)) result |= BIT32(23);
 478             if (sim_fpu_is_lt (s1, s2)) result |= BIT32(24);
 479             if (sim_fpu_is_ge (s1, s2)) result |= BIT32(25);
 480             if (sim_fpu_is_lt (s1, sim_fpu_i32to (0))
 481                 || sim_fpu_is_gt (s1, s2)) result |= BIT32(26);
 482             if (sim_fpu_is_lt (sim_fpu_i32to (0), s1)
 483                 && sim_fpu_is_lt (s1, s2)) result |= BIT32(27);
 484             if (sim_fpu_is_le (sim_fpu_i32to (0), s1)
 485                 && sim_fpu_is_le (s1, s2)) result |= BIT32(28);
 486             if (sim_fpu_is_le (s1, sim_fpu_i32to (0))
 487                 || sim_fpu_is_ge (s1, s2)) result |= BIT32(29);
 488           }
 489         GPR (Dest) = result;
 490         TRACE_FPU2I (MY_INDEX, result, s1, s2);
 491 31.Dest,26.Source2,21.0b111110101,12.0,11./,10.0,8.P2,6.P1,4.Source1::f::fcmp r
 492         do_fcmp (_SD, Dest,
 493                  get_fp_reg (_SD, Source1, rSource1, P1),
 494                  get_fp_reg (_SD, Source2, rSource2, P2));
 495 31.Dest,26.Source2,21.0b111110101,12.1,11./,10.0,8.P2,6.P1,4./::f::fcmp l
 496         long_immediate (SinglePrecisionFloatingPoint);
 497         do_fcmp (_SD, Dest,
 498                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
 499                  get_fp_reg (_SD, Source2, rSource2, P2));
 500
 501
 502
 503 // fdiv.{s|d}{s|d}{s|d}
 504 void::function::do_fdiv:int Dest, int PD, sim_fpu s1, sim_fpu s2
 505         sim_fpu ans = sim_fpu_div (s1, s2);
 506         TRACE_FPU3 (MY_INDEX, ans, s1, s2);
 507         set_fp_reg (_SD, Dest, ans, PD);
 508 31.Dest,26.Source2,21.0b111110011,12.0,11./,10.PD,8.P2,6.P1,4.Source1::f::fdiv r
 509         do_fdiv (_SD, Dest, PD,
 510                  get_fp_reg (_SD, Source1, rSource1, P1),
 511                  get_fp_reg (_SD, Source2, rSource2, P2));
 512 31.Dest,26.Source2,21.0b111110011,12.1,11./,10.PD,8.P2,6.P1,4./::f::fdiv l
 513         long_immediate (SinglePrecisionFloatingPoint);
 514         do_fdiv (_SD, Dest, PD,
 515                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
 516                  get_fp_reg (_SD, Source2, rSource2, P2));
 517
 518
 519 // fmpy.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 520 void::function::do_fmpy:int Dest, int PD, sim_fpu s1, sim_fpu s2
 521         switch (PD)
 522           {
 523           case 2: /* signed */
 524             {
 525               GPR (Dest) = sim_fpu_to64i (s1) * sim_fpu_to64i (s2);
 526               TRACE_FPU2I (MY_INDEX, GPR (Dest), s1, s2);
 527               break;
 528             }
 529           case 3: /* unsigned */
 530             {
 531               GPR (Dest) = sim_fpu_to64u (s1) * sim_fpu_to64u (s2);
 532               TRACE_FPU2I (MY_INDEX, GPR (Dest), s1, s2);
 533               break;
 534             }
 535           default:
 536             {
 537               sim_fpu ans = sim_fpu_mul (s1, s2);
 538               set_fp_reg (_SD, Dest, ans, PD);
 539               TRACE_FPU3 (MY_INDEX, ans, s1, s2);
 540             }
 541           }
 542 31.Dest,26.Source2,21.0b111110010,12.0,11./,10.PD,8.P2,6.P1,4.Source1::f::fmpy r
 543         do_fmpy (_SD, Dest, PD,
 544                  get_fp_reg (_SD, Source1, rSource1, P1),
 545                  get_fp_reg (_SD, Source2, rSource2, P2));
 546 31.Dest,26.Source2,21.0b111110010,12.1,11./,10.PD,8.P2,6.P1,4./::f::fmpy l
 547         long_immediate (SinglePrecisionFloatingPoint);
 548         do_fmpy (_SD, Dest, PD,
 549                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
 550                  get_fp_reg (_SD, Source2, rSource2, P2));
 551
 552
 553 // frndm.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 554 void::function::do_frnd:int Dest, int PD, sim_fpu s1
 555         set_fp_reg (_SD, Dest, s1, PD);
 556         TRACE_FPU1 (MY_INDEX, s1);
 557 31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b11,6.P1,4.Source::f::frndm r
 558         do_frnd (_SD, Dest, PD,
 559                  get_fp_reg (_SD, Source, rSource, P1));
 560 31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b11,6.P1,4./::f::frndm l
 561         long_immediate (SinglePrecisionFloatingPoint);
 562         do_frnd (_SD, Dest, PD,
 563                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
 564
 565
 566 // frndn.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 567 31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b00,6.P1,4.Source::f::frndn r
 568         do_frnd (_SD, Dest, PD,
 569                  get_fp_reg (_SD, Source, rSource, P1));
 570 31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b00,6.P1,4./::f::frndn l
 571         long_immediate (SinglePrecisionFloatingPoint);
 572         do_frnd (_SD, Dest, PD,
 573                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
 574
 575
 576 // frndp.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 577 31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b10,6.P1,4.Source::f::frndp r
 578         do_frnd (_SD, Dest, PD,
 579                  get_fp_reg (_SD, Source, rSource, P1));
 580 31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b10,6.P1,4./::f::frndp l
 581         long_immediate (SinglePrecisionFloatingPoint);
 582         do_frnd (_SD, Dest, PD,
 583                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
 584
 585
 586 // frndz.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 587 31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b01,6.P1,4.Source::f::frndz r
 588         do_frnd (_SD, Dest, PD,
 589                  get_fp_reg (_SD, Source, rSource, P1));
 590 31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b01,6.P1,4./::f::frndz l
 591         long_immediate (SinglePrecisionFloatingPoint);
 592         do_frnd (_SD, Dest, PD,
 593                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
 594
 595
 596 // fsqrt.{s|d}{s|d}{s|d}
 597 #void::function::do_fsqrt:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
 598 #       sim_io_error ("fsqrt");
 599 31.Dest,26.Source2,21.0b111110111,12.0,11./,10.PD,8.//,6.P1,4.Source1::f::fsqrt r
 600 #       do_fsqrt (_SD, rDest, rSource1, rSource2);
 601 31.Dest,26.Source2,21.0b111110111,12.1,11./,10.PD,8.//,6.P1,4./::f::fsqrt l
 602 #       do_fsqrt (_SD, rDest, LongSignedImmediate, rSource2);
 603
 604
 605 // fsub.{s|d}{s|d}{s|d}
 606 void::function::do_fsub:int Dest, int PD, sim_fpu s1, sim_fpu s2
 607         sim_fpu ans = sim_fpu_sub (s1, s2);
 608         TRACE_FPU3 (MY_INDEX, ans, s1, s2);
 609         set_fp_reg (_SD, Dest, ans, PD);
 610 31.Dest,26.Source2,21.0b111110001,12.0,11.r,10.PD,8.P2,6.P1,4.Source1::f::fsub r
 611         do_fsub (_SD, Dest, PD,
 612                  get_fp_reg (_SD, Source1, rSource1, P1),
 613                  get_fp_reg (_SD, Source2, rSource2, P2));
 614 31.Dest,26.Source2,21.0b111110001,12.1,11.r,10.PD,8.P2,6.P1,4./::f::fsub l
 615         long_immediate (SinglePrecisionFloatingPoint);
 616         do_fsub (_SD, Dest, PD,
 617                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
 618                  get_fp_reg (_SD, Source2, rSource2, P2));
 619
 620
 621 // illop
 622 31./,21.0b0000000,14./::::illop
 623 31./,21.0b111111111,12./::::illop l
 624
 625
 626 // ins - see sl.im
 627
 628
 629 // jsr[.a]
 630 instruction_address::function::do_jsr:instruction_address nia, signed32 *rLink, int annul, unsigned32 offset, unsigned32 base
 631         address_word target = offset + base;
 632         TRACE_UCOND_BR (MY_INDEX, target);
 633         nia = do_branch (_SD, annul, target, 1, rLink);
 634         if (nia.dp & 0x3)
 635           engine_error (SD, CPU, cia,
 636                         "0x%lx: destination address 0x%lx misaligned",
 637                         (unsigned long) cia.ip,
 638                         (unsigned long) nia.dp);
 639         return nia;
 640 31.Link,26.Base,21.0b100010,15.A,14.SignedOffset::::jsr i
 641         nia = do_jsr (_SD, nia, rLink, A, vSignedOffset, rBase);
 642 31.Link,26.Base,21.0b11100010,13.A,12.0,11./,4.Source1::::jsr r
 643         nia = do_jsr (_SD, nia, rLink, A, rSource1, rBase);
 644 31.Link,26.Base,21.0b11100010,13.A,12.1,11./::::jsr l
 645         long_immediate (LongSignedImmediate);
 646         nia = do_jsr (_SD, nia, rLink, A, LongSignedImmediate, rBase);
 647
 648
 649 // ld[{.b.h.d}]
 650 void::function::do_ld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
 651         unsigned32 addr;
 652         switch (sz)
 653           {
 654           case 0:
 655             addr = Base + (S ? (Offset << 0) : Offset);
 656             if (m)
 657               *rBase = addr;
 658             GPR(Dest) = MEM (signed, addr, 1);
 659             break;
 660           case 1:
 661             addr = Base + (S ? (Offset << 1) : Offset);
 662             if (m)
 663               *rBase = addr;
 664             GPR(Dest) = MEM (signed, addr, 2);
 665             break;
 666           case 2:
 667             addr = Base + (S ? (Offset << 2) : Offset);
 668             if (m)
 669               *rBase = addr;
 670             GPR(Dest) = MEM (signed, addr, 4);
 671             break;
 672           case 3:
 673             {
 674               signed64 val;
 675               if (Dest & 0x1)
 676                 engine_error (SD, CPU, cia, "0x%lx: ld.d to odd register %d",
 677                               cia.ip, Dest);
 678               addr = Base + (S ? (Offset << 3) : Offset);
 679               if (m)
 680                 *rBase = addr;
 681               val = MEM (signed, addr, 8);
 682               GPR(Dest + 1) = VH4_8 (val);
 683               GPR(Dest + 0) = VL4_8 (val);
 684             }
 685             break;
 686           default:
 687             addr = -1;
 688             engine_error (SD, CPU, cia, "ld - invalid sz %d", sz);
 689           }
 690         TRACE_LD (MY_INDEX, GPR(Dest), m, S, Base, Offset);
 691 31.Dest,26.Base,21.0b0100,17.m,16.sz,14.SignedOffset::::ld i
 692         do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, 0, vSignedOffset);
 693 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::ld r
 694         do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, S, rIndOff);
 695 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.0,9./::::ld l
 696         long_immediate (LongSignedImmediateOffset);
 697         do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
 698
 699
 700 // ld.u[{.b.h.d}]
 701 void::function::do_ld_u:unsigned32 *rDest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
 702         unsigned32 addr;
 703         switch (sz)
 704           {
 705           case 0:
 706             addr = Base + (S ? (Offset << 0) : Offset);
 707             *rDest = MEM (unsigned, addr, 1);
 708             break;
 709           case 1:
 710             addr = Base + (S ? (Offset << 1) : Offset);
 711             *rDest = MEM (unsigned, addr, 2);
 712             break;
 713           default:
 714             addr = -1;
 715             engine_error (SD, CPU, cia, "ld.u - invalid sz %d", sz);
 716           }
 717         if (m)
 718           *rBase = addr;
 719         TRACE_LD (MY_INDEX, m, S, *rDest, Base, Offset);
 720 31.Dest,26.Base,21.0b0101,17.m,16.sz,14.SignedOffset::::ld.u i
 721         do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, 0, vSignedOffset);
 722 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::ld.u r
 723         do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, rIndOff);
 724 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.0,9./::::ld.u l
 725         long_immediate (LongSignedImmediateOffset);
 726         do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
 727
 728
 729 // lmo
 730 31.Dest,26.Source,21.0b111111000,12.0,11./::::lmo
 731         int b;
 732         for (b = 0; b < 32; b++)
 733           if (rSource & BIT32 (31 - b))
 734             break;
 735         TRACE_ALU2 (MY_INDEX, b, rSource);
 736         *rDest = b;
 737
 738
 739 // nop - see rdcr 0, r0
 740
 741
 742 void::function::do_or:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
 743         unsigned32 result = Source1 | Source2;
 744         TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
 745         *rDest = result;
 746
 747
 748 // or, or.tt
 749 31.Dest,26.Source2,21.0b0010111,14.UnsignedImmediate::::or.tt i
 750         do_or (_SD, rDest, vSource1, rSource2);
 751 31.Dest,26.Source2,21.0b110010111,12.0,11./,4.Source1::::or.tt r
 752         do_or (_SD, rDest, rSource1, rSource2);
 753 31.Dest,26.Source2,21.0b110010111,12.1,11./::::or.tt l
 754         long_immediate (LongUnsignedImmediate);
 755         do_or (_SD, rDest, LongUnsignedImmediate, rSource2);
 756
 757
 758 // or.ff
 759 31.Dest,26.Source2,21.0b0011110,14.UnsignedImmediate::::or.ff i
 760         do_or (_SD, rDest, ~vSource1, ~rSource2);
 761 31.Dest,26.Source2,21.0b110011110,12.0,11./,4.Source1::::or.ff r
 762         do_or (_SD, rDest, ~rSource1, ~rSource2);
 763 31.Dest,26.Source2,21.0b110011110,12.1,11./::::or.ff l
 764         long_immediate (LongUnsignedImmediate);
 765         do_or (_SD, rDest, ~LongUnsignedImmediate, ~rSource2);
 766
 767
 768 // or.ft
 769 31.Dest,26.Source2,21.0b0011101,14.UnsignedImmediate::::or.ft i
 770         do_or (_SD, rDest, ~vSource1, rSource2);
 771 31.Dest,26.Source2,21.0b110011101,12.0,11./,4.Source1::::or.ft r
 772         do_or (_SD, rDest, ~rSource1, rSource2);
 773 31.Dest,26.Source2,21.0b110011101,12.1,11./::::or.ft l
 774         long_immediate (LongUnsignedImmediate);
 775         do_or (_SD, rDest, ~LongUnsignedImmediate, rSource2);
 776
 777
 778 // or.tf
 779 31.Dest,26.Source2,21.0b0011011,14.UnsignedImmediate::::or.tf i
 780         do_or (_SD, rDest, vSource1, ~rSource2);
 781 31.Dest,26.Source2,21.0b110011011,12.0,11./,4.Source1::::or.tf r
 782         do_or (_SD, rDest, rSource1, ~rSource2);
 783 31.Dest,26.Source2,21.0b110011011,12.1,11./::::or.tf l
 784         long_immediate (LongUnsignedImmediate);
 785         do_or (_SD, rDest, LongUnsignedImmediate, ~rSource2);
 786
 787
 788 // rdcr
 789 void::function::do_rdcr:unsigned32 Dest, int cr
 790         TRACE_SINK2 (MY_INDEX, Dest, cr);
 791         GPR (Dest) = CR (cr);
 792 31.Dest,26.0,21.0b0000100,14.UCRN::::rdcr i
 793         do_rdcr (_SD, Dest, UCRN);
 794 31.Dest,26.0,21.0b110000100,12.0,11./,4.INDCR::::rdcr r
 795         do_rdcr (_SD, Dest, UCRN);
 796 31.Dest,26.0,21.0b110000100,12.1,11./::::rdcr l
 797         long_immediate (UnsignedControlRegisterNumber);
 798         do_rdcr (_SD, Dest, UnsignedControlRegisterNumber);
 799
 800
 801 // rmo
 802 31.Dest,26.Source,21.0b111111001,12.0,11./::::rmo
 803         int b;
 804         for (b = 0; b < 32; b++)
 805           if (rSource & BIT32 (b))
 806             break;
 807         if (b < 32)
 808           b = 31 - b;
 809         TRACE_ALU2 (MY_INDEX, b, rSource);
 810         *rDest = b;
 811
 812
 813 // rotl - see sl.dz
 814
 815
 816 // rotr - see sl.dz
 817
 818
 819 // shl - see sl.iz
 820
 821
 822 // sl.{d|e|i}{m|s|z}
 823 void::function::do_shift:int Dest, int Source, int Merge, int i, int n, int EndMask, int Rotate
 824         /* see 10-30 for a reasonable description */
 825         unsigned32 input = GPR (Source);
 826         unsigned32 rotated;
 827         unsigned32 endmask;
 828         unsigned32 shiftmask;
 829         unsigned32 cm;
 830         int nRotate;
 831         /* rotate the source */
 832         if (n)
 833           {
 834             rotated = ROTR32 (GPR (Source), Rotate);
 835             nRotate = (- Rotate) & 31;
 836           }
 837         else
 838           {
 839             rotated = ROTL32 (GPR (Source), Rotate);
 840             nRotate = Rotate;
 841           }
 842         /* form the end mask */
 843         if (EndMask == 0)
 844           endmask = ~ (unsigned32)0;
 845         else
 846           endmask = (1 << EndMask) - 1;
 847         if (i)
 848           endmask = ~endmask;
 849         /* form the shiftmask */
 850         switch (Merge)
 851           {
 852           case 0: case 1: case 2:
 853             shiftmask = ~ (unsigned32)0;        /* disabled */
 854             break;
 855           case 3: case 5:                       /* enabled - 0 -> 32 */
 856             if (nRotate == 0)
 857               shiftmask = ~ (unsigned32)0;
 858             else
 859               shiftmask = ((1 << nRotate) - 1); /* enabled - 0 -> 0 */
 860             break;
 861           case 4:
 862             shiftmask = ((1 << nRotate) - 1);   /* enabled - 0 -> 0 */
 863             break;
 864           case 6: case 7:
 865             shiftmask = ~((1 << nRotate) - 1);  /* inverted */
 866             break;
 867           default:
 868             engine_error (SD, CPU, cia,
 869                           "0x%lx: Invalid merge (%d) for shift",
 870                           cia.ip, Source);
 871             shiftmask = 0;
 872           }
 873         /* and the composite mask */
 874         cm = shiftmask & endmask;
 875         /* and merge */
 876         switch (Merge)
 877           {
 878           case 0: case 3: case 6:               /* zero */
 879             GPR (Dest) = rotated & cm;
 880             break;
 881           case 1: case 4: case 7:               /* merge */
 882             GPR (Dest) = (rotated & cm) | (GPR (Dest) & ~cm);
 883             break;
 884           case 2: case 5:                       /* sign */
 885             {
 886               int b;
 887               GPR (Dest) = rotated & cm;
 888               for (b = 1; b <= 31; b++)
 889                 if (!MASKED32 (cm, b, b))
 890                   GPR (Dest) |= INSERTED32 (EXTRACTED32 (GPR (Dest), b - 1, b - 1),
 891                                             b, b);
 892             }
 893             break;
 894           default:
 895             engine_error (SD, CPU, cia,
 896                           "0x%lx: Invalid merge (%d)",
 897                           cia.ip, Source);
 898
 899           }
 900         TRACE_SHIFT (MY_INDEX, GPR (Dest), input, i, n, Merge, EndMask, Rotate);
 901 31.Dest,26.Source,21.0b0001,17.Merge,14./,11.i,10.n,9.EndMask,4.Rotate::::sl i
 902         do_shift (_SD, Dest, Source, Merge, i, n, EndMask, Rotate);
 903 31.Dest,26.Source,21.0b110001,15.Merge,12.0,11.i,10.n,9.EndMask,4.RotReg::::sl r
 904         do_shift (_SD, Dest, Source, Merge, i, n, EndMask, GPR (RotReg) & 31);
 905
 906
 907 // sli.{d|e|i}{m|s|z} - see shift
 908
 909
 910 // sr.{d|e|i}{m|s|z} - see shift
 911
 912
 913 // sra - see sr.es - see shift
 914
 915
 916 // sri.{d|e|i}{m|s|z} - see shift
 917
 918
 919 // srl - see sr.ez
 920
 921
 922 // st[{.b|.h|.d}]
 923 void::function::do_st:int Source, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
 924         unsigned32 addr;
 925         switch (sz)
 926           {
 927           case 0:
 928             addr = Base + (S ? (Offset << 0) : Offset);
 929             STORE (addr, 1, GPR(Source));
 930             break;
 931           case 1:
 932             addr = Base + (S ? (Offset << 1) : Offset);
 933             STORE (addr, 2, GPR(Source));
 934             break;
 935           case 2:
 936             addr = Base + (S ? (Offset << 2) : Offset);
 937             STORE (addr, 4, GPR(Source));
 938             break;
 939           case 3:
 940             {
 941               signed64 val;
 942               if (Source & 0x1)
 943                 engine_error (SD, CPU, cia,
 944                               "0x%lx: st.d with odd source register %d",
 945                               cia.ip, Source);
 946               addr = Base + (S ? (Offset << 3) : Offset);
 947               val = (V4_H8 (GPR(Source + 1)) | V4_L8 (GPR(Source)));
 948               STORE (addr, 8, val);
 949             }
 950             break;
 951           default:
 952             addr = -1;
 953             engine_error (SD, CPU, cia, "st - invalid sz %d", sz);
 954           }
 955         if (m)
 956           *rBase = addr;
 957         TRACE_ST (MY_INDEX, Source, m, S, Base, Offset);
 958 31.Source,26.Base,21.0b0110,17.m,16.sz,14.SignedOffset::::st i
 959         do_st (_SD, Source, rBase, &GPR(Base), m, sz, 0, vSignedOffset);
 960 31.Source,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::st r
 961         do_st (_SD, Source, rBase, &GPR(Base), m, sz, S, rIndOff);
 962 31.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.0,9./::::st l
 963         long_immediate (LongSignedImmediateOffset);
 964         do_st (_SD, Source, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
 965
 966
 967 // sub
 968 void::function::do_sub:signed32 *rDest, signed32 Source1, signed32 Source2
 969         ALU_BEGIN (Source1);
 970         ALU_SUB (Source2);
 971         ALU_END (*rDest);
 972         TRACE_ALU3 (MY_INDEX, *rDest, Source1, Source2);
 973 31.Dest,26.Source2,21.0b101101,15.0,14.SignedImmediate::::sub i
 974         do_sub (_SD, rDest, vSource1, rSource2);
 975 31.Dest,26.Source2,21.0b11101101,13.0,12.0,11./,4.Source1::::sub r
 976         do_sub (_SD, rDest, rSource1, rSource2);
 977 31.Dest,26.Source2,21.0b11101101,13.0,12.1,11./::::sub l
 978         long_immediate (LongSignedImmediate);
 979         do_sub (_SD, rDest, LongSignedImmediate, rSource2);
 980
 981
 982 // subu
 983 void::function::do_subu:unsigned32 *rDest, unsigned32 Source1, signed32 Source2
 984         unsigned32 result = Source1 - Source2;
 985         TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
 986         *rDest = result;
 987 // NOTE - the book has 15.1 which conflicts with subu.
 988 31.Dest,26.Source2,21.0b101101,15.1,14.UnsignedImmediate::::subu i
 989         do_subu (_SD, rDest, vSource1, rSource2);
 990 31.Dest,26.Source2,21.0b11101101,13.1,12.0,11./,4.Source1::::subu r
 991         do_subu (_SD, rDest, rSource1, rSource2);
 992 31.Dest,26.Source2,21.0b11101101,13.1,12.1,11./::::subu l
 993         long_immediate (LongSignedImmediate);
 994         do_subu (_SD, rDest, LongSignedImmediate, rSource2);
 995
 996
 997 // swcr
 998 void::function::do_swcr:int Dest, signed32 rSource, signed32 cr
 999         tic80_control_regs reg = tic80_index2cr (cr);
1000         /* cache the old CR value */
1001         unsigned32 old_cr = CR (cr);
1002         /* Handle the write if allowed */
1003         if (cr >= 0x4000 || !(CPU)->is_user_mode)
1004           switch (reg)
1005             {
1006             case INTPEN_CR:
1007               CR (cr) &= ~rSource;
1008               break;
1009             default:
1010               CR (cr) = rSource;
1011               break;
1012             }
1013         /* Finish off the read */
1014         GPR (Dest) = old_cr;
1015         TRACE_SINK3 (MY_INDEX, rSource, cr, Dest);
1016 31.Dest,26.Source,21.0b000010,15.1,14.UCRN::::swcr i
1017         do_swcr (_SD, Dest, rSource, UCRN);
1018 31.Dest,26.Source,21.0b11000010,13.1,12.0,11./,4.INDCR::::swcr r
1019         do_swcr (_SD, Dest, rSource, UCRN);
1020 31.Dest,26.Source,21.0b11000010,13.1,12.1,11./::::swcr l
1021         long_immediate (LongUnsignedControlRegister);
1022         do_swcr (_SD, Dest, rSource, LongUnsignedControlRegister);
1023
1024
1025 // trap
1026 void::function::do_trap:unsigned32 trap_number
1027         int i;
1028         TRACE_SINK1 (MY_INDEX, trap_number);
1029         switch (trap_number)
1030           {
1031           case 72:
1032             switch (GPR(15))
1033               {
1034               case 1: /* EXIT */
1035                 {
1036                   engine_halt (SD, CPU, cia, sim_exited, GPR(2));
1037                   break;
1038                 }
1039               case 4: /* WRITE */
1040                 {
1041                   int i;
1042                   if (GPR(2) == 1)
1043                     for (i = 0; i < GPR(6); i++)
1044                       {
1045                         char c;
1046                         c = MEM (unsigned, GPR(4) + i, 1);
1047                         sim_io_write_stdout (SD, &c, 1);
1048                       }
1049                   else if (GPR(2) == 2)
1050                     for (i = 0; i < GPR(6); i++)
1051                       {
1052                         char c;
1053                         c = MEM (unsigned, GPR(4) + i, 1);
1054                         sim_io_write_stderr (SD, &c, 1);
1055                       }
1056                   else
1057                     engine_error (SD, CPU, cia,
1058                                   "0x%lx: write to invalid fid %d",
1059                                   (unsigned long) cia.ip, GPR(2));
1060                   GPR(2) = GPR(6);
1061                   break;
1062                 }
1063               default:
1064                 /* For system calls which are defined, just return EINVAL instead of trapping */
1065                 if (GPR(15) <= 204)
1066                   {
1067                     GPR(2) = -22;               /* -EINVAL */
1068                     break;
1069                   }
1070                 engine_error (SD, CPU, cia,
1071                               "0x%lx: unknown syscall %d",
1072                               (unsigned long) cia.ip, GPR(15));
1073               }
1074             break;
1075           case 73:
1076             engine_halt (SD, CPU, cia, sim_stopped, SIGTRAP);
1077
1078           /* Add a few traps for now to print the register state */
1079           case 74:
1080           case 75:
1081           case 76:
1082           case 77:
1083           case 78:
1084           case 79:
1085             if (!TRACE_ALU_P (CPU))
1086               trace_one_insn (SD, CPU, cia.ip, 1, itable[MY_INDEX].file,
1087                               itable[MY_INDEX].line_nr, "trap",
1088                               "Trap %ld", (long) trap_number);
1089
1090             for (i = 0; i < 32; i++)
1091               sim_io_eprintf (SD, "%s0x%.8lx%s", ((i % 8) == 0) ? "\t" : " ", (long)GPR(i),
1092                               (((i+1) % 8) == 0) ? "\n" : "");
1093             sim_io_write_stderr (SD, "\n", 1);
1094             break;
1095
1096           default:
1097             engine_error (SD, CPU, cia,
1098                           "0x%lx: unsupported trap %d",
1099                           (unsigned long) cia.ip, trap_number);
1100           }
1101 31./,27.0,26./,21.0b0000001,14.UTN::::trap i
1102         do_trap (_SD, UTN);
1103 31./,27.0,26./,21.0b110000001,12.0,11./,4.INDTR::::trap r
1104         do_trap (_SD, UTN);
1105 31./,27.0,26./,21.0b110000001,12.1,11./::::trap l
1106         long_immediate (UTN);
1107         do_trap (_SD, UTN);
1108
1109
1110 // vadd.{s|d}{s|d}
1111 31.*,26.Dest,21.0b11110,16./,15.0b000,12.0,11./,10.*,9.*,7.PD,6.*,5.P1,4.Source::f::vadd r
1112 31.*,26.Dest,21.0b11110,16./,15.0b000,12.1,11./,10.*,9.*,7.PD,6.*,5.P1,4.Source::f::vadd l
1113
1114
1115 // vld{0|1}.{s|d} - see above - same instruction
1116 #31.Dest,26.*,21.0b11110,16.*,10.1,9.S,8.*,6.p,7.******::f::vld
1117
1118
1119 // vmac.ss{s|d}
1120 #31.*,   26.Source2,21.0b11110,16.a0,15.0b110,12.0,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4.Source1::f::vmac.ss ra
1121 31.Dest,26.Source2,21.0b11110,16.a0,15.0b110,12.0,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4.Source1::f::vmac.ss rr
1122 #31.*,   26.Source2,21.0b11110,16.a0,15.0b110,12.1,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4./::f::vmac.ss ia
1123 31.Dest,26.Source2,21.0b11110,16.a0,15.0b110,12.1,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4./::f::vmac.ss ir
1124
1125
1126 // vmpy.{s|d}{s|d}
1127 31.*,26.Dest,21.0b11110,16./,15.0b010,12.0,11./,10.*,8.*,7.PD,6.*,5.P1,4.Source::f::vmpy r
1128 31.*,26.Dest,21.0b11110,16./,15.0b010,12.1,11./,10.*,8.*,7.PD,6.*,5.P1,4./::f::vmpy l
1129
1130
1131 // vmsc.ss{s|d}
1132 #31.*,   26.Source2,21.0b11110,16.a0,15.0b111,12.0,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4.Source1::f::vmsc.ss ra
1133 31.Dest,26.Source2,21.0b11110,16.a0,15.0b111,12.0,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4.Source1::f::vmsc.ss rr
1134 #31.*,   26.Source2,21.0b11110,16.a0,15.0b111,12.1,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4./::f::vmsc.ss ia
1135 31.Dest,26.Source2,21.0b11110,16.a0,15.0b111,12.1,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4./::f::vmsc.ss ir
1136
1137
1138 // vmsub.{s|d}{s|d}
1139 31.*,26.Dest,21.0b11110,16.a0,15.0b011,12.0,11.a1,10.*,8.Z,7.PD,6.*,5./,4.Source::f::vmsub r
1140 31.*,26.Dest,21.0b11110,16.a0,15.0b011,12.1,11.a1,10.*,8.Z,7.PD,6.*,5./,4./::f::vmsub l
1141
1142
1143 // vrnd.{s|d}{s|d}
1144 31.*,26.Dest,21.0b11110,16.a0,15.0b100,12.0,11.a1,10.*,8.PD,6.*,5.P1,4.Source::f::vrnd f r
1145 31.*,26.Dest,21.0b11110,16.a0,15.0b100,12.1,11.a1,10.*,8.PD,6.*,5.P1,4./::f::vrnd f l
1146
1147
1148 // vrnd.{i|u}{s|d}
1149 31.*,26.Dest,21.0b11110,16./,15.0b101,12.0,11./,10.*,8./,7.PD,6.*,5.P1,4.Source::f::vrnd i r
1150 31.*,26.Dest,21.0b11110,16./,15.0b101,12.1,11./,10.*,8./,7.PD,6.*,5.P1,4./::f::vrnd i l
1151
1152
1153 // vst.{s|d} - see above - same instruction
1154 #31.Source,26.*,21.0b11110,16.*,10.0,9.S,8.*,6.1,5.*::f::vst
1155
1156
1157 // vsub.{i|u}{s|d}
1158 31.*,26.Dest,21.0b11110,16./,15.0b001,12.0,11./,10.*,8./,7.PD,6.*,5.P1,4.Source::f::vsub r
1159 31.*,26.Dest,21.0b11110,16./,15.0b001,12.1,11./,10.*,8./,7.PD,6.*,5.P1,4./::f::vsub l
1160
1161
1162 // wrcr - see swcr, creg, source, r0
1163
1164
1165 // xnor
1166 void::function::do_xnor:signed32 *rDest, signed32 Source1, signed32 Source2
1167         unsigned32 result = ~ (Source1 ^ Source2);
1168         TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
1169         *rDest = result;
1170 31.Dest,26.Source2,21.0b0011001,14.UnsignedImmediate::::xnor i
1171         do_xnor (_SD, rDest, vSource1, rSource2);
1172 31.Dest,26.Source2,21.0b110011001,12.0,11./,4.Source1::::xnor r
1173         do_xnor (_SD, rDest, rSource1, rSource2);
1174 31.Dest,26.Source2,21.0b110011001,12.1,11./::::xnor l
1175         long_immediate (LongUnsignedImmediate);
1176         do_xnor (_SD, rDest, LongUnsignedImmediate, rSource2);
1177
1178
1179 // xor
1180 void::function::do_xor:signed32 *rDest, signed32 Source1, signed32 Source2
1181         unsigned32 result = Source1 ^ Source2;
1182         TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
1183         *rDest = result;
1184 31.Dest,26.Source2,21.0b0010110,14.UnsignedImmediate::::xor i
1185         do_xor (_SD, rDest, vSource1, rSource2);
1186 31.Dest,26.Source2,21.0b110010110,12.0,11./,4.Source1::::xor r
1187         do_xor (_SD, rDest, rSource1, rSource2);
1188 31.Dest,26.Source2,21.0b110010110,12.1,11./::::xor l
1189         long_immediate (LongUnsignedImmediate);
1190         do_xor (_SD, rDest, LongUnsignedImmediate, rSource2);