sim/tic80/insns

   1 // Texas Instruments TMS320C80 (MVP) Simulator.
   2 // Copyright (C) 1997 Free Software Foundation, Inc.
   3 // Contributed by Cygnus Support.
   4 //
   5 // This file is part of GDB, the GNU debugger.
   6 //
   7 // This program is free software; you can redistribute it and/or modify
   8 // it under the terms of the GNU General Public License as published by
   9 // the Free Software Foundation; either version 2, or (at your option)
  10 // any later version.
  11 //
  12 // This program is distributed in the hope that it will be useful,
  13 // but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 // GNU General Public License for more details.
  16 //
  17 // You should have received a copy of the GNU General Public License along
  18 // with this program; if not, write to the Free Software Foundation, Inc.,
  19 // 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21
  22 // The following is called when ever an illegal instruction is encountered.
  23 ::internal::illegal
  24         engine_error (SD, CPU, cia, "illegal instruction at 0x%lx", cia.ip);
  25 // The following is called when ever an FP op is attempted with FPU disabled.
  26 ::internal::fp_unavailable
  27         engine_error (SD, CPU, cia, "floating-point unavailable at 0x%lx", cia.ip);
  28
  29 // Signed Integer Add - add source1, source2, dest
  30 void::function::do_add:signed32 *rDest, signed32 Source1, signed32 Source2
  31         ALU_BEGIN (Source1);
  32         ALU_ADD (Source2);
  33         ALU_END (*rDest);
  34         TRACE_ALU3 (MY_INDEX, *rDest, Source1, Source2);
  35         /* FIXME - a signed add may cause an exception */
  36 31.Dest,26.Source2,21.0b101100,15.0,14.SignedImmediate::::add i
  37         do_add (_SD, rDest, vSource1, rSource2);
  38 31.Dest,26.Source2,21.0b11101100,13.0,12.0,11./,4.Source1::::add r
  39         do_add (_SD, rDest, rSource1, rSource2);
  40 31.Dest,26.Source2,21.0b11101100,13.0,12.1,11./::::add l
  41         long_immediate (LongSignedImmediate);
  42         do_add (_SD, rDest, LongSignedImmediate, rSource2);
  43
  44
  45 // Unsigned Integer Add - addu source1, source2, dest
  46 void::function::do_addu:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
  47         unsigned32 result = Source1 + Source2;
  48         TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
  49         *rDest = result;
  50
  51 31.Dest,26.Source2,21.0b101100,15.1,14.SignedImmediate::::addu i
  52         do_addu (_SD, rDest, vSource1, rSource2);
  53 31.Dest,26.Source2,21.0b11101100,13.1,12.0,11./,4.Source1::::addu r
  54         do_addu (_SD, rDest, rSource1, rSource2);
  55 31.Dest,26.Source2,21.0b11101100,13.1,12.1,11./::::addu l
  56         long_immediate (LongSignedImmediate);
  57         do_addu (_SD, rDest, LongSignedImmediate, rSource2);
  58
  59
  60 void::function::do_and:signed32 *rDest, signed32 Source1, signed32 Source2
  61         unsigned32 result = Source1 & Source2;
  62         TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
  63         *rDest = result;
  64
  65
  66 // and, and.tt
  67 31.Dest,26.Source2,21.0b0010001,14.UnsignedImmediate::::and.tt i
  68         do_and (_SD, rDest, vSource1, rSource2);
  69 31.Dest,26.Source2,21.0b110010001,12.0,11./,4.Source1::::and.tt r
  70         do_and (_SD, rDest, rSource1, rSource2);
  71 31.Dest,26.Source2,21.0b110010001,12.1,11./::::and.tt l
  72         long_immediate (LongSignedImmediate);
  73         do_and (_SD, rDest, LongSignedImmediate, rSource2);
  74
  75
  76 // and.ff
  77 31.Dest,26.Source2,21.0b0011000,14.UnsignedImmediate::::and.ff i
  78         do_and (_SD, rDest, ~vSource1, ~rSource2);
  79 31.Dest,26.Source2,21.0b110011000,12.0,11./,4.Source1::::and.ff r
  80         do_and (_SD, rDest, ~rSource1, ~rSource2);
  81 31.Dest,26.Source2,21.0b110011000,12.1,11./::::and.ff l
  82         long_immediate (LongSignedImmediate);
  83         do_and (_SD, rDest, ~LongSignedImmediate, ~rSource2);
  84
  85
  86 // and.ft
  87 31.Dest,26.Source2,21.0b0010100,14.UnsignedImmediate::::and.ft i
  88         do_and (_SD, rDest, ~vSource1, rSource2);
  89 31.Dest,26.Source2,21.0b110010100,12.0,11./,4.Source1::::and.ft r
  90         do_and (_SD, rDest, ~rSource1, rSource2);
  91 31.Dest,26.Source2,21.0b110010100,12.1,11./::::and.ft l
  92         long_immediate (LongSignedImmediate);
  93         do_and (_SD, rDest, ~LongSignedImmediate, rSource2);
  94
  95
  96 // and.tf
  97 31.Dest,26.Source2,21.0b0010010,14.UnsignedImmediate::::and.tf i
  98         do_and (_SD, rDest, vSource1, ~rSource2);
  99 31.Dest,26.Source2,21.0b110010010,12.0,11./,4.Source1::::and.tf r
 100         do_and (_SD, rDest, rSource1, ~rSource2);
 101 31.Dest,26.Source2,21.0b110010010,12.1,11./::::and.tf l
 102         long_immediate (LongSignedImmediate);
 103         do_and (_SD, rDest, LongSignedImmediate, ~rSource2);
 104
 105
 106 // bbo.[a]
 107 instruction_address::function::do_bbo:instruction_address nia, int bitnum, unsigned32 source, int annul, unsigned32 offset
 108         int jump_p;
 109         unsigned32 target = cia.ip + 4 * offset;
 110         bitnum = (~ bitnum) & 0x1f;
 111         if (MASKED32 (source, bitnum, bitnum))
 112           {
 113             if (annul)
 114               nia.ip = -1;
 115             nia.dp = target;
 116             jump_p = 1;
 117           }
 118         else
 119           jump_p = 0;
 120         TRACE_COND_BR(MY_INDEX, jump_p, bitnum, target);
 121         return nia;
 122 31.BITNUM,26.Source,21.0b100101,15.A,14.SignedOffset::::bbo i
 123         nia = do_bbo (_SD, nia, BITNUM, rSource, A, vSignedOffset);
 124 31.BITNUM,26.Source,21.0b11100101,13.A,12.0,11./,4.IndOff::::bbo r
 125         nia = do_bbo (_SD, nia, BITNUM, rSource, A, rIndOff);
 126 31.BITNUM,26.Source,21.0b11100101,13.A,12.1,11./::::bbo l
 127         long_immediate (LongSignedImmediate);
 128         nia = do_bbo (_SD, nia, BITNUM, rSource, A, LongSignedImmediate);
 129
 130
 131 // bbz[.a]
 132 instruction_address::function::do_bbz:instruction_address nia, int bitnum, unsigned32 source, int annul, unsigned32 offset
 133         int jump_p;
 134         unsigned32 target = cia.ip + 4 * offset;
 135         bitnum = (~ bitnum) & 0x1f;
 136         if (!MASKED32 (source, bitnum, bitnum))
 137           {
 138             if (annul)
 139               nia.ip = -1;
 140             nia.dp = target;
 141             jump_p = 1;
 142           }
 143         else
 144           jump_p = 0;
 145         TRACE_COND_BR(MY_INDEX, jump_p, bitnum, target);
 146         return nia;
 147 31.BITNUM,26.Source,21.0b100100,15.A,14.SignedOffset::::bbz i
 148         nia = do_bbz (_SD, nia, BITNUM, rSource, A, vSignedOffset);
 149 31.BITNUM,26.Source,21.0b11100100,13.A,12.0,11./,4.IndOff::::bbz r
 150         nia = do_bbz (_SD, nia, BITNUM, rSource, A, rIndOff);
 151 31.BITNUM,26.Source,21.0b11100100,13.A,12.1,11./::::bbz l
 152         long_immediate (LongSignedImmediate);
 153         nia = do_bbz (_SD, nia, BITNUM, rSource, A, LongSignedImmediate);
 154
 155
 156 // bcnd[.a]
 157 instruction_address::function::do_bcnd:instruction_address nia, int Cond, unsigned32 source, int annul, unsigned32 offset
 158         int condition;
 159         int size = EXTRACTED32 (Cond, 31 - 27, 30 - 27);
 160         int code = EXTRACTED32 (Cond, 29 - 27, 27 - 27);
 161         signed32 val = 0;
 162         unsigned32 target = cia.ip + 4 * offset;
 163         switch (size)
 164           {
 165           case 0: val = SEXT32 (source, 7); break;
 166           case 1: val = SEXT32 (source, 15); break;
 167           case 2: val = source; break;
 168           default: engine_error (SD, CPU, cia, "bcnd - reserved size");
 169           }
 170         switch (code)
 171           {
 172           case 0: condition = 0; break;
 173           case 1: condition = val > 0; break;
 174           case 2: condition = val == 0; break;
 175           case 3: condition = val >= 0; break;
 176           case 4: condition = val < 0; break;
 177           case 5: condition = val != 0; break;
 178           case 6: condition = val <= 0; break;
 179           default: condition = 1; break;
 180           }
 181         if (condition)
 182           {
 183             if (annul)
 184               nia.ip = -1;
 185             nia.dp = target;
 186           }
 187         TRACE_COND_BR(MY_INDEX, condition, source, target);
 188         return nia;
 189 31.Code,26.Source,21.0b100110,15.A,14.SignedOffset::::bcnd i
 190         nia = do_bcnd (_SD, nia, Code, rSource, A, vSignedOffset);
 191 31.Code,26.Source,21.0b11100110,13.A,12.0,11./,4.IndOff::::bcnd r
 192         nia = do_bcnd (_SD, nia, Code, rSource, A, rIndOff);
 193 31.Code,26.Source,21.0b11100110,13.A,12.1,11./::::bcnd l
 194         long_immediate (LongSignedImmediate);
 195         nia = do_bcnd (_SD, nia, Code, rSource, A, LongSignedImmediate);
 196
 197
 198 // br[.a] - see bbz[.a]
 199
 200
 201 // brcr
 202 sim_cia::function::do_brcr:instruction_address nia, int cr
 203         if (cr >= 0x4000 || !(CPU)->is_user_mode)
 204           {
 205             unsigned32 control = CR (cr);
 206             unsigned32 ie = control & 0x00000001;
 207             unsigned32 pc = control & 0xfffffffc;
 208             unsigned32 is_user_mode = control & 0x00000002;
 209             (CPU)->is_user_mode = is_user_mode;
 210             nia.dp = pc;
 211             if (ie)
 212               (CPU)->cr[IE_CR] |= IE_CR_IE;
 213             else
 214               (CPU)->cr[IE_CR] &= ~IE_CR_IE;
 215           }
 216         TRACE_UCOND_BR (MY_INDEX, nia.dp);
 217         return nia;
 218 31.//,27.0,26.//,21.0b0000110,14.UCRN::::brcr i
 219         nia = do_brcr (_SD, nia, UCRN);
 220 31.//,27.0,26.//,21.0b110000110,12.0,11./,4.INDCR::::brcr r
 221         nia = do_brcr (_SD, nia, UCRN);
 222 31.//,27.0,26.//,21.0b110000110,12.1,11./::::brcr l
 223         long_immediate (UnsignedControlRegisterNumber)
 224         nia = do_brcr (_SD, nia, UnsignedControlRegisterNumber);
 225
 226
 227 // bsr[.a]
 228 instruction_address::function::do_bsr:instruction_address nia, signed32 *rLink, int annul, unsigned32 offset
 229         if (annul)
 230           {
 231             *rLink = nia.ip;
 232             nia.ip = -1;
 233           }
 234         else
 235           *rLink = nia.ip + sizeof (instruction_word);
 236         nia.dp = cia.ip + 4 * offset;
 237         TRACE_UCOND_BR (MY_INDEX, nia.dp);
 238         return nia;
 239 31.Link,26./,21.0b100000,15.A,14.SignedOffset::::bsr i
 240         nia = do_bsr (_SD, nia, rLink, A, vSignedOffset);
 241 31.Link,26./,21.0b11100000,13.A,12.0,11./,4.IndOff::::bsr r
 242         nia = do_bsr (_SD, nia, rLink, A, rIndOff);
 243 31.Link,26./,21.0b11100000,13.A,12.1,11./::::bsr l
 244         long_immediate (LongSignedImmediate);
 245         nia = do_bsr (_SD, nia, rLink, A, LongSignedImmediate);
 246
 247
 248 // cmnd
 249 void::function::do_cmnd:signed32 source
 250         int Reset = EXTRACTED32 (source, 31, 31);
 251         int Halt = EXTRACTED32 (source, 30, 30);
 252         int Unhalt = EXTRACTED32 (source, 29, 29);
 253         /* int ICR = EXTRACTED32 (source, 28, 28); */
 254         /* int DCR = EXTRACTED32 (source, 27, 27); */
 255         int Task = EXTRACTED32 (source, 14, 14);
 256         int Msg = EXTRACTED32 (source, 13, 13);
 257         int VC = EXTRACTED32 (source, 10, 10);
 258         int TC = EXTRACTED32 (source, 9, 9);
 259         int MP = EXTRACTED32 (source, 8, 8);
 260         int PP = EXTRACTED32 (source, 3, 0);
 261         /* what is implemented? */
 262         if (PP != 0)
 263           engine_error (SD, CPU, cia, "0x%lx: cmnd - PPs not supported",
 264                         (unsigned long) cia.ip);
 265         if (VC != 0)
 266           engine_error (SD, CPU, cia, "0x%lx: cmnd - VC not supported",
 267                         (unsigned long) cia.ip);
 268         if (TC != 0)
 269           engine_error (SD, CPU, cia, "0x%lx: cmnd - TC not supported",
 270                         (unsigned long) cia.ip);
 271         if (MP)
 272           {
 273             if (Reset || Halt)
 274               engine_halt (SD, CPU, cia, sim_exited, 0);
 275             if (Unhalt)
 276               engine_error (SD, CPU, cia, "0x%lx: cmnd - Can not unhalt the MP",
 277                             (unsigned long) cia.ip);
 278             /* if (ICR || DCR); */
 279             if (Task)
 280               engine_error (SD, CPU, cia, "0x%lx: cmnd - Can not Task the MP",
 281                             (unsigned long) cia.ip);
 282             if (Msg)
 283               engine_error (SD, CPU, cia, "0x%lx: cmnd - Msg to MP not suported",
 284                             (unsigned long) cia.ip);
 285           }
 286         TRACE_SINK1 (MY_INDEX, source);
 287 31./,21.0b0000010,14.UI::::cmnd i
 288         do_cmnd (_SD, UI);
 289 31./,21.0b110000010,12.0,11./,4.Source::::cmnd r
 290         do_cmnd (_SD, rSource);
 291 31./,21.0b110000010,12.1,11./::::cmnd l
 292         long_immediate (LongUnsignedImmediate);
 293         do_cmnd (_SD, LongUnsignedImmediate);
 294
 295 // cmp
 296 unsigned32::function::cmp_vals:signed32 s1, unsigned32 u1, signed32 s2, unsigned32 u2
 297         unsigned32 field = 0;
 298         if (s1 == s2) field |= 0x001;
 299         if (s1 != s2) field |= 0x002;
 300         if (s1 >  s2) field |= 0x004;
 301         if (s1 <= s2) field |= 0x008;
 302         if (s1 <  s2) field |= 0x010;
 303         if (s1 >= s2) field |= 0x020;
 304         if (u1 >  u2) field |= 0x040;
 305         if (u1 <= u2) field |= 0x080;
 306         if (u1 <  u2) field |= 0x100;
 307         if (u1 >= u2) field |= 0x200;
 308         return field;
 309 void::function::do_cmp:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
 310         unsigned32 field = 0;
 311         field |= cmp_vals (_SD, Source1, Source1, Source2, Source2) << 20;
 312         field |= cmp_vals (_SD, (signed16)Source1, (unsigned16)Source1,
 313                            (signed16)Source2, (unsigned16)Source2) << 10;
 314         field |= cmp_vals (_SD, (signed8)Source1, (unsigned8)Source1,
 315                             (signed8)Source2, (unsigned8)Source2);
 316         TRACE_ALU3 (MY_INDEX, field, Source1, Source2);
 317         *rDest = field;
 318 31.Dest,26.Source2,21.0b1010000,14.SignedImmediate::::cmp i
 319         do_cmp (_SD, rDest, vSource1, rSource2);
 320 31.Dest,26.Source2,21.0b111010000,12.0,11./,4.Source1::::cmp r
 321         do_cmp (_SD, rDest, rSource1, rSource2);
 322 31.Dest,26.Source2,21.0b111010000,12.1,11./::::cmp l
 323         long_immediate (LongSignedImmediate);
 324         do_cmp (_SD, rDest, LongSignedImmediate, rSource2);
 325
 326
 327 // dcache
 328 31./,27.F,26.Source2,21.0b0111,17.M,16.0b00,14.SignedOffset::::dcache i
 329         TRACE_NOP (MY_INDEX);
 330         /* NOP */
 331 31./,27.F,26.Source2,21.0b110111,15.M,14.0b00,12.0,11./,4.Source1::::dcache r
 332         TRACE_NOP (MY_INDEX);
 333         /* NOP */
 334 31./,27.F,26.Source2,21.0b110111,15.M,14.0b00,12.1,11./::::dcache l
 335         long_immediate (LongSignedImmediate);
 336         LongSignedImmediate++;
 337         TRACE_NOP (MY_INDEX);
 338         /* NOP */
 339
 340
 341 // dld[{.b|.h|.d}]
 342 void::function::do_dld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
 343         do_ld (_SD, Dest, Base, rBase, m, sz, S, Offset);
 344 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dld r
 345         do_dld (_SD, Dest, rBase, &GPR(Base), m, sz, S, rIndOff);
 346 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.1,9./::::dld l
 347         long_immediate (LongSignedImmediateOffset);
 348         do_dld (_SD, Dest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
 349
 350
 351 // dld.u[{.b|.h|.d}]
 352 void::function::do_dld_u:unsigned32 *rDest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
 353         do_ld_u (_SD, rDest, Base, rBase, m, sz, S, Offset);
 354 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dld.u r
 355         do_dld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, rIndOff);
 356 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.1,9./::::dld.u l
 357         long_immediate (LongSignedImmediateOffset);
 358         do_dld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
 359
 360
 361 // dst[{.b|.h|.d}]
 362 void::function::do_dst:int Source, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
 363         do_st (_SD, Source, Base, rBase, m, sz, S, Offset);
 364 31.Source,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dst r
 365         do_dst (_SD, Source, rBase, &GPR(Base), m, sz, S, rIndOff);
 366 31.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.1,9./::::dst l
 367         long_immediate (LongSignedImmediateOffset);
 368         do_dst (_SD, Source, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
 369
 370
 371 // estop
 372 31./,21.0b1111111,14.1,13.0,12.0,11./::::estop
 373
 374 // etrap
 375 31./,27.1,26./,21.0b0000001,14.UTN::::etrap i
 376 31./,27.1,26./,21.0b110000001,12.0,11./,4.iUTN::::etrap r
 377 31./,27.1,26./,21.0b110000001,12.1,11./::::etrap l
 378
 379
 380 // exts - see shift.ds
 381
 382
 383 // extu - see shift.dz
 384
 385
 386 sim_fpu::function::get_fp_reg:int reg, unsigned32 val, int precision
 387         switch (precision)
 388           {
 389           case 0: /* single */
 390             if (reg == 0)
 391               return sim_fpu_32to (0);
 392             else
 393               return sim_fpu_32to (val);
 394           case 1: /* double */
 395             if (reg < 0)
 396               return sim_fpu_32to (val);
 397             if (reg & 1)
 398               engine_error (SD, CPU, cia, "DP FP register must be even");
 399             if (reg <= 1)
 400               engine_error (SD, CPU, cia, "DP FP register must be >= 2");
 401             return sim_fpu_64to (INSERTED64 (GPR(reg + 1), 63, 32)
 402                                  | INSERTED64 (GPR(reg), 31, 0));
 403           case 2: /* 32 bit signed integer */
 404             if (reg == 0)
 405               return sim_fpu_32to (0);
 406             else
 407               return sim_fpu_d2 ((signed32) val);
 408           case 3: /* 32 bit unsigned integer */
 409             if (reg == 0)
 410               return sim_fpu_32to (0);
 411             else
 412               return sim_fpu_d2 ((unsigned32) val);
 413           default:
 414             engine_error (SD, CPU, cia, "Unsupported FP precision");
 415           }
 416         return sim_fpu_32to (0);
 417 void::function::set_fp_reg:int Dest, sim_fpu val, int PD
 418         switch (PD)
 419           {
 420           case 0: /* single */
 421             {
 422               GPR (Dest) = sim_fpu_to32 (val);
 423               break;
 424             }
 425           case 1: /* double */
 426             {
 427               unsigned64 v = *(unsigned64*) &val;
 428               if (Dest & 1)
 429                 engine_error (SD, CPU, cia, "DP FP Dest register must be even");
 430               if (Dest <= 1)
 431                 engine_error (SD, CPU, cia, "DP FP Dest register must be >= 2");
 432               GPR (Dest) = EXTRACTED64 (v, 21, 0);
 433               GPR (Dest + 1) = EXTRACTED64 (v, 63, 32);
 434               break;
 435             }
 436           case 2: /* signed */
 437             /* FIXME - rounding */
 438             GPR (Dest) = sim_fpu_2d (val);
 439             break;
 440           case 3: /* unsigned */
 441             /* FIXME - rounding */
 442             GPR (Dest) = sim_fpu_2d (val);
 443             break;
 444           default:
 445             engine_error (SD, CPU, cia, "Unsupported FP precision");
 446           }
 447
 448 // fadd.{s|d}{s|d}{s|d}
 449 void::function::do_fadd:int Dest, int PD, sim_fpu s1, sim_fpu s2
 450         sim_fpu ans = sim_fpu_add (s1, s2);
 451         TRACE_FPU3 (MY_INDEX, ans, s1, s2);
 452         set_fp_reg (_SD, Dest, ans, PD);
 453 31.Dest,26.Source2,21.0b111110000,12.0,11.r,10.PD,8.P2,6.P1,4.Source1::f::fadd r
 454         do_fadd (_SD, Dest, PD,
 455                  get_fp_reg (_SD, Source1, rSource1, P1),
 456                  get_fp_reg (_SD, Source2, rSource2, P2));
 457 31.Dest,26.Source2,21.0b111110000,12.1,11.r,10.PD,8.P2,6.P1,4./::f::fadd l
 458         long_immediate (SinglePrecisionFloatingPoint);
 459         do_fadd (_SD, Dest, PD,
 460                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
 461                  get_fp_reg (_SD, Source2, rSource2, P2));
 462
 463
 464 // fcmp.{s|d}{s|d}{s|d}
 465 void::function::do_fcmp:unsigned32 *rDest, sim_fpu s1, sim_fpu s2
 466         *rDest = 0;
 467         if (sim_fpu_is_nan (s1) || sim_fpu_is_nan (s2))
 468           *rDest |= BIT32 (30);
 469         else
 470           {
 471             *rDest |= BIT32 (31);
 472             if (sim_fpu_cmp (s1, s2) == 0) *rDest |= BIT32(20);
 473             if (sim_fpu_cmp (s1, s2) != 0) *rDest |= BIT32(21);
 474             if (sim_fpu_cmp (s1, s2) >  0) *rDest |= BIT32(22);
 475             if (sim_fpu_cmp (s1, s2) <= 0) *rDest |= BIT32(23);
 476             if (sim_fpu_cmp (s1, s2) <  0) *rDest |= BIT32(24);
 477             if (sim_fpu_cmp (s1, s2) >= 0) *rDest |= BIT32(25);
 478             if (sim_fpu_cmp (s1, sim_fpu_32to (0)) < 0
 479                 || sim_fpu_cmp (s1, s2) > 0) *rDest |= BIT32(26);
 480             if (sim_fpu_cmp (sim_fpu_32to (0), s1) < 0
 481                 && sim_fpu_cmp (s1, s2) < 0) *rDest |= BIT32(27);
 482             if (sim_fpu_cmp (sim_fpu_32to (0), s1) <= 0
 483                 && sim_fpu_cmp (s1, s2) <= 0) *rDest |= BIT32(28);
 484             if (sim_fpu_cmp (s1, sim_fpu_32to (0)) <= 0
 485                 || sim_fpu_cmp (s1, s2) >= 0) *rDest |= BIT32(29);
 486           }
 487         TRACE_FPU2I (MY_INDEX, *rDest, s1, s2);
 488 31.Dest,26.Source2,21.0b111110101,12.0,11./,10.0,8.P2,6.P1,4.Source1::f::fcmp r
 489         do_fcmp (_SD, rDest,
 490                  get_fp_reg (_SD, Source1, rSource1, P1),
 491                  get_fp_reg (_SD, Source2, rSource2, P2));
 492 31.Dest,26.Source2,21.0b111110101,12.1,11./,10.0,8.P2,6.P1,4./::f::fcmp l
 493         long_immediate (SinglePrecisionFloatingPoint);
 494         do_fcmp (_SD, rDest,
 495                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
 496                  get_fp_reg (_SD, Source2, rSource2, P2));
 497
 498
 499
 500 // fdiv.{s|d}{s|d}{s|d}
 501 void::function::do_fdiv:int Dest, int PD, sim_fpu s1, sim_fpu s2
 502         sim_fpu ans = sim_fpu_div (s1, s2);
 503         TRACE_FPU3 (MY_INDEX, ans, s1, s2);
 504         set_fp_reg (_SD, Dest, ans, PD);
 505 31.Dest,26.Source2,21.0b111110011,12.0,11./,10.PD,8.P2,6.P1,4.Source1::f::fdiv r
 506         do_fdiv (_SD, Dest, PD,
 507                  get_fp_reg (_SD, Source1, rSource1, P1),
 508                  get_fp_reg (_SD, Source2, rSource2, P2));
 509 31.Dest,26.Source2,21.0b111110011,12.1,11./,10.PD,8.P2,6.P1,4./::f::fdiv l
 510         long_immediate (SinglePrecisionFloatingPoint);
 511         do_fdiv (_SD, Dest, PD,
 512                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
 513                  get_fp_reg (_SD, Source2, rSource2, P2));
 514
 515
 516 // fmpy.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 517 void::function::do_fmpy:int Dest, int PD, sim_fpu s1, sim_fpu s2
 518         sim_fpu ans = sim_fpu_mul (s1, s2);
 519         TRACE_FPU3 (MY_INDEX, ans, s1, s2);
 520         set_fp_reg (_SD, Dest, ans, PD);
 521 31.Dest,26.Source2,21.0b111110010,12.0,11./,10.PD,8.P2,6.P1,4.Source1::f::fmpy r
 522         do_fmpy (_SD, Dest, PD,
 523                  get_fp_reg (_SD, Source1, rSource1, P1),
 524                  get_fp_reg (_SD, Source2, rSource2, P2));
 525 31.Dest,26.Source2,21.0b111110010,12.1,11./,10.PD,8.P2,6.P1,4./::f::fmpy l
 526         long_immediate (SinglePrecisionFloatingPoint);
 527         do_fmpy (_SD, Dest, PD,
 528                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
 529                  get_fp_reg (_SD, Source2, rSource2, P2));
 530
 531
 532 // frndm.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 533 void::function::do_frnd:int Dest, int PD, sim_fpu s1
 534         set_fp_reg (_SD, Dest, s1, PD);
 535 31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b11,6.P1,4.Source::f::frndm r
 536         do_frnd (_SD, Dest, PD,
 537                  get_fp_reg (_SD, Source, rSource, P1));
 538 31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b11,6.P1,4./::f::frndm l
 539         long_immediate (SinglePrecisionFloatingPoint);
 540         do_frnd (_SD, Dest, PD,
 541                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
 542
 543
 544 // frndn.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 545 31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b00,6.P1,4.Source::f::frndn r
 546         do_frnd (_SD, Dest, PD,
 547                  get_fp_reg (_SD, Source, rSource, P1));
 548 31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b00,6.P1,4./::f::frndn l
 549         long_immediate (SinglePrecisionFloatingPoint);
 550         do_frnd (_SD, Dest, PD,
 551                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
 552
 553
 554 // frndp.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 555 31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b10,6.P1,4.Source::f::frndp r
 556         do_frnd (_SD, Dest, PD,
 557                  get_fp_reg (_SD, Source, rSource, P1));
 558 31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b10,6.P1,4./::f::frndp l
 559         long_immediate (SinglePrecisionFloatingPoint);
 560         do_frnd (_SD, Dest, PD,
 561                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
 562
 563
 564 // frndz.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 565 31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b01,6.P1,4.Source::f::frndz r
 566         do_frnd (_SD, Dest, PD,
 567                  get_fp_reg (_SD, Source, rSource, P1));
 568 31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b01,6.P1,4./::f::frndz l
 569         long_immediate (SinglePrecisionFloatingPoint);
 570         do_frnd (_SD, Dest, PD,
 571                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
 572
 573
 574 // fsqrt.{s|d}{s|d}{s|d}
 575 #void::function::do_fsqrt:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
 576 #       sim_io_error ("fsqrt");
 577 31.Dest,26.Source2,21.0b111110111,12.0,11./,10.PD,8.//,6.P1,4.Source1::f::fsqrt r
 578 #       do_fsqrt (_SD, rDest, rSource1, rSource2);
 579 31.Dest,26.Source2,21.0b111110111,12.1,11./,10.PD,8.//,6.P1,4./::f::fsqrt l
 580 #       do_fsqrt (_SD, rDest, LongSignedImmediate, rSource2);
 581
 582
 583 // fsub.{s|d}{s|d}{s|d}
 584 void::function::do_fsub:int Dest, int PD, sim_fpu s1, sim_fpu s2
 585         sim_fpu ans = sim_fpu_sub (s1, s2);
 586         TRACE_FPU3 (MY_INDEX, ans, s1, s2);
 587         set_fp_reg (_SD, Dest, ans, PD);
 588 31.Dest,26.Source2,21.0b111110001,12.0,11.r,10.PD,8.P2,6.P1,4.Source1::f::fsub r
 589         do_fsub (_SD, Dest, PD,
 590                  get_fp_reg (_SD, Source1, rSource1, P1),
 591                  get_fp_reg (_SD, Source2, rSource2, P2));
 592 31.Dest,26.Source2,21.0b111110001,12.1,11.r,10.PD,8.P2,6.P1,4./::f::fsub l
 593         long_immediate (SinglePrecisionFloatingPoint);
 594         do_fsub (_SD, Dest, PD,
 595                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
 596                  get_fp_reg (_SD, Source2, rSource2, P2));
 597
 598
 599 // illop
 600 31./,21.0b0000000,14./::::illop
 601 31./,21.0b111111111,12./::::illop l
 602
 603
 604 // ins - see sl.im
 605
 606
 607 // jsr[.a]
 608 instruction_address::function::do_jsr:instruction_address nia, signed32 *rLink, int annul, unsigned32 offset, unsigned32 base
 609         TRACE_UCOND_BR (MY_INDEX, nia.ip);
 610         if (annul)
 611           {
 612             *rLink = nia.ip;
 613             nia.ip = -1;
 614           }
 615         else
 616           *rLink = nia.ip + sizeof (instruction_word);
 617         nia.dp = offset + base;
 618         if (nia.dp & 0x3)
 619           engine_error (SD, CPU, cia,
 620                         "0x%lx: destination address 0x%lx misaligned",
 621                         (unsigned long) cia.ip,
 622                         (unsigned long) nia.dp);
 623         return nia;
 624 31.Link,26.Base,21.0b100010,15.A,14.SignedOffset::::jsr i
 625         nia = do_jsr (_SD, nia, rLink, A, vSignedOffset, rBase);
 626 31.Link,26.Base,21.0b11100010,13.A,12.0,11./,4.Source1::::jsr r
 627         nia = do_jsr (_SD, nia, rLink, A, rSource1, rBase);
 628 31.Link,26.Base,21.0b11100010,13.A,12.1,11./::::jsr l
 629         long_immediate (LongSignedImmediate);
 630         nia = do_jsr (_SD, nia, rLink, A, LongSignedImmediate, rBase);
 631
 632
 633 // ld[{.b.h.d}]
 634 void::function::do_ld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
 635         unsigned32 addr;
 636         switch (sz)
 637           {
 638           case 0:
 639             addr = Base + (S ? (Offset << 0) : Offset);
 640             if (m)
 641               *rBase = addr;
 642             GPR(Dest) = MEM (signed, addr, 1);
 643             break;
 644           case 1:
 645             addr = Base + (S ? (Offset << 1) : Offset);
 646             if (m)
 647               *rBase = addr;
 648             GPR(Dest) = MEM (signed, addr, 2);
 649             break;
 650           case 2:
 651             addr = Base + (S ? (Offset << 2) : Offset);
 652             if (m)
 653               *rBase = addr;
 654             GPR(Dest) = MEM (signed, addr, 4);
 655             break;
 656           case 3:
 657             {
 658               signed64 val;
 659               if (Dest & 0x1)
 660                 engine_error (SD, CPU, cia, "0x%lx: ld.d to odd register %d",
 661                               cia.ip, Dest);
 662               addr = Base + (S ? (Offset << 3) : Offset);
 663               if (m)
 664                 *rBase = addr;
 665               val = MEM (signed, addr, 8);
 666               GPR(Dest + 1) = VH4_8 (val);
 667               GPR(Dest + 0) = VL4_8 (val);
 668             }
 669             break;
 670           default:
 671             addr = -1;
 672             engine_error (SD, CPU, cia, "ld - invalid sz %d", sz);
 673           }
 674         TRACE_LD (MY_INDEX, m, S, GPR(Dest), Base, Offset);
 675 31.Dest,26.Base,21.0b0100,17.m,16.sz,14.SignedOffset::::ld i
 676         do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, 0, vSignedOffset);
 677 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::ld r
 678         do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, S, rIndOff);
 679 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.0,9./::::ld l
 680         long_immediate (LongSignedImmediateOffset);
 681         do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
 682
 683
 684 // ld.u[{.b.h.d}]
 685 void::function::do_ld_u:unsigned32 *rDest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
 686         unsigned32 addr;
 687         switch (sz)
 688           {
 689           case 0:
 690             addr = Base + (S ? (Offset << 0) : Offset);
 691             *rDest = MEM (unsigned, addr, 1);
 692             break;
 693           case 1:
 694             addr = Base + (S ? (Offset << 1) : Offset);
 695             *rDest = MEM (unsigned, addr, 2);
 696             break;
 697           default:
 698             addr = -1;
 699             engine_error (SD, CPU, cia, "ld.u - invalid sz %d", sz);
 700           }
 701         if (m)
 702           *rBase = addr;
 703         TRACE_LD (MY_INDEX, m, S, *rDest, Base, Offset);
 704 31.Dest,26.Base,21.0b0101,17.m,16.sz,14.SignedOffset::::ld.u i
 705         do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, 0, vSignedOffset);
 706 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::ld.u r
 707         do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, rIndOff);
 708 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.0,9./::::ld.u l
 709         long_immediate (LongSignedImmediateOffset);
 710         do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
 711
 712
 713 // lmo
 714 31.Dest,26.Source,21.0b111111000,12.0,11./::::lmo
 715         int b;
 716         for (b = 0; b < 32; b++)
 717           if (rSource & BIT32 (31 - b))
 718             break;
 719         TRACE_ALU2 (MY_INDEX, b, rSource);
 720         *rDest = b;
 721
 722
 723 // nop - see rdcr 0, r0
 724
 725
 726 void::function::do_or:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
 727         unsigned32 result = Source1 | Source2;
 728         TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
 729         *rDest = result;
 730
 731
 732 // or, or.tt
 733 31.Dest,26.Source2,21.0b0010111,14.UnsignedImmediate::::or.tt i
 734         do_or (_SD, rDest, vSource1, rSource2);
 735 31.Dest,26.Source2,21.0b110010111,12.0,11./,4.Source1::::or.tt r
 736         do_or (_SD, rDest, rSource1, rSource2);
 737 31.Dest,26.Source2,21.0b110010111,12.1,11./::::or.tt l
 738         long_immediate (LongUnsignedImmediate);
 739         do_or (_SD, rDest, LongUnsignedImmediate, rSource2);
 740
 741
 742 // or.ff
 743 31.Dest,26.Source2,21.0b0011110,14.UnsignedImmediate::::or.ff i
 744         do_or (_SD, rDest, ~vSource1, ~rSource2);
 745 31.Dest,26.Source2,21.0b110011110,12.0,11./,4.Source1::::or.ff r
 746         do_or (_SD, rDest, ~rSource1, ~rSource2);
 747 31.Dest,26.Source2,21.0b110011110,12.1,11./::::or.ff l
 748         long_immediate (LongUnsignedImmediate);
 749         do_or (_SD, rDest, ~LongUnsignedImmediate, ~rSource2);
 750
 751
 752 // or.ft
 753 31.Dest,26.Source2,21.0b0011101,14.UnsignedImmediate::::or.ft i
 754         do_or (_SD, rDest, ~vSource1, rSource2);
 755 31.Dest,26.Source2,21.0b110011101,12.0,11./,4.Source1::::or.ft r
 756         do_or (_SD, rDest, ~rSource1, rSource2);
 757 31.Dest,26.Source2,21.0b110011101,12.1,11./::::or.ft l
 758         long_immediate (LongUnsignedImmediate);
 759         do_or (_SD, rDest, ~LongUnsignedImmediate, rSource2);
 760
 761
 762 // or.tf
 763 31.Dest,26.Source2,21.0b0011011,14.UnsignedImmediate::::or.tf i
 764         do_or (_SD, rDest, vSource1, ~rSource2);
 765 31.Dest,26.Source2,21.0b110011011,12.0,11./,4.Source1::::or.tf r
 766         do_or (_SD, rDest, rSource1, ~rSource2);
 767 31.Dest,26.Source2,21.0b110011011,12.1,11./::::or.tf l
 768         long_immediate (LongUnsignedImmediate);
 769         do_or (_SD, rDest, LongUnsignedImmediate, ~rSource2);
 770
 771
 772 // rdcr
 773 void::function::do_rdcr:unsigned32 Dest, int cr
 774         TRACE_SINK2 (MY_INDEX, Dest, cr);
 775         GPR (Dest) = CR (cr);
 776 31.Dest,26.0,21.0b0000100,14.UCRN::::rdcr i
 777         do_rdcr (_SD, Dest, UCRN);
 778 31.Dest,26.0,21.0b110000100,12.0,11./,4.INDCR::::rdcr r
 779         do_rdcr (_SD, Dest, UCRN);
 780 31.Dest,26.0,21.0b110000100,12.1,11./::::rdcr l
 781         long_immediate (UnsignedControlRegisterNumber);
 782         do_rdcr (_SD, Dest, UnsignedControlRegisterNumber);
 783
 784
 785 // rmo
 786 31.Dest,26.Source,21.0b111111001,12.0,11./::::rmo
 787         int b;
 788         for (b = 0; b < 32; b++)
 789           if (rSource & BIT32 (b))
 790             break;
 791         if (b < 32)
 792           b = 31 - b;
 793         TRACE_ALU2 (MY_INDEX, b, rSource);
 794         *rDest = b;
 795
 796
 797 // rotl - see sl.dz
 798
 799
 800 // rotr - see sl.dz
 801
 802
 803 // shl - see sl.iz
 804
 805
 806 // sl.{d|e|i}{m|s|z}
 807 void::function::do_shift:int Dest, int Source, int Merge, int i, int n, int EndMask, int Rotate
 808         /* see 10-30 for a reasonable description */
 809         unsigned32 input = GPR (Source);
 810         unsigned32 rotated;
 811         unsigned32 endmask;
 812         unsigned32 shiftmask;
 813         unsigned32 cm;
 814         int nRotate;
 815         /* rotate the source */
 816         if (n)
 817           {
 818             rotated = ROTR32 (GPR (Source), Rotate);
 819             nRotate = (- Rotate) & 31;
 820           }
 821         else
 822           {
 823             rotated = ROTL32 (GPR (Source), Rotate);
 824             nRotate = Rotate;
 825           }
 826         /* form the end mask */
 827         if (EndMask == 0)
 828           endmask = ~ (unsigned32)0;
 829         else
 830           endmask = (1 << EndMask) - 1;
 831         if (i)
 832           endmask = ~endmask;
 833         /* form the shiftmask */
 834         switch (Merge)
 835           {
 836           case 0: case 1: case 2:
 837             shiftmask = ~ (unsigned32)0;        /* disabled */
 838             break;
 839           case 3: case 4: case 5:
 840             shiftmask = ((1 << nRotate) - 1);   /* enabled */
 841             break;
 842           case 6: case 7:
 843             shiftmask = ~((1 << nRotate) - 1);  /* inverted */
 844             break;
 845           default:
 846             engine_error (SD, CPU, cia,
 847                           "0x%lx: Invalid merge (%d) for shift",
 848                           cia.ip, Source);
 849             shiftmask = 0;
 850           }
 851         /* and the composite mask */
 852         cm = shiftmask & endmask;
 853         /* and merge */
 854         switch (Merge)
 855           {
 856           case 0: case 3: case 6:               /* zero */
 857             GPR (Dest) = rotated & cm;
 858             break;
 859           case 1: case 4: case 7:               /* merge */
 860             GPR (Dest) = (rotated & cm) | (GPR (Dest) & ~cm);
 861             break;
 862           case 2: case 5:                       /* sign */
 863             {
 864               int b;
 865               GPR (Dest) = rotated & cm;
 866               for (b = 1; b <= 31; b++)
 867                 if (!MASKED32 (cm, b, b))
 868                   GPR (Dest) |= INSERTED32 (EXTRACTED32 (GPR (Dest), b - 1, b - 1),
 869                                             b, b);
 870             }
 871             break;
 872           default:
 873             engine_error (SD, CPU, cia,
 874                           "0x%lx: Invalid merge (%d)",
 875                           cia.ip, Source);
 876
 877           }
 878         TRACE_SHIFT (MY_INDEX, GPR (Dest), input, i, n, Merge, EndMask, Rotate);
 879 31.Dest,26.Source,21.0b0001,17.Merge,14./,11.i,10.n,9.EndMask,4.Rotate::::sl i
 880         do_shift (_SD, Dest, Source, Merge, i, n, EndMask, Rotate);
 881 31.Dest,26.Source,21.0b110001,15.Merge,12.0,11.i,10.n,9.EndMask,4.RotReg::::sl r
 882         do_shift (_SD, Dest, Source, Merge, i, n, EndMask, GPR (RotReg) & 31);
 883
 884
 885 // sli.{d|e|i}{m|s|z} - see shift
 886
 887
 888 // sr.{d|e|i}{m|s|z} - see shift
 889
 890
 891 // sra - see sr.es - see shift
 892
 893
 894 // sri.{d|e|i}{m|s|z} - see shift
 895
 896
 897 // srl - see sr.ez
 898
 899
 900 // st[{.b|.h|.d}]
 901 void::function::do_st:int Source, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
 902         unsigned32 addr;
 903         switch (sz)
 904           {
 905           case 0:
 906             addr = Base + (S ? (Offset << 0) : Offset);
 907             STORE (addr, 1, GPR(Source));
 908             break;
 909           case 1:
 910             addr = Base + (S ? (Offset << 1) : Offset);
 911             STORE (addr, 2, GPR(Source));
 912             break;
 913           case 2:
 914             addr = Base + (S ? (Offset << 2) : Offset);
 915             STORE (addr, 4, GPR(Source));
 916             break;
 917           case 3:
 918             {
 919               signed64 val;
 920               if (Source & 0x1)
 921                 engine_error (SD, CPU, cia,
 922                               "0x%lx: st.d with odd source register %d",
 923                               cia.ip, Source);
 924               addr = Base + (S ? (Offset << 3) : Offset);
 925               val = (V4_H8 (GPR(Source + 1)) | V4_L8 (GPR(Source)));
 926               STORE (addr, 8, val);
 927             }
 928             break;
 929           default:
 930             addr = -1;
 931             engine_error (SD, CPU, cia, "st - invalid sz %d", sz);
 932           }
 933         if (m)
 934           *rBase = addr;
 935         TRACE_ST (MY_INDEX, m, S, Source, Base, Offset);
 936 31.Source,26.Base,21.0b0110,17.m,16.sz,14.SignedOffset::::st i
 937         do_st (_SD, Source, rBase, &GPR(Base), m, sz, 0, vSignedOffset);
 938 31.Source,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::st r
 939         do_st (_SD, Source, rBase, &GPR(Base), m, sz, S, rIndOff);
 940 31.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.0,9./::::st l
 941         long_immediate (LongSignedImmediateOffset);
 942         do_st (_SD, Source, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
 943
 944
 945 // sub
 946 void::function::do_sub:signed32 *rDest, signed32 Source1, signed32 Source2
 947         ALU_BEGIN (Source1);
 948         ALU_SUB (Source2);
 949         ALU_END (*rDest);
 950         TRACE_ALU3 (MY_INDEX, *rDest, Source1, Source2);
 951 31.Dest,26.Source2,21.0b101101,15.0,14.SignedImmediate::::sub i
 952         do_sub (_SD, rDest, vSource1, rSource2);
 953 31.Dest,26.Source2,21.0b11101101,13.0,12.0,11./,4.Source1::::sub r
 954         do_sub (_SD, rDest, rSource1, rSource2);
 955 31.Dest,26.Source2,21.0b11101101,13.0,12.1,11./::::sub l
 956         long_immediate (LongSignedImmediate);
 957         do_sub (_SD, rDest, LongSignedImmediate, rSource2);
 958
 959
 960 // subu
 961 void::function::do_subu:unsigned32 *rDest, unsigned32 Source1, signed32 Source2
 962         unsigned32 result = Source1 - Source2;
 963         TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
 964         *rDest = result;
 965 // NOTE - the book has 15.1 which conflicts with subu.
 966 31.Dest,26.Source2,21.0b101101,15.1,14.UnsignedImmediate::::subu i
 967         do_subu (_SD, rDest, vSource1, rSource2);
 968 31.Dest,26.Source2,21.0b11101101,13.1,12.0,11./,4.Source1::::subu r
 969         do_subu (_SD, rDest, rSource1, rSource2);
 970 31.Dest,26.Source2,21.0b11101101,13.1,12.1,11./::::subu l
 971         long_immediate (LongSignedImmediate);
 972         do_subu (_SD, rDest, LongSignedImmediate, rSource2);
 973
 974
 975 // swcr
 976 void::function::do_swcr:int Dest, signed32 rSource, signed32 cr
 977         tic80_control_regs reg = tic80_index2cr (cr);
 978         /* cache the old CR value */
 979         unsigned32 old_cr = CR (cr);
 980         /* Handle the write if allowed */
 981         if (cr >= 0x4000 || !(CPU)->is_user_mode)
 982           switch (reg)
 983             {
 984             case INTPEN_CR:
 985               CR (cr) &= ~rSource;
 986               break;
 987             default:
 988               CR (cr) = rSource;
 989               break;
 990             }
 991         /* Finish off the read */
 992         GPR (Dest) = old_cr;
 993         TRACE_SINK3 (MY_INDEX, rSource, cr, Dest);
 994 31.Dest,26.Source,21.0b000010,15.1,14.UCRN::::swcr i
 995         do_swcr (_SD, Dest, rSource, UCRN);
 996 31.Dest,26.Source,21.0b11000010,13.1,12.0,11./,4.INDCR::::swcr r
 997         do_swcr (_SD, Dest, rSource, UCRN);
 998 31.Dest,26.Source,21.0b11000010,13.1,12.1,11./::::swcr l
 999         long_immediate (LongUnsignedControlRegister);
1000         do_swcr (_SD, Dest, rSource, LongUnsignedControlRegister);
1001
1002
1003 // trap
1004 void::function::do_trap:unsigned32 trap_number
1005         TRACE_SINK1 (MY_INDEX, trap_number);
1006         switch (trap_number)
1007           {
1008           case 72:
1009             switch (GPR(15))
1010               {
1011               case 1: /* EXIT */
1012                 {
1013                   engine_halt (SD, CPU, cia, sim_exited, GPR(2));
1014                   break;
1015                 }
1016               case 4: /* WRITE */
1017                 {
1018                   int i;
1019                   if (GPR(2) == 1)
1020                     for (i = 0; i < GPR(6); i++)
1021                       {
1022                         char c;
1023                         c = MEM (unsigned, GPR(4) + i, 1);
1024                         sim_io_write_stdout (SD, &c, 1);
1025                       }
1026                   else if (GPR(2) == 2)
1027                     for (i = 0; i < GPR(6); i++)
1028                       {
1029                         char c;
1030                         c = MEM (unsigned, GPR(4) + i, 1);
1031                         sim_io_write_stderr (SD, &c, 1);
1032                       }
1033                   else
1034                     engine_error (SD, CPU, cia,
1035                                   "0x%lx: write to invalid fid %d",
1036                                   (unsigned long) cia.ip, GPR(2));
1037                   GPR(2) = GPR(6);
1038                   break;
1039                 }
1040               default:
1041                 engine_error (SD, CPU, cia,
1042                               "0x%lx: unknown syscall %d",
1043                               (unsigned long) cia.ip, GPR(15));
1044               }
1045             break;
1046           case 73:
1047             engine_halt (SD, CPU, cia, sim_stopped, SIGTRAP);
1048           default:
1049             engine_error (SD, CPU, cia,
1050                           "0x%lx: unsupported trap %d",
1051                           (unsigned long) cia.ip, trap_number);
1052           }
1053 31./,27.0,26./,21.0b0000001,14.UTN::::trap i
1054         do_trap (_SD, UTN);
1055 31./,27.0,26./,21.0b110000001,12.0,11./,4.INDTR::::trap r
1056         do_trap (_SD, UTN);
1057 31./,27.0,26./,21.0b110000001,12.1,11./::::trap l
1058         long_immediate (UTN);
1059         do_trap (_SD, UTN);
1060
1061
1062 // vadd.{s|d}{s|d}
1063 31.*,26.Dest,21.0b11110,16./,15.0b000,12.0,11./,10.*,9.*,7.PD,6.*,5.P1,4.Source::f::vadd r
1064 31.*,26.Dest,21.0b11110,16./,15.0b000,12.1,11./,10.*,9.*,7.PD,6.*,5.P1,4.Source::f::vadd l
1065
1066
1067 // vld{0|1}.{s|d} - see above - same instruction
1068 #31.Dest,26.*,21.0b11110,16.*,10.1,9.S,8.*,6.p,7.******::f::vld
1069
1070
1071 // vmac.ss{s|d}
1072 #31.*,   26.Source2,21.0b11110,16.a0,15.0b110,12.0,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4.Source1::f::vmac.ss ra
1073 31.Dest,26.Source2,21.0b11110,16.a0,15.0b110,12.0,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4.Source1::f::vmac.ss rr
1074 #31.*,   26.Source2,21.0b11110,16.a0,15.0b110,12.1,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4./::f::vmac.ss ia
1075 31.Dest,26.Source2,21.0b11110,16.a0,15.0b110,12.1,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4./::f::vmac.ss ir
1076
1077
1078 // vmpy.{s|d}{s|d}
1079 31.*,26.Dest,21.0b11110,16./,15.0b010,12.0,11./,10.*,8.*,7.PD,6.*,5.P1,4.Source::f::vmpy r
1080 31.*,26.Dest,21.0b11110,16./,15.0b010,12.1,11./,10.*,8.*,7.PD,6.*,5.P1,4./::f::vmpy l
1081
1082
1083 // vmsc.ss{s|d}
1084 #31.*,   26.Source2,21.0b11110,16.a0,15.0b111,12.0,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4.Source1::f::vmsc.ss ra
1085 31.Dest,26.Source2,21.0b11110,16.a0,15.0b111,12.0,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4.Source1::f::vmsc.ss rr
1086 #31.*,   26.Source2,21.0b11110,16.a0,15.0b111,12.1,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4./::f::vmsc.ss ia
1087 31.Dest,26.Source2,21.0b11110,16.a0,15.0b111,12.1,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4./::f::vmsc.ss ir
1088
1089
1090 // vmsub.{s|d}{s|d}
1091 31.*,26.Dest,21.0b11110,16.a0,15.0b011,12.0,11.a1,10.*,8.Z,7.PD,6.*,5./,4.Source::f::vmsub r
1092 31.*,26.Dest,21.0b11110,16.a0,15.0b011,12.1,11.a1,10.*,8.Z,7.PD,6.*,5./,4./::f::vmsub l
1093
1094
1095 // vrnd.{s|d}{s|d}
1096 31.*,26.Dest,21.0b11110,16.a0,15.0b100,12.0,11.a1,10.*,8.PD,6.*,5.P1,4.Source::f::vrnd f r
1097 31.*,26.Dest,21.0b11110,16.a0,15.0b100,12.1,11.a1,10.*,8.PD,6.*,5.P1,4./::f::vrnd f l
1098
1099
1100 // vrnd.{i|u}{s|d}
1101 31.*,26.Dest,21.0b11110,16./,15.0b101,12.0,11./,10.*,8./,7.PD,6.*,5.P1,4.Source::f::vrnd i r
1102 31.*,26.Dest,21.0b11110,16./,15.0b101,12.1,11./,10.*,8./,7.PD,6.*,5.P1,4./::f::vrnd i l
1103
1104
1105 // vst.{s|d} - see above - same instruction
1106 #31.Source,26.*,21.0b11110,16.*,10.0,9.S,8.*,6.1,5.*::f::vst
1107
1108
1109 // vsub.{i|u}{s|d}
1110 31.*,26.Dest,21.0b11110,16./,15.0b001,12.0,11./,10.*,8./,7.PD,6.*,5.P1,4.Source::f::vsub r
1111 31.*,26.Dest,21.0b11110,16./,15.0b001,12.1,11./,10.*,8./,7.PD,6.*,5.P1,4./::f::vsub l
1112
1113
1114 // wrcr - see swcr, creg, source, r0
1115
1116
1117 // xnor
1118 void::function::do_xnor:signed32 *rDest, signed32 Source1, signed32 Source2
1119         unsigned32 result = ~ (Source1 ^ Source2);
1120         TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
1121         *rDest = result;
1122 31.Dest,26.Source2,21.0b0011001,14.UnsignedImmediate::::xnor i
1123         do_xnor (_SD, rDest, vSource1, rSource2);
1124 31.Dest,26.Source2,21.0b110011001,12.0,11./,4.Source1::::xnor r
1125         do_xnor (_SD, rDest, rSource1, rSource2);
1126 31.Dest,26.Source2,21.0b110011001,12.1,11./::::xnor l
1127         long_immediate (LongUnsignedImmediate);
1128         do_xnor (_SD, rDest, LongUnsignedImmediate, rSource2);
1129
1130
1131 // xor
1132 void::function::do_xor:signed32 *rDest, signed32 Source1, signed32 Source2
1133         unsigned32 result = Source1 ^ Source2;
1134         TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
1135         *rDest = result;
1136 31.Dest,26.Source2,21.0b0010110,14.UnsignedImmediate::::xor i
1137         do_xor (_SD, rDest, vSource1, rSource2);
1138 31.Dest,26.Source2,21.0b110010110,12.0,11./,4.Source1::::xor r
1139         do_xor (_SD, rDest, rSource1, rSource2);
1140 31.Dest,26.Source2,21.0b110010110,12.1,11./::::xor l
1141         long_immediate (LongUnsignedImmediate);
1142         do_xor (_SD, rDest, LongUnsignedImmediate, rSource2);