sim/v850/sim-main.h

   1 #define WITH_MODULO_MEMORY 1
   2 #define WITH_WATCHPOINTS 1
   3 #define WITH_TARGET_WORD_MSB 31
   4
   5 #include "sim-basics.h"
   6
   7 typedef address_word sim_cia;
   8
   9 /* This simulator doesn't cache state */
  10 #define SIM_ENGINE_HALT_HOOK(sd,last_cpu,cia) while (0)
  11 #define SIM_ENGINE_RESTART_HOOK(sd,last_cpu,cia) while (0)
  12
  13 #include "sim-base.h"
  14
  15 typedef signed8 int8;
  16 typedef unsigned8 uint8;
  17 typedef signed16 int16;
  18 typedef unsigned16 uint16;
  19 typedef signed32 int32;
  20 typedef unsigned32 uint32;
  21 typedef unsigned32 reg_t;
  22
  23
  24 /* The current state of the processor; registers, memory, etc.  */
  25
  26 typedef struct _v850_regs {
  27   reg_t regs[32];               /* general-purpose registers */
  28   reg_t sregs[32];              /* system registers, including psw */
  29   reg_t pc;
  30   int dummy_mem;                /* where invalid accesses go */
  31   int pending_nmi;
  32 } v850_regs;
  33
  34 struct _sim_cpu
  35 {
  36   /* ... simulator specific members ... */
  37   v850_regs reg;
  38   /* ... base type ... */
  39   sim_cpu_base base;
  40 };
  41
  42 #define CPU_CIA(CPU) ((CPU)->reg.pc)
  43
  44 struct sim_state {
  45   sim_cpu cpu[MAX_NR_PROCESSORS];
  46 #if (WITH_SMP)
  47 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
  48 #else
  49 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
  50 #endif
  51 #if 0
  52   SIM_ADDR rom_size;
  53   SIM_ADDR low_end;
  54   SIM_ADDR high_start;
  55   SIM_ADDR high_base;
  56   void *mem;
  57 #endif
  58   sim_state_base base;
  59 };
  60
  61 /* For compatibility, until all functions converted to passing
  62    SIM_DESC as an argument */
  63 extern SIM_DESC simulator;
  64
  65
  66 #define V850_ROM_SIZE 0x8000
  67 #define V850_LOW_END 0x200000
  68 #define V850_HIGH_START 0xffe000
  69
  70
  71 #define SIG_V850_EXIT   -1      /* indication of a normal exit */
  72
  73 extern uint32 OP[4];
  74
  75 /* Because we are still using the old semantic table, provide compat
  76    macro's that store the instruction where the old simops expects
  77    it. */
  78
  79 #if 0
  80 OP[0] = inst & 0x1f;
  81 OP[1] = (inst >> 11) & 0x1f;
  82 OP[2] = (inst >> 16) & 0xffff;
  83 OP[3] = inst;
  84 #endif
  85
  86 #define COMPAT_1(CALL) \
  87 PC = cia; \
  88 OP[0] = instruction_0 & 0x1f; \
  89 OP[1] = (instruction_0 >> 11) & 0x1f; \
  90 OP[2] = 0; \
  91 OP[3] = instruction_0 ; \
  92 PC += (CALL); \
  93 nia = PC
  94
  95 #define COMPAT_2(CALL) \
  96 PC = cia; \
  97 OP[0] = instruction_0 & 0x1f; \
  98 OP[1] = (instruction_0 >> 11) & 0x1f; \
  99 OP[2] = instruction_1; \
 100 OP[3] = (instruction_1 << 16) | instruction_0; \
 101 PC += (CALL); \
 102 nia = PC
 103
 104
 105 #if 0
 106 extern struct simops Simops[];
 107 #endif
 108
 109 #define State    (STATE_CPU (simulator, 0)->reg)
 110 #define PC      (State.pc)
 111 #define SP      (State.regs[3])
 112 #define EP      (State.regs[30])
 113
 114 #define EIPC  (State.sregs[0])
 115 #define EIPSW (State.sregs[1])
 116 #define FEPC  (State.sregs[2])
 117 #define FEPSW (State.sregs[3])
 118 #define ECR   (State.sregs[4])
 119 #define PSW   (State.sregs[5])
 120 /* start-sanitize-v850e */
 121 #define CTPC  (State.sregs[16])
 122 #define CTPSW (State.sregs[17])
 123 /* end-sanitize-v850e */
 124 #define DBPC  (State.sregs[18])
 125 #define DBPSW (State.sregs[19])
 126 /* start-sanitize-v850e */
 127 #define CTBP  (State.sregs[20])
 128 /* end-sanitize-v850e */
 129
 130 #define PSW_NP 0x80
 131 #define PSW_EP 0x40
 132 #define PSW_ID 0x20
 133 #define PSW_SAT 0x10
 134 #define PSW_CY 0x8
 135 #define PSW_OV 0x4
 136 #define PSW_S 0x2
 137 #define PSW_Z 0x1
 138
 139 #define SEXT3(x)        ((((x)&0x7)^(~0x3))+0x4)
 140
 141 /* sign-extend a 4-bit number */
 142 #define SEXT4(x)        ((((x)&0xf)^(~0x7))+0x8)
 143
 144 /* sign-extend a 5-bit number */
 145 #define SEXT5(x)        ((((x)&0x1f)^(~0xf))+0x10)
 146
 147 /* sign-extend a 9-bit number */
 148 #define SEXT9(x)        ((((x)&0x1ff)^(~0xff))+0x100)
 149
 150 /* sign-extend a 22-bit number */
 151 #define SEXT22(x)       ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
 152
 153 /* sign extend a 40 bit number */
 154 #define SEXT40(x)       ((((x) & UNSIGNED64 (0xffffffffff)) \
 155                           ^ (~UNSIGNED64 (0x7fffffffff))) \
 156                          + UNSIGNED64 (0x8000000000))
 157
 158 /* sign extend a 44 bit number */
 159 #define SEXT44(x)       ((((x) & UNSIGNED64 (0xfffffffffff)) \
 160                           ^ (~ UNSIGNED64 (0x7ffffffffff))) \
 161                          + UNSIGNED64 (0x80000000000))
 162
 163 /* sign extend a 60 bit number */
 164 #define SEXT60(x)       ((((x) & UNSIGNED64 (0xfffffffffffffff)) \
 165                           ^ (~ UNSIGNED64 (0x7ffffffffffffff))) \
 166                          + UNSIGNED64 (0x800000000000000))
 167
 168 /* No sign extension */
 169 #define NOP(x)          (x)
 170
 171 #define INC_ADDR(x,i)   x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
 172
 173 #define RLW(x) load_mem (x, 4)
 174
 175 #ifdef _WIN32
 176 #ifndef SIGTRAP
 177 #define SIGTRAP 5
 178 #endif
 179 #ifndef SIGQUIT
 180 #define SIGQUIT 3
 181 #endif
 182 #endif
 183
 184 /* Function declarations.  */
 185
 186 #define IMEM(EA) \
 187 sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
 188                          PC, sim_core_execute_map, (EA))
 189
 190 #define IMEM_IMMED(EA,N) \
 191 sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
 192                          PC, sim_core_execute_map, (EA) + (N) * 2)
 193
 194 #define load_mem(ADDR,LEN) \
 195 sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \
 196                                PC, sim_core_read_map, (ADDR))
 197
 198 #define store_mem(ADDR,LEN,DATA) \
 199 sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
 200                                 PC, sim_core_write_map, (ADDR), (DATA))
 201
 202 #include "simops.h"