4 /* General config options */
7 #define WITH_MODULO_MEMORY 1
8 #define WITH_WATCHPOINTS 1
11 /* The v850 has 32bit words, numbered 31 (MSB) to 0 (LSB) */
13 #define WITH_TARGET_WORD_MSB 31
16 #include "sim-basics.h"
17 #include "sim-signal.h"
20 typedef address_word sim_cia
;
29 typedef unsigned8 uint8
;
30 typedef signed16 int16
;
31 typedef unsigned16 uint16
;
32 typedef signed32 int32
;
33 typedef unsigned32 uint32
;
34 typedef unsigned32 reg_t
;
37 /* The current state of the processor; registers, memory, etc. */
39 typedef struct _v850_regs
{
40 reg_t regs
[32]; /* general-purpose registers */
41 reg_t sregs
[32]; /* system registers, including psw */
43 int dummy_mem
; /* where invalid accesses go */
44 reg_t mpu0_sregs
[28]; /* mpu0 system registers */
45 reg_t mpu1_sregs
[28]; /* mpu1 system registers */
46 reg_t fpu_sregs
[28]; /* fpu system registers */
51 /* ... simulator specific members ... */
53 reg_t psw_mask
; /* only allow non-reserved bits to be set */
54 sim_event
*pending_nmi
;
55 /* ... base type ... */
59 #define CIA_GET(CPU) ((CPU)->reg.pc + 0)
60 #define CIA_SET(CPU,VAL) ((CPU)->reg.pc = (VAL))
63 sim_cpu cpu
[MAX_NR_PROCESSORS
];
65 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
67 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
79 /* For compatibility, until all functions converted to passing
80 SIM_DESC as an argument */
81 extern SIM_DESC simulator
;
84 #define V850_ROM_SIZE 0x8000
85 #define V850_LOW_END 0x200000
86 #define V850_HIGH_START 0xffe000
89 /* Because we are still using the old semantic table, provide compat
90 macro's that store the instruction where the old simops expects
95 OP
[0] = inst
& 0x1f; /* RRRRR -> reg1 */
96 OP
[1] = (inst
>> 11) & 0x1f; /* rrrrr -> reg2 */
97 OP
[2] = (inst
>> 16) & 0xffff; /* wwwww -> reg3 OR imm16 */
103 OP[0] = instruction_0 & 0x1f; \
104 OP[1] = (instruction_0 >> 11) & 0x1f; \
106 OP[3] = instruction_0
108 #define COMPAT_1(CALL) \
115 OP[0] = instruction_0 & 0x1f; \
116 OP[1] = (instruction_0 >> 11) & 0x1f; \
117 OP[2] = instruction_1; \
118 OP[3] = (instruction_1 << 16) | instruction_0
120 #define COMPAT_2(CALL) \
127 #define GR ((CPU)->reg.regs)
128 #define SR ((CPU)->reg.sregs)
129 #define MPU0_SR ((STATE_CPU (sd, 0))->reg.mpu0_sregs)
130 #define MPU1_SR ((STATE_CPU (sd, 0))->reg.mpu1_sregs)
131 #define FPU_SR ((STATE_CPU (sd, 0))->reg.fpu_sregs)
134 #define State (STATE_CPU (simulator, 0)->reg)
135 #define PC (State.pc)
137 #define SP (State.regs[SP_REGNO])
138 #define EP (State.regs[30])
140 #define EIPC (State.sregs[0])
141 #define EIPSW (State.sregs[1])
142 #define FEPC (State.sregs[2])
143 #define FEPSW (State.sregs[3])
144 #define ECR (State.sregs[4])
145 #define PSW (State.sregs[5])
147 #define EIIC (State.sregs[13])
148 #define FEIC (State.sregs[14])
149 #define DBIC (SR[15])
150 #define CTPC (SR[16])
151 #define CTPSW (SR[17])
152 #define DBPC (State.sregs[18])
153 #define DBPSW (State.sregs[19])
154 #define CTBP (State.sregs[20])
156 #define EIWR (SR[28])
157 #define FEWR (SR[29])
158 #define DBWR (SR[30])
159 #define BSEL (SR[31])
161 #define PSW_US BIT32 (8)
171 #define PSW_NPV (1<<18)
172 #define PSW_DMP (1<<17)
173 #define PSW_IMP (1<<16)
175 #define ECR_EICC 0x0000ffff
176 #define ECR_FECC 0xffff0000
180 #define FPSR (FPU_SR[6])
182 #define FPEPC (FPU_SR[7])
183 #define FPST (FPU_SR[8])
185 #define FPCC (FPU_SR[9])
186 #define FPCFG (FPU_SR[10])
187 #define FPCFG_REGNO 10
189 #define FPSR_DEM 0x00200000
190 #define FPSR_SEM 0x00100000
191 #define FPSR_RM 0x000c0000
192 #define FPSR_RN 0x00000000
193 #define FPSR_FS 0x00020000
194 #define FPSR_PR 0x00010000
196 #define FPSR_XC 0x0000fc00
197 #define FPSR_XCE 0x00008000
198 #define FPSR_XCV 0x00004000
199 #define FPSR_XCZ 0x00002000
200 #define FPSR_XCO 0x00001000
201 #define FPSR_XCU 0x00000800
202 #define FPSR_XCI 0x00000400
204 #define FPSR_XE 0x000003e0
205 #define FPSR_XEV 0x00000200
206 #define FPSR_XEZ 0x00000100
207 #define FPSR_XEO 0x00000080
208 #define FPSR_XEU 0x00000040
209 #define FPSR_XEI 0x00000020
211 #define FPSR_XP 0x0000001f
212 #define FPSR_XPV 0x00000010
213 #define FPSR_XPZ 0x00000008
214 #define FPSR_XPO 0x00000004
215 #define FPSR_XPU 0x00000002
216 #define FPSR_XPI 0x00000001
218 #define FPST_PR 0x00008000
219 #define FPST_XCE 0x00002000
220 #define FPST_XCV 0x00001000
221 #define FPST_XCZ 0x00000800
222 #define FPST_XCO 0x00000400
223 #define FPST_XCU 0x00000200
224 #define FPST_XCI 0x00000100
226 #define FPST_XPV 0x00000010
227 #define FPST_XPZ 0x00000008
228 #define FPST_XPO 0x00000004
229 #define FPST_XPU 0x00000002
230 #define FPST_XPI 0x00000001
232 #define FPCFG_RM 0x00000180
233 #define FPCFG_XEV 0x00000010
234 #define FPCFG_XEZ 0x00000008
235 #define FPCFG_XEO 0x00000004
236 #define FPCFG_XEU 0x00000002
237 #define FPCFG_XEI 0x00000001
242 #define CLEAR_FPCC(bbb)\
243 (FPSR &= ~(1 << (bbb+24)))
245 #define SET_FPCC(bbb)\
246 (FPSR |= 1 << (bbb+24))
248 #define TEST_FPCC(bbb)\
249 ((FPSR & (1 << (bbb+24))) != 0)
251 #define FPSR_GET_ROUND() \
252 (((FPSR & FPSR_RM) == FPSR_RN) ? sim_fpu_round_near \
253 : ((FPSR & FPSR_RM) == 0x00040000) ? sim_fpu_round_up \
254 : ((FPSR & FPSR_RM) == 0x00080000) ? sim_fpu_round_down \
255 : sim_fpu_round_zero)
279 #define MPM (MPU1_SR[0])
280 #define MPC (MPU1_SR[1])
282 #define TID (MPU1_SR[2])
283 #define PPA (MPU1_SR[3])
284 #define PPM (MPU1_SR[4])
285 #define PPC (MPU1_SR[5])
286 #define DCC (MPU1_SR[6])
287 #define DCV0 (MPU1_SR[7])
288 #define DCV1 (MPU1_SR[8])
289 #define SPAL (MPU1_SR[10])
290 #define SPAU (MPU1_SR[11])
291 #define IPA0L (MPU1_SR[12])
292 #define IPA0U (MPU1_SR[13])
293 #define IPA1L (MPU1_SR[14])
294 #define IPA1U (MPU1_SR[15])
295 #define IPA2L (MPU1_SR[16])
296 #define IPA2U (MPU1_SR[17])
297 #define IPA3L (MPU1_SR[18])
298 #define IPA3U (MPU1_SR[19])
299 #define DPA0L (MPU1_SR[20])
300 #define DPA0U (MPU1_SR[21])
301 #define DPA1L (MPU1_SR[22])
302 #define DPA1U (MPU1_SR[23])
303 #define DPA2L (MPU1_SR[24])
304 #define DPA2U (MPU1_SR[25])
305 #define DPA3L (MPU1_SR[26])
306 #define DPA3U (MPU1_SR[27])
310 #define SPAL_SPS 0x10
312 #define VIP (MPU0_SR[0])
313 #define VMECR (MPU0_SR[4])
314 #define VMTID (MPU0_SR[5])
315 #define VMADR (MPU0_SR[6])
316 #define VPECR (MPU0_SR[8])
317 #define VPTID (MPU0_SR[9])
318 #define VPADR (MPU0_SR[10])
319 #define VDECR (MPU0_SR[12])
320 #define VDTID (MPU0_SR[13])
325 #define VMECR_VMX 0x2
326 #define VMECR_VMR 0x4
327 #define VMECR_VMW 0x8
328 #define VMECR_VMS 0x10
329 #define VMECR_VMRMW 0x20
330 #define VMECR_VMMS 0x40
332 #define IPA2ADDR(IPA) ((IPA) & 0x1fffff80)
336 #define IPE0 (IPA0L & IPA_IPE)
337 #define IPE1 (IPA1L & IPA_IPE)
338 #define IPE2 (IPA2L & IPA_IPE)
339 #define IPE3 (IPA3L & IPA_IPE)
340 #define IPX0 (IPA0L & IPA_IPX)
341 #define IPX1 (IPA1L & IPA_IPX)
342 #define IPX2 (IPA2L & IPA_IPX)
343 #define IPX3 (IPA3L & IPA_IPX)
344 #define IPR0 (IPA0L & IPA_IPR)
345 #define IPR1 (IPA1L & IPA_IPR)
346 #define IPR2 (IPA2L & IPA_IPR)
347 #define IPR3 (IPA3L & IPA_IPR)
349 #define DPA2ADDR(DPA) ((DPA) & 0x1fffff80)
353 #define DPE0 (DPA0L & DPA_DPE)
354 #define DPE1 (DPA1L & DPA_DPE)
355 #define DPE2 (DPA2L & DPA_DPE)
356 #define DPE3 (DPA3L & DPA_DPE)
357 #define DPR0 (DPA0L & DPA_DPR)
358 #define DPR1 (DPA1L & DPA_DPR)
359 #define DPR2 (DPA2L & DPA_DPR)
360 #define DPR3 (DPA3L & DPA_DPR)
361 #define DPW0 (DPA0L & DPA_DPW)
362 #define DPW1 (DPA1L & DPA_DPW)
363 #define DPW2 (DPA2L & DPA_DPW)
364 #define DPW3 (DPA3L & DPA_DPW)
367 #define DCC_DCE1 0x10000
369 #define PPA2ADDR(PPA) ((PPA) & 0x1fffff80)
370 #define PPC_PPC 0xfffffffe
372 #define PPC_PPM 0x0000fff8
375 #define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4)
377 /* sign-extend a 4-bit number */
378 #define SEXT4(x) ((((x)&0xf)^(~0x7))+0x8)
380 /* sign-extend a 5-bit number */
381 #define SEXT5(x) ((((x)&0x1f)^(~0xf))+0x10)
383 /* sign-extend a 9-bit number */
384 #define SEXT9(x) ((((x)&0x1ff)^(~0xff))+0x100)
386 /* sign-extend a 22-bit number */
387 #define SEXT22(x) ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
389 /* sign extend a 40 bit number */
390 #define SEXT40(x) ((((x) & UNSIGNED64 (0xffffffffff)) \
391 ^ (~UNSIGNED64 (0x7fffffffff))) \
392 + UNSIGNED64 (0x8000000000))
394 /* sign extend a 44 bit number */
395 #define SEXT44(x) ((((x) & UNSIGNED64 (0xfffffffffff)) \
396 ^ (~ UNSIGNED64 (0x7ffffffffff))) \
397 + UNSIGNED64 (0x80000000000))
399 /* sign extend a 60 bit number */
400 #define SEXT60(x) ((((x) & UNSIGNED64 (0xfffffffffffffff)) \
401 ^ (~ UNSIGNED64 (0x7ffffffffffffff))) \
402 + UNSIGNED64 (0x800000000000000))
404 /* No sign extension */
407 #define INC_ADDR(x,i) x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
409 #define RLW(x) load_mem (x, 4)
411 /* Function declarations. */
414 sim_core_read_aligned_2 (CPU, PC, exec_map, (EA))
416 #define IMEM16_IMMED(EA,N) \
417 sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
418 PC, exec_map, (EA) + (N) * 2)
420 #define load_mem(ADDR,LEN) \
421 sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \
422 PC, read_map, (ADDR))
424 #define store_mem(ADDR,LEN,DATA) \
425 sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
426 PC, write_map, (ADDR), (DATA))
429 /* compare cccc field against PSW */
430 int condition_met (unsigned code
);
433 /* Debug/tracing calls */
472 void trace_input
PARAMS ((char *name
, enum op_types type
, int size
));
473 void trace_output
PARAMS ((enum op_types result
));
474 void trace_result
PARAMS ((int has_result
, unsigned32 result
));
476 extern int trace_num_values
;
477 extern unsigned32 trace_values
[];
478 extern unsigned32 trace_pc
;
479 extern const char *trace_name
;
480 extern int trace_module
;
482 #define TRACE_BRANCH0() \
484 if (TRACE_BRANCH_P (CPU)) { \
485 trace_module = TRACE_BRANCH_IDX; \
487 trace_name = itable[MY_INDEX].name; \
488 trace_num_values = 0; \
489 trace_result (1, (nia)); \
493 #define TRACE_BRANCH1(IN1) \
495 if (TRACE_BRANCH_P (CPU)) { \
496 trace_module = TRACE_BRANCH_IDX; \
498 trace_name = itable[MY_INDEX].name; \
499 trace_values[0] = (IN1); \
500 trace_num_values = 1; \
501 trace_result (1, (nia)); \
505 #define TRACE_BRANCH2(IN1, IN2) \
507 if (TRACE_BRANCH_P (CPU)) { \
508 trace_module = TRACE_BRANCH_IDX; \
510 trace_name = itable[MY_INDEX].name; \
511 trace_values[0] = (IN1); \
512 trace_values[1] = (IN2); \
513 trace_num_values = 2; \
514 trace_result (1, (nia)); \
518 #define TRACE_BRANCH3(IN1, IN2, IN3) \
520 if (TRACE_BRANCH_P (CPU)) { \
521 trace_module = TRACE_BRANCH_IDX; \
523 trace_name = itable[MY_INDEX].name; \
524 trace_values[0] = (IN1); \
525 trace_values[1] = (IN2); \
526 trace_values[2] = (IN3); \
527 trace_num_values = 3; \
528 trace_result (1, (nia)); \
532 #define TRACE_LD(ADDR,RESULT) \
534 if (TRACE_MEMORY_P (CPU)) { \
535 trace_module = TRACE_MEMORY_IDX; \
537 trace_name = itable[MY_INDEX].name; \
538 trace_values[0] = (ADDR); \
539 trace_num_values = 1; \
540 trace_result (1, (RESULT)); \
544 #define TRACE_LD_NAME(NAME, ADDR,RESULT) \
546 if (TRACE_MEMORY_P (CPU)) { \
547 trace_module = TRACE_MEMORY_IDX; \
549 trace_name = (NAME); \
550 trace_values[0] = (ADDR); \
551 trace_num_values = 1; \
552 trace_result (1, (RESULT)); \
556 #define TRACE_ST(ADDR,RESULT) \
558 if (TRACE_MEMORY_P (CPU)) { \
559 trace_module = TRACE_MEMORY_IDX; \
561 trace_name = itable[MY_INDEX].name; \
562 trace_values[0] = (ADDR); \
563 trace_num_values = 1; \
564 trace_result (1, (RESULT)); \
568 #define TRACE_FP_INPUT_FPU1(V0) \
570 if (TRACE_FPU_P (CPU)) \
573 sim_fpu_to64 (&f0, (V0)); \
574 trace_input_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
578 #define TRACE_FP_INPUT_FPU2(V0, V1) \
580 if (TRACE_FPU_P (CPU)) \
583 sim_fpu_to64 (&f0, (V0)); \
584 sim_fpu_to64 (&f1, (V1)); \
585 trace_input_fp2 (SD, CPU, TRACE_FPU_IDX, f0, f1); \
589 #define TRACE_FP_INPUT_FPU3(V0, V1, V2) \
591 if (TRACE_FPU_P (CPU)) \
593 unsigned64 f0, f1, f2; \
594 sim_fpu_to64 (&f0, (V0)); \
595 sim_fpu_to64 (&f1, (V1)); \
596 sim_fpu_to64 (&f2, (V2)); \
597 trace_input_fp3 (SD, CPU, TRACE_FPU_IDX, f0, f1, f2); \
601 #define TRACE_FP_INPUT_BOOL1_FPU2(V0, V1, V2) \
603 if (TRACE_FPU_P (CPU)) \
607 TRACE_DATA *data = CPU_TRACE_DATA (CPU); \
608 TRACE_IDX (data) = TRACE_FPU_IDX; \
609 sim_fpu_to64 (&f1, (V1)); \
610 sim_fpu_to64 (&f2, (V2)); \
611 save_data (SD, data, trace_fmt_bool, sizeof (d0), &d0); \
612 save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f1); \
613 save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f2); \
617 #define TRACE_FP_INPUT_WORD2(V0, V1) \
619 if (TRACE_FPU_P (CPU)) \
620 trace_input_word2 (SD, CPU, TRACE_FPU_IDX, (V0), (V1)); \
623 #define TRACE_FP_RESULT_FPU1(R0) \
625 if (TRACE_FPU_P (CPU)) \
628 sim_fpu_to64 (&f0, (R0)); \
629 trace_result_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
633 #define TRACE_FP_RESULT_WORD1(R0) TRACE_FP_RESULT_WORD(R0)
635 #define TRACE_FP_RESULT_WORD2(R0, R1) \
637 if (TRACE_FPU_P (CPU)) \
638 trace_result_word2 (SD, CPU, TRACE_FPU_IDX, (R0), (R1)); \
642 #define trace_input(NAME, IN1, IN2)
643 #define trace_output(RESULT)
644 #define trace_result(HAS_RESULT, RESULT)
646 #define TRACE_ALU_INPUT0()
647 #define TRACE_ALU_INPUT1(IN0)
648 #define TRACE_ALU_INPUT2(IN0, IN1)
649 #define TRACE_ALU_INPUT2(IN0, IN1)
650 #define TRACE_ALU_INPUT2(IN0, IN1 INS2)
651 #define TRACE_ALU_RESULT(RESULT)
653 #define TRACE_BRANCH0()
654 #define TRACE_BRANCH1(IN1)
655 #define TRACE_BRANCH2(IN1, IN2)
656 #define TRACE_BRANCH2(IN1, IN2, IN3)
658 #define TRACE_LD(ADDR,RESULT)
659 #define TRACE_ST(ADDR,RESULT)
663 #define GPR_SET(N, VAL) (State.regs[(N)] = (VAL))
664 #define GPR_CLEAR(N) (State.regs[(N)] = 0)
666 extern void divun ( unsigned int N
,
667 unsigned long int als
,
668 unsigned long int sfi
,
669 unsigned32
/*unsigned long int*/ * quotient_ptr
,
670 unsigned32
/*unsigned long int*/ * remainder_ptr
,
673 extern void divn ( unsigned int N
,
674 unsigned long int als
,
675 unsigned long int sfi
,
676 signed32
/*signed long int*/ * quotient_ptr
,
677 signed32
/*signed long int*/ * remainder_ptr
,
680 extern int type1_regs
[];
681 extern int type2_regs
[];
682 extern int type3_regs
[];
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