sim/v850/sim-main.h

   1 #define WITH_CORE
   2 #define WITH_MODULO_MEMORY 1
   3 #define WITH_WATCHPOINTS 1
   4 #define WITH_TARGET_WORD_MSB 31
   5
   6 #include "sim-basics.h"
   7
   8 #include <signal.h>
   9 typedef address_word sim_cia;
  10
  11
  12 /* This simulator doesn't cache state */
  13 #define SIM_ENGINE_HALT_HOOK(sd,last_cpu,cia) while (0)
  14 #define SIM_ENGINE_RESTART_HOOK(sd,last_cpu,cia) while (0)
  15
  16 /* Get the number of instructions.  FIXME: must be a more elegant way
  17    of doing this.  */
  18 #include "itable.h"
  19 #define MAX_INSNS (nr_itable_entries)
  20 #define INSN_NAME(i) itable[(i)].name
  21
  22 #include "sim-base.h"
  23
  24 #include "simops.h"
  25 #include "bfd.h"
  26
  27
  28 typedef signed8 int8;
  29 typedef unsigned8 uint8;
  30 typedef signed16 int16;
  31 typedef unsigned16 uint16;
  32 typedef signed32 int32;
  33 typedef unsigned32 uint32;
  34 typedef unsigned32 reg_t;
  35
  36
  37 /* The current state of the processor; registers, memory, etc.  */
  38
  39 typedef struct _v850_regs {
  40   reg_t regs[32];               /* general-purpose registers */
  41   reg_t sregs[32];              /* system registers, including psw */
  42   reg_t pc;
  43   int dummy_mem;                /* where invalid accesses go */
  44   int pending_nmi;
  45 } v850_regs;
  46
  47 struct _sim_cpu
  48 {
  49   /* ... simulator specific members ... */
  50   v850_regs reg;
  51   /* ... base type ... */
  52   sim_cpu_base base;
  53 };
  54
  55 #define CPU_CIA(CPU) ((CPU)->reg.pc)
  56
  57 struct sim_state {
  58   sim_cpu cpu[MAX_NR_PROCESSORS];
  59 #if (WITH_SMP)
  60 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
  61 #else
  62 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
  63 #endif
  64 #if 0
  65   SIM_ADDR rom_size;
  66   SIM_ADDR low_end;
  67   SIM_ADDR high_start;
  68   SIM_ADDR high_base;
  69   void *mem;
  70 #endif
  71   sim_state_base base;
  72 };
  73
  74 /* For compatibility, until all functions converted to passing
  75    SIM_DESC as an argument */
  76 extern SIM_DESC simulator;
  77
  78
  79 #define V850_ROM_SIZE 0x8000
  80 #define V850_LOW_END 0x200000
  81 #define V850_HIGH_START 0xffe000
  82
  83
  84 #define SIG_V850_EXIT   -1      /* indication of a normal exit */
  85
  86 extern uint32 OP[4];
  87
  88 /* Because we are still using the old semantic table, provide compat
  89    macro's that store the instruction where the old simops expects
  90    it. */
  91
  92 #if 0
  93 OP[0] = inst & 0x1f;           /* RRRRR -> reg1 */
  94 OP[1] = (inst >> 11) & 0x1f;   /* rrrrr -> reg2 */
  95 OP[2] = (inst >> 16) & 0xffff; /* wwwww -> reg3 */
  96 OP[3] = inst;
  97 #endif
  98
  99 #define SAVE_1 \
 100 PC = cia; \
 101 OP[0] = instruction_0 & 0x1f; \
 102 OP[1] = (instruction_0 >> 11) & 0x1f; \
 103 OP[2] = 0; \
 104 OP[3] = instruction_0
 105
 106 #define COMPAT_1(CALL) \
 107 SAVE_1; \
 108 PC += (CALL); \
 109 nia = PC
 110
 111 #define SAVE_2 \
 112 PC = cia; \
 113 OP[0] = instruction_0 & 0x1f; \
 114 OP[1] = (instruction_0 >> 11) & 0x1f; \
 115 OP[2] = instruction_1; \
 116 OP[3] = (instruction_1 << 16) | instruction_0
 117
 118 #define COMPAT_2(CALL) \
 119 SAVE_2; \
 120 PC += (CALL); \
 121 nia = PC
 122
 123
 124 #if 0
 125 extern struct simops Simops[];
 126 #endif
 127
 128 #define State    (STATE_CPU (simulator, 0)->reg)
 129 #define PC      (State.pc)
 130 #define SP      (State.regs[3])
 131 #define EP      (State.regs[30])
 132
 133 #define EIPC  (State.sregs[0])
 134 #define EIPSW (State.sregs[1])
 135 #define FEPC  (State.sregs[2])
 136 #define FEPSW (State.sregs[3])
 137 #define ECR   (State.sregs[4])
 138 #define PSW   (State.sregs[5])
 139 /* start-sanitize-v850e */
 140 #define CTPC  (State.sregs[16])
 141 #define CTPSW (State.sregs[17])
 142 /* end-sanitize-v850e */
 143 #define DBPC  (State.sregs[18])
 144 #define DBPSW (State.sregs[19])
 145 /* start-sanitize-v850e */
 146 #define CTBP  (State.sregs[20])
 147 /* end-sanitize-v850e */
 148
 149 /* start-sanitize-v850eq */
 150 #define PSW_US BIT32 (8)
 151 /* end-sanitize-v850eq */
 152 #define PSW_NP 0x80
 153 #define PSW_EP 0x40
 154 #define PSW_ID 0x20
 155 #define PSW_SAT 0x10
 156 #define PSW_CY 0x8
 157 #define PSW_OV 0x4
 158 #define PSW_S 0x2
 159 #define PSW_Z 0x1
 160
 161 #define SEXT3(x)        ((((x)&0x7)^(~0x3))+0x4)
 162
 163 /* sign-extend a 4-bit number */
 164 #define SEXT4(x)        ((((x)&0xf)^(~0x7))+0x8)
 165
 166 /* sign-extend a 5-bit number */
 167 #define SEXT5(x)        ((((x)&0x1f)^(~0xf))+0x10)
 168
 169 /* sign-extend a 9-bit number */
 170 #define SEXT9(x)        ((((x)&0x1ff)^(~0xff))+0x100)
 171
 172 /* sign-extend a 22-bit number */
 173 #define SEXT22(x)       ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
 174
 175 /* sign extend a 40 bit number */
 176 #define SEXT40(x)       ((((x) & UNSIGNED64 (0xffffffffff)) \
 177                           ^ (~UNSIGNED64 (0x7fffffffff))) \
 178                          + UNSIGNED64 (0x8000000000))
 179
 180 /* sign extend a 44 bit number */
 181 #define SEXT44(x)       ((((x) & UNSIGNED64 (0xfffffffffff)) \
 182                           ^ (~ UNSIGNED64 (0x7ffffffffff))) \
 183                          + UNSIGNED64 (0x80000000000))
 184
 185 /* sign extend a 60 bit number */
 186 #define SEXT60(x)       ((((x) & UNSIGNED64 (0xfffffffffffffff)) \
 187                           ^ (~ UNSIGNED64 (0x7ffffffffffffff))) \
 188                          + UNSIGNED64 (0x800000000000000))
 189
 190 /* No sign extension */
 191 #define NOP(x)          (x)
 192
 193 #define INC_ADDR(x,i)   x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
 194
 195 #define RLW(x) load_mem (x, 4)
 196
 197 #ifdef _WIN32
 198 #ifndef SIGTRAP
 199 #define SIGTRAP 5
 200 #endif
 201 #ifndef SIGQUIT
 202 #define SIGQUIT 3
 203 #endif
 204 #endif
 205
 206 /* Function declarations.  */
 207
 208 #define IMEM(EA) \
 209 sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
 210                          PC, sim_core_execute_map, (EA))
 211
 212 #define IMEM_IMMED(EA,N) \
 213 sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
 214                          PC, sim_core_execute_map, (EA) + (N) * 2)
 215
 216 #define load_mem(ADDR,LEN) \
 217 sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \
 218                                PC, sim_core_read_map, (ADDR))
 219
 220 #define store_mem(ADDR,LEN,DATA) \
 221 sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
 222                                 PC, sim_core_write_map, (ADDR), (DATA))
 223
 224
 225 /* Debug/tracing calls */
 226
 227 enum op_types
 228 {
 229   OP_UNKNOWN,
 230   OP_NONE,
 231   OP_TRAP,
 232   OP_REG,
 233   OP_REG_REG,
 234   OP_REG_REG_CMP,
 235   OP_REG_REG_MOVE,
 236   OP_IMM_REG,
 237   OP_IMM_REG_CMP,
 238   OP_IMM_REG_MOVE,
 239   OP_COND_BR,
 240   OP_LOAD16,
 241   OP_STORE16,
 242   OP_LOAD32,
 243   OP_STORE32,
 244   OP_JUMP,
 245   OP_IMM_REG_REG,
 246   OP_UIMM_REG_REG,
 247   OP_BIT,
 248   OP_EX1,
 249   OP_EX2,
 250   OP_LDSR,
 251   OP_STSR,
 252 /* start-sanitize-v850e */
 253   OP_BIT_CHANGE,
 254   OP_REG_REG_REG,
 255   OP_REG_REG3,
 256 /* end-sanitize-v850e */
 257 /* start-sanitize-v850eq */
 258   OP_IMM_REG_REG_REG,
 259   OP_PUSHPOP1,
 260   OP_PUSHPOP2,
 261   OP_PUSHPOP3,
 262 /* end-sanitize-v850eq */
 263 };
 264
 265 #ifdef DEBUG
 266 void trace_input PARAMS ((char *name, enum op_types type, int size));
 267 void trace_output PARAMS ((enum op_types result));
 268 #else
 269 #define trace_input(NAME, IN1, IN2)
 270 #define trace_output(RESULT)
 271 #endif
 272
 273
 274 /* start-sanitize-v850eq */
 275 extern void divun ( unsigned int       N,
 276                     unsigned long int  als,
 277                     unsigned long int  sfi,
 278                     unsigned long int *  quotient_ptr,
 279                     unsigned long int *  remainder_ptr,
 280                     boolean *          overflow_ptr
 281                     );
 282 extern void divn ( unsigned int       N,
 283                    unsigned long int  als,
 284                    unsigned long int  sfi,
 285                    signed long int *  quotient_ptr,
 286                    signed long int *  remainder_ptr,
 287                    boolean *          overflow_ptr
 288                    );
 289 /* end-sanitize-v850eq */
 290 /* start-sanitize-v850e */
 291 extern int type1_regs[];
 292 extern int type2_regs[];
 293 /* end-sanitize-v850e */
 294 /* start-sanitize-v850eq */
 295 extern int type3_regs[];
 296 /* end-sanitize-v850eq */