4 /* General config options */
7 #define WITH_MODULO_MEMORY 1
8 #define WITH_WATCHPOINTS 1
11 /* The v850 has 32bit words, numbered 31 (MSB) to 0 (LSB) */
13 #define WITH_TARGET_WORD_MSB 31
16 #include "sim-basics.h"
17 #include "sim-signal.h"
19 typedef address_word sim_cia
;
28 typedef unsigned8 uint8
;
29 typedef signed16 int16
;
30 typedef unsigned16 uint16
;
31 typedef signed32 int32
;
32 typedef unsigned32 uint32
;
33 typedef unsigned32 reg_t
;
36 /* The current state of the processor; registers, memory, etc. */
38 typedef struct _v850_regs
{
39 reg_t regs
[32]; /* general-purpose registers */
40 reg_t sregs
[32]; /* system registers, including psw */
42 int dummy_mem
; /* where invalid accesses go */
47 /* ... simulator specific members ... */
49 reg_t psw_mask
; /* only allow non-reserved bits to be set */
50 sim_event
*pending_nmi
;
51 /* ... base type ... */
55 #define CIA_GET(CPU) ((CPU)->reg.pc + 0)
56 #define CIA_SET(CPU,VAL) ((CPU)->reg.pc = (VAL))
59 sim_cpu cpu
[MAX_NR_PROCESSORS
];
61 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
63 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
75 /* For compatibility, until all functions converted to passing
76 SIM_DESC as an argument */
77 extern SIM_DESC simulator
;
80 #define V850_ROM_SIZE 0x8000
81 #define V850_LOW_END 0x200000
82 #define V850_HIGH_START 0xffe000
85 /* Because we are still using the old semantic table, provide compat
86 macro's that store the instruction where the old simops expects
91 OP
[0] = inst
& 0x1f; /* RRRRR -> reg1 */
92 OP
[1] = (inst
>> 11) & 0x1f; /* rrrrr -> reg2 */
93 OP
[2] = (inst
>> 16) & 0xffff; /* wwwww -> reg3 OR imm16 */
99 OP[0] = instruction_0 & 0x1f; \
100 OP[1] = (instruction_0 >> 11) & 0x1f; \
102 OP[3] = instruction_0
104 #define COMPAT_1(CALL) \
111 OP[0] = instruction_0 & 0x1f; \
112 OP[1] = (instruction_0 >> 11) & 0x1f; \
113 OP[2] = instruction_1; \
114 OP[3] = (instruction_1 << 16) | instruction_0
116 #define COMPAT_2(CALL) \
123 #define GR ((CPU)->reg.regs)
124 #define SR ((CPU)->reg.sregs)
127 #define State (STATE_CPU (simulator, 0)->reg)
128 #define PC (State.pc)
129 #define SP (State.regs[3])
130 #define EP (State.regs[30])
132 #define EIPC (State.sregs[0])
133 #define EIPSW (State.sregs[1])
134 #define FEPC (State.sregs[2])
135 #define FEPSW (State.sregs[3])
136 #define ECR (State.sregs[4])
137 #define PSW (State.sregs[5])
138 #define CTPC (SR[16])
139 #define CTPSW (SR[17])
140 #define DBPC (State.sregs[18])
141 #define DBPSW (State.sregs[19])
142 #define CTBP (State.sregs[20])
144 #define PSW_US BIT32 (8)
154 #define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4)
156 /* sign-extend a 4-bit number */
157 #define SEXT4(x) ((((x)&0xf)^(~0x7))+0x8)
159 /* sign-extend a 5-bit number */
160 #define SEXT5(x) ((((x)&0x1f)^(~0xf))+0x10)
162 /* sign-extend a 9-bit number */
163 #define SEXT9(x) ((((x)&0x1ff)^(~0xff))+0x100)
165 /* sign-extend a 22-bit number */
166 #define SEXT22(x) ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
168 /* sign extend a 40 bit number */
169 #define SEXT40(x) ((((x) & UNSIGNED64 (0xffffffffff)) \
170 ^ (~UNSIGNED64 (0x7fffffffff))) \
171 + UNSIGNED64 (0x8000000000))
173 /* sign extend a 44 bit number */
174 #define SEXT44(x) ((((x) & UNSIGNED64 (0xfffffffffff)) \
175 ^ (~ UNSIGNED64 (0x7ffffffffff))) \
176 + UNSIGNED64 (0x80000000000))
178 /* sign extend a 60 bit number */
179 #define SEXT60(x) ((((x) & UNSIGNED64 (0xfffffffffffffff)) \
180 ^ (~ UNSIGNED64 (0x7ffffffffffffff))) \
181 + UNSIGNED64 (0x800000000000000))
183 /* No sign extension */
186 #define INC_ADDR(x,i) x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
188 #define RLW(x) load_mem (x, 4)
190 /* Function declarations. */
193 sim_core_read_aligned_2 (CPU, PC, exec_map, (EA))
195 #define IMEM16_IMMED(EA,N) \
196 sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
197 PC, exec_map, (EA) + (N) * 2)
199 #define load_mem(ADDR,LEN) \
200 sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \
201 PC, read_map, (ADDR))
203 #define store_mem(ADDR,LEN,DATA) \
204 sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
205 PC, write_map, (ADDR), (DATA))
208 /* compare cccc field against PSW */
209 int condition_met (unsigned code
);
212 /* Debug/tracing calls */
251 void trace_input
PARAMS ((char *name
, enum op_types type
, int size
));
252 void trace_output
PARAMS ((enum op_types result
));
253 void trace_result
PARAMS ((int has_result
, unsigned32 result
));
255 extern int trace_num_values
;
256 extern unsigned32 trace_values
[];
257 extern unsigned32 trace_pc
;
258 extern const char *trace_name
;
259 extern int trace_module
;
261 #define TRACE_BRANCH0() \
263 if (TRACE_BRANCH_P (CPU)) { \
264 trace_module = TRACE_BRANCH_IDX; \
266 trace_name = itable[MY_INDEX].name; \
267 trace_num_values = 0; \
268 trace_result (1, (nia)); \
272 #define TRACE_BRANCH1(IN1) \
274 if (TRACE_BRANCH_P (CPU)) { \
275 trace_module = TRACE_BRANCH_IDX; \
277 trace_name = itable[MY_INDEX].name; \
278 trace_values[0] = (IN1); \
279 trace_num_values = 1; \
280 trace_result (1, (nia)); \
284 #define TRACE_BRANCH2(IN1, IN2) \
286 if (TRACE_BRANCH_P (CPU)) { \
287 trace_module = TRACE_BRANCH_IDX; \
289 trace_name = itable[MY_INDEX].name; \
290 trace_values[0] = (IN1); \
291 trace_values[1] = (IN2); \
292 trace_num_values = 2; \
293 trace_result (1, (nia)); \
297 #define TRACE_BRANCH3(IN1, IN2, IN3) \
299 if (TRACE_BRANCH_P (CPU)) { \
300 trace_module = TRACE_BRANCH_IDX; \
302 trace_name = itable[MY_INDEX].name; \
303 trace_values[0] = (IN1); \
304 trace_values[1] = (IN2); \
305 trace_values[2] = (IN3); \
306 trace_num_values = 3; \
307 trace_result (1, (nia)); \
311 #define TRACE_LD(ADDR,RESULT) \
313 if (TRACE_MEMORY_P (CPU)) { \
314 trace_module = TRACE_MEMORY_IDX; \
316 trace_name = itable[MY_INDEX].name; \
317 trace_values[0] = (ADDR); \
318 trace_num_values = 1; \
319 trace_result (1, (RESULT)); \
323 #define TRACE_LD_NAME(NAME, ADDR,RESULT) \
325 if (TRACE_MEMORY_P (CPU)) { \
326 trace_module = TRACE_MEMORY_IDX; \
328 trace_name = (NAME); \
329 trace_values[0] = (ADDR); \
330 trace_num_values = 1; \
331 trace_result (1, (RESULT)); \
335 #define TRACE_ST(ADDR,RESULT) \
337 if (TRACE_MEMORY_P (CPU)) { \
338 trace_module = TRACE_MEMORY_IDX; \
340 trace_name = itable[MY_INDEX].name; \
341 trace_values[0] = (ADDR); \
342 trace_num_values = 1; \
343 trace_result (1, (RESULT)); \
348 #define trace_input(NAME, IN1, IN2)
349 #define trace_output(RESULT)
350 #define trace_result(HAS_RESULT, RESULT)
352 #define TRACE_ALU_INPUT0()
353 #define TRACE_ALU_INPUT1(IN0)
354 #define TRACE_ALU_INPUT2(IN0, IN1)
355 #define TRACE_ALU_INPUT2(IN0, IN1)
356 #define TRACE_ALU_INPUT2(IN0, IN1 INS2)
357 #define TRACE_ALU_RESULT(RESULT)
359 #define TRACE_BRANCH0()
360 #define TRACE_BRANCH1(IN1)
361 #define TRACE_BRANCH2(IN1, IN2)
362 #define TRACE_BRANCH2(IN1, IN2, IN3)
364 #define TRACE_LD(ADDR,RESULT)
365 #define TRACE_ST(ADDR,RESULT)
369 #define GPR_SET(N, VAL) (State.regs[(N)] = (VAL))
370 #define GPR_CLEAR(N) (State.regs[(N)] = 0)
372 extern void divun ( unsigned int N
,
373 unsigned long int als
,
374 unsigned long int sfi
,
375 unsigned32
/*unsigned long int*/ * quotient_ptr
,
376 unsigned32
/*unsigned long int*/ * remainder_ptr
,
379 extern void divn ( unsigned int N
,
380 unsigned long int als
,
381 unsigned long int sfi
,
382 signed32
/*signed long int*/ * quotient_ptr
,
383 signed32
/*signed long int*/ * remainder_ptr
,
386 extern int type1_regs
[];
387 extern int type2_regs
[];
388 extern int type3_regs
[];
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