projects / deliverable / binutils-gdb.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
o Wordwrap usage messages from sim-options
[deliverable/binutils-gdb.git] / sim / v850 / simops.c
1 #include <signal.h>
2 #include "sim-main.h"
3 #include "v850_sim.h"
4 #include "simops.h"
5
6 #ifdef HAVE_UTIME_H
7 #include <utime.h>
8 #endif
9
10 #ifdef HAVE_TIME_H
11 #include <time.h>
12 #endif
13
14 #ifdef HAVE_UNISTD_H
15 #include <unistd.h>
16 #endif
17
18 #ifdef HAVE_STRING_H
19 #include <string.h>
20 #else
21 #ifdef HAVE_STRINGS_H
22 #include <strings.h>
23 #endif
24 #endif
25
26
27
28
29
30 /* FIXME - should be including a version of syscall.h that does not
31 pollute the name space */
32 #include "../../libgloss/v850/sys/syscall.h"
33
34 #include "bfd.h"
35 #include "libiberty.h"
36
37 #include <errno.h>
38 #if !defined(__GO32__) && !defined(_WIN32)
39 #include <sys/stat.h>
40 #include <sys/times.h>
41 #include <sys/time.h>
42 #endif
43
44 enum op_types
45 {
46 OP_UNKNOWN,
47 OP_NONE,
48 OP_TRAP,
49 OP_REG,
50 OP_REG_REG,
51 OP_REG_REG_CMP,
52 OP_REG_REG_MOVE,
53 OP_IMM_REG,
54 OP_IMM_REG_CMP,
55 OP_IMM_REG_MOVE,
56 OP_COND_BR,
57 OP_LOAD16,
58 OP_STORE16,
59 OP_LOAD32,
60 OP_STORE32,
61 OP_JUMP,
62 OP_IMM_REG_REG,
63 OP_UIMM_REG_REG,
64 OP_BIT,
65 OP_EX1,
66 OP_EX2,
67 OP_LDSR,
68 OP_STSR,
69 /* start-sanitize-v850e */
70 OP_BIT_CHANGE,
71 OP_REG_REG_REG,
72 OP_REG_REG3,
73 /* end-sanitize-v850e */
74 /* start-sanitize-v850eq */
75 OP_IMM_REG_REG_REG,
76 OP_PUSHPOP1,
77 OP_PUSHPOP2,
78 OP_PUSHPOP3,
79 /* end-sanitize-v850eq */
80 };
81
82 /* start-sanitize-v850e */
83 /* This is an array of the bit positions of registers r20 .. r31 in that order in a prepare/dispose instruction. */
84 static int type1_regs[12] = { 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 0, 21 };
85 /* end-sanitize-v850e */
86 /* start-sanitize-v850eq */
87 /* This is an array of the bit positions of registers r16 .. r31 in that order in a push/pop instruction. */
88 static int type2_regs[16] = { 3, 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
89 /* This is an array of the bit positions of registers r1 .. r15 in that order in a push/pop instruction. */
90 static int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
91 /* end-sanitize-v850eq */
92
93 #ifdef DEBUG
94 static void trace_input PARAMS ((char *name, enum op_types type, int size));
95 static void trace_output PARAMS ((enum op_types result));
96
97 #ifndef SIZE_INSTRUCTION
98 #define SIZE_INSTRUCTION 6
99 #endif
100
101 #ifndef SIZE_OPERANDS
102 #define SIZE_OPERANDS 16
103 #endif
104
105 #ifndef SIZE_VALUES
106 #define SIZE_VALUES 11
107 #endif
108
109 #ifndef SIZE_LOCATION
110 #define SIZE_LOCATION 40
111 #endif
112
113
114 static void
115 trace_input (name, type, size)
116 char *name;
117 enum op_types type;
118 int size;
119 {
120 char buf[1024];
121 char *p;
122 uint32 values[3];
123 int num_values, i;
124 const char *filename;
125 const char *functionname;
126 unsigned int linenumber;
127
128 if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
129 return;
130
131 buf[0] = '\0';
132
133 if (STATE_TEXT_SECTION (simulator)
134 && PC >= STATE_TEXT_START (simulator)
135 && PC < STATE_TEXT_END (simulator))
136 {
137 filename = (const char *)0;
138 functionname = (const char *)0;
139 linenumber = 0;
140 if (bfd_find_nearest_line (STATE_PROG_BFD (simulator),
141 STATE_TEXT_SECTION (simulator),
142 (struct symbol_cache_entry **)0,
143 PC - STATE_TEXT_START (simulator),
144 &filename, &functionname, &linenumber))
145 {
146 p = buf;
147 if (linenumber)
148 {
149 sprintf (p, "Line %5d ", linenumber);
150 p += strlen (p);
151 }
152
153 if (functionname)
154 {
155 sprintf (p, "Func %s ", functionname);
156 p += strlen (p);
157 }
158 else if (filename)
159 {
160 char *q = (char *) strrchr (filename, '/');
161 sprintf (p, "File %s ", (q) ? q+1 : filename);
162 p += strlen (p);
163 }
164
165 if (*p == ' ')
166 *p = '\0';
167 }
168 }
169
170 trace_printf (simulator, STATE_CPU (simulator, 0),
171 "0x%.8x: %-*.*s %-*s",
172 (unsigned)PC,
173 SIZE_LOCATION, SIZE_LOCATION, buf,
174 SIZE_INSTRUCTION, name);
175
176 #if 0
177 switch (type)
178 {
179 default:
180 case OP_UNKNOWN:
181 case OP_NONE:
182 strcpy (buf, "unknown");
183 break;
184
185 case OP_TRAP:
186 sprintf (buf, "%ld", OP[0]);
187 break;
188
189 case OP_REG:
190 sprintf (buf, "r%ld", OP[0]);
191 break;
192
193 case OP_REG_REG:
194 case OP_REG_REG_CMP:
195 case OP_REG_REG_MOVE:
196 sprintf (buf, "r%ld,r%ld", OP[0], OP[1]);
197 break;
198
199 case OP_IMM_REG:
200 case OP_IMM_REG_CMP:
201 case OP_IMM_REG_MOVE:
202 sprintf (buf, "%ld,r%ld", OP[0], OP[1]);
203 break;
204
205 case OP_COND_BR:
206 sprintf (buf, "%ld", SEXT9 (OP[0]));
207 break;
208
209 case OP_LOAD16:
210 sprintf (buf, "%ld[r30],r%ld", OP[1] * size, OP[0]);
211 break;
212
213 case OP_STORE16:
214 sprintf (buf, "r%ld,%ld[r30]", OP[0], OP[1] * size);
215 break;
216
217 case OP_LOAD32:
218 sprintf (buf, "%ld[r%ld],r%ld", EXTEND16 (OP[2]) & ~0x1, OP[0], OP[1]);
219 break;
220
221 case OP_STORE32:
222 sprintf (buf, "r%ld,%ld[r%ld]", OP[1], EXTEND16 (OP[2] & ~0x1), OP[0]);
223 break;
224
225 case OP_JUMP:
226 sprintf (buf, "%ld,r%ld", SEXT22 (OP[0]), OP[1]);
227 break;
228
229 case OP_IMM_REG_REG:
230 sprintf (buf, "%ld,r%ld,r%ld", EXTEND16 (OP[0]), OP[1], OP[2]);
231 break;
232
233 case OP_UIMM_REG_REG:
234 sprintf (buf, "%ld,r%ld,r%ld", OP[0] & 0xffff, OP[1], OP[2]);
235 break;
236
237 case OP_BIT:
238 sprintf (buf, "%ld,%ld[r%ld]", OP[1] & 0x7, EXTEND16 (OP[2]), OP[0]);
239 break;
240
241 case OP_EX1:
242 {
243 char *cond;
244 switch (OP[0] & 0xf)
245 {
246 default: cond = "?"; break;
247 case 0x0: cond = "v"; break;
248 case 0x1: cond = "c"; break;
249 case 0x2: cond = "z"; break;
250 case 0x3: cond = "nh"; break;
251 case 0x4: cond = "s"; break;
252 case 0x5: cond = "t"; break;
253 case 0x6: cond = "lt"; break;
254 case 0x7: cond = "le"; break;
255 case 0x8: cond = "nv"; break;
256 case 0x9: cond = "nc"; break;
257 case 0xa: cond = "nz"; break;
258 case 0xb: cond = "h"; break;
259 case 0xc: cond = "ns"; break;
260 case 0xd: cond = "sa"; break;
261 case 0xe: cond = "ge"; break;
262 case 0xf: cond = "gt"; break;
263 }
264 sprintf (buf, "%s,r%ld", cond, OP[1]);
265 break;
266 }
267
268 case OP_EX2:
269 strcpy (buf, "EX2");
270 break;
271
272 case OP_LDSR:
273 case OP_STSR:
274 sprintf (buf, "r%ld,s%ld", OP[0], OP[1]);
275 break;
276
277 case OP_PUSHPOP1:
278 for (i = 0; i < 12; i++)
279 if (OP[3] & (1 << type1_regs[i]))
280 sprintf (strchr (buf, 0), "r%d ", i + 20);
281 break;
282
283 case OP_PUSHPOP2:
284 for (i = 0; i < 16; i++)
285 if (OP[3] & (1 << type2_regs[i]))
286 sprintf (strchr (buf, 0), "r%d ", i + 16);
287 if (OP[3] & (1 << 19))
288 strcat (buf, "F/EIPC, F/EIPSW " );
289 break;
290
291 case OP_PUSHPOP3:
292 for (i = 0; i < 15; i++)
293 if (OP[3] & (1 << type3_regs[i]))
294 sprintf (strchr (buf, 0), "r%d ", i + 1);
295 if (OP[3] & (1 << 3))
296 strcat (buf, "PSW " );
297 if (OP[3] & (1 << 19))
298 strcat (buf, "F/EIPC, F/EIPSW " );
299 break;
300
301 case OP_BIT_CHANGE:
302 sprintf (buf, "r%ld, [r%ld]", OP[1], OP[0] );
303 break;
304 }
305 #endif
306
307 if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
308 {
309 trace_printf (simulator, STATE_CPU (simulator, 0),
310 "%s\n", buf);
311 }
312 else
313 {
314 #if 0
315 trace_printf (simulator, STATE_CPU (simulator, 0),
316 "%-*s", SIZE_OPERANDS, buf);
317 #endif
318 switch (type)
319 {
320 default:
321 case OP_UNKNOWN:
322 case OP_NONE:
323 case OP_TRAP:
324 num_values = 0;
325 break;
326
327 case OP_REG:
328 case OP_REG_REG_MOVE:
329 values[0] = State.regs[OP[0]];
330 num_values = 1;
331 break;
332
333 case OP_BIT_CHANGE:
334 case OP_REG_REG:
335 case OP_REG_REG_CMP:
336 values[0] = State.regs[OP[1]];
337 values[1] = State.regs[OP[0]];
338 num_values = 2;
339 break;
340
341 case OP_IMM_REG:
342 case OP_IMM_REG_CMP:
343 values[0] = SEXT5 (OP[0]);
344 values[1] = OP[1];
345 num_values = 2;
346 break;
347
348 case OP_IMM_REG_MOVE:
349 values[0] = SEXT5 (OP[0]);
350 num_values = 1;
351 break;
352
353 case OP_COND_BR:
354 values[0] = State.pc;
355 values[1] = SEXT9 (OP[0]);
356 values[2] = PSW;
357 num_values = 3;
358 break;
359
360 case OP_LOAD16:
361 values[0] = OP[1] * size;
362 values[1] = State.regs[30];
363 num_values = 2;
364 break;
365
366 case OP_STORE16:
367 values[0] = State.regs[OP[0]];
368 values[1] = OP[1] * size;
369 values[2] = State.regs[30];
370 num_values = 3;
371 break;
372
373 case OP_LOAD32:
374 values[0] = EXTEND16 (OP[2]);
375 values[1] = State.regs[OP[0]];
376 num_values = 2;
377 break;
378
379 case OP_STORE32:
380 values[0] = State.regs[OP[1]];
381 values[1] = EXTEND16 (OP[2]);
382 values[2] = State.regs[OP[0]];
383 num_values = 3;
384 break;
385
386 case OP_JUMP:
387 values[0] = SEXT22 (OP[0]);
388 values[1] = State.pc;
389 num_values = 2;
390 break;
391
392 case OP_IMM_REG_REG:
393 values[0] = EXTEND16 (OP[0]) << size;
394 values[1] = State.regs[OP[1]];
395 num_values = 2;
396 break;
397
398 case OP_UIMM_REG_REG:
399 values[0] = (OP[0] & 0xffff) << size;
400 values[1] = State.regs[OP[1]];
401 num_values = 2;
402 break;
403
404 case OP_BIT:
405 num_values = 0;
406 break;
407
408 case OP_EX1:
409 values[0] = PSW;
410 num_values = 1;
411 break;
412
413 case OP_EX2:
414 num_values = 0;
415 break;
416
417 case OP_LDSR:
418 values[0] = State.regs[OP[0]];
419 num_values = 1;
420 break;
421
422 case OP_STSR:
423 values[0] = State.sregs[OP[1]];
424 num_values = 1;
425 }
426
427 for (i = 0; i < num_values; i++)
428 trace_printf (simulator, STATE_CPU (simulator, 0),
429 "%*s0x%.8lx", SIZE_VALUES - 10, "", values[i]);
430
431 while (i++ < 3)
432 trace_printf (simulator, STATE_CPU (simulator, 0),
433 "%*s", SIZE_VALUES, "");
434 }
435 }
436
437 static void
438 trace_output (result)
439 enum op_types result;
440 {
441 if (TRACE_ALU_P (STATE_CPU (simulator, 0)))
442 {
443 switch (result)
444 {
445 default:
446 case OP_UNKNOWN:
447 case OP_NONE:
448 case OP_TRAP:
449 case OP_REG:
450 case OP_REG_REG_CMP:
451 case OP_IMM_REG_CMP:
452 case OP_COND_BR:
453 case OP_STORE16:
454 case OP_STORE32:
455 case OP_BIT:
456 case OP_EX2:
457 break;
458
459 case OP_LOAD16:
460 case OP_STSR:
461 trace_printf (simulator, STATE_CPU (simulator, 0),
462 " :: 0x%.8lx", (unsigned long)State.regs[OP[0]]);
463 break;
464
465 case OP_REG_REG:
466 case OP_REG_REG_MOVE:
467 case OP_IMM_REG:
468 case OP_IMM_REG_MOVE:
469 case OP_LOAD32:
470 case OP_EX1:
471 trace_printf (simulator, STATE_CPU (simulator, 0),
472 " :: 0x%.8lx", (unsigned long)State.regs[OP[1]]);
473 break;
474
475 case OP_IMM_REG_REG:
476 case OP_UIMM_REG_REG:
477 trace_printf (simulator, STATE_CPU (simulator, 0),
478 " :: 0x%.8lx", (unsigned long)State.regs[OP[2]]);
479 break;
480
481 case OP_JUMP:
482 if (OP[1] != 0)
483 trace_printf (simulator, STATE_CPU (simulator, 0),
484 " :: 0x%.8lx", (unsigned long)State.regs[OP[1]]);
485 break;
486
487 case OP_LDSR:
488 trace_printf (simulator, STATE_CPU (simulator, 0),
489 " :: 0x%.8lx", (unsigned long)State.sregs[OP[1]]);
490 break;
491 }
492
493 trace_printf (simulator, STATE_CPU (simulator, 0),
494 "\n");
495 }
496 }
497
498 #else
499 #define trace_input(NAME, IN1, IN2)
500 #define trace_output(RESULT)
501
502 /* #define trace_input(NAME, IN1, IN2) fprintf (stderr, NAME "\n" ); */
503
504 #endif
505
506 \f
507 /* Returns 1 if the specific condition is met, returns 0 otherwise. */
508 static unsigned int
509 condition_met (unsigned code)
510 {
511 unsigned int psw = PSW;
512
513 switch (code & 0xf)
514 {
515 case 0x0: return ((psw & PSW_OV) != 0);
516 case 0x1: return ((psw & PSW_CY) != 0);
517 case 0x2: return ((psw & PSW_Z) != 0);
518 case 0x3: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
519 case 0x4: return ((psw & PSW_S) != 0);
520 /*case 0x5: return 1;*/
521 case 0x6: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
522 case 0x7: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) != 0);
523 case 0x8: return ((psw & PSW_OV) == 0);
524 case 0x9: return ((psw & PSW_CY) == 0);
525 case 0xa: return ((psw & PSW_Z) == 0);
526 case 0xb: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
527 case 0xc: return ((psw & PSW_S) == 0);
528 case 0xd: return ((psw & PSW_SAT) != 0);
529 case 0xe: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
530 case 0xf: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) == 0);
531 }
532
533 return 1;
534 }
535
536 static unsigned long
537 Add32 (unsigned long a1, unsigned long a2, int * carry)
538 {
539 unsigned long result = (a1 + a2);
540
541 * carry = (result < a1);
542
543 return result;
544 }
545
546 static void
547 Multiply64 (boolean sign, unsigned long op0)
548 {
549 unsigned long op1;
550 unsigned long lo;
551 unsigned long mid1;
552 unsigned long mid2;
553 unsigned long hi;
554 unsigned long RdLo;
555 unsigned long RdHi;
556 int carry;
557
558 op1 = State.regs[ OP[1] ];
559
560 if (sign)
561 {
562 /* Compute sign of result and adjust operands if necessary. */
563
564 sign = (op0 ^ op1) & 0x80000000;
565
566 if (((signed long) op0) < 0)
567 op0 = - op0;
568
569 if (((signed long) op1) < 0)
570 op1 = - op1;
571 }
572
573 /* We can split the 32x32 into four 16x16 operations. This ensures
574 that we do not lose precision on 32bit only hosts: */
575 lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF));
576 mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
577 mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF));
578 hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
579
580 /* We now need to add all of these results together, taking care
581 to propogate the carries from the additions: */
582 RdLo = Add32 (lo, (mid1 << 16), & carry);
583 RdHi = carry;
584 RdLo = Add32 (RdLo, (mid2 << 16), & carry);
585 RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi);
586
587 if (sign)
588 {
589 /* Negate result if necessary. */
590
591 RdLo = ~ RdLo;
592 RdHi = ~ RdHi;
593 if (RdLo == 0xFFFFFFFF)
594 {
595 RdLo = 0;
596 RdHi += 1;
597 }
598 else
599 RdLo += 1;
600 }
601
602 State.regs[ OP[1] ] = RdLo;
603 State.regs[ OP[2] >> 11 ] = RdHi;
604
605 return;
606 }
607
608 \f
609 /* Read a null terminated string from memory, return in a buffer */
610 static char *
611 fetch_str (sd, addr)
612 SIM_DESC sd;
613 address_word addr;
614 {
615 char *buf;
616 int nr = 0;
617 while (sim_core_read_1 (STATE_CPU (sd, 0),
618 PC, sim_core_read_map, addr + nr) != 0)
619 nr++;
620 buf = NZALLOC (char, nr + 1);
621 sim_read (simulator, addr, buf, nr);
622 return buf;
623 }
624
625 /* Read a null terminated argument vector from memory, return in a
626 buffer */
627 static char **
628 fetch_argv (sd, addr)
629 SIM_DESC sd;
630 address_word addr;
631 {
632 int max_nr = 64;
633 int nr = 0;
634 char **buf = xmalloc (max_nr * sizeof (char*));
635 while (1)
636 {
637 unsigned32 a = sim_core_read_4 (STATE_CPU (sd, 0),
638 PC, sim_core_read_map, addr + nr * 4);
639 if (a == 0) break;
640 buf[nr] = fetch_str (sd, a);
641 nr ++;
642 if (nr == max_nr - 1)
643 {
644 max_nr += 50;
645 buf = xrealloc (buf, max_nr * sizeof (char*));
646 }
647 }
648 buf[nr] = 0;
649 return buf;
650 }
651
652 \f
653 /* sld.b */
654 int
655 OP_300 ()
656 {
657 unsigned long result;
658
659 result = load_mem (State.regs[30] + (OP[3] & 0x7f), 1);
660
661 /* start-sanitize-v850eq */
662 #ifdef ARCH_v850eq
663 trace_input ("sld.bu", OP_LOAD16, 1);
664
665 State.regs[ OP[1] ] = result;
666 #else
667 /* end-sanitize-v850eq */
668 trace_input ("sld.b", OP_LOAD16, 1);
669
670 State.regs[ OP[1] ] = EXTEND8 (result);
671 /* start-sanitize-v850eq */
672 #endif
673 /* end-sanitize-v850eq */
674
675 trace_output (OP_LOAD16);
676
677 return 2;
678 }
679
680 /* sld.h */
681 int
682 OP_400 ()
683 {
684 unsigned long result;
685
686 result = load_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2);
687
688 /* start-sanitize-v850eq */
689 #ifdef ARCH_v850eq
690 trace_input ("sld.hu", OP_LOAD16, 2);
691
692 State.regs[ OP[1] ] = result;
693 #else
694 /* end-sanitize-v850eq */
695 trace_input ("sld.h", OP_LOAD16, 2);
696
697 State.regs[ OP[1] ] = EXTEND16 (result);
698 /* start-sanitize-v850eq */
699 #endif
700 /* end-sanitize-v850eq */
701
702 trace_output (OP_LOAD16);
703
704 return 2;
705 }
706
707 /* sld.w */
708 int
709 OP_500 ()
710 {
711 trace_input ("sld.w", OP_LOAD16, 4);
712
713 State.regs[ OP[1] ] = load_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 4);
714
715 trace_output (OP_LOAD16);
716
717 return 2;
718 }
719
720 /* sst.b */
721 int
722 OP_380 ()
723 {
724 trace_input ("sst.b", OP_STORE16, 1);
725
726 store_mem (State.regs[30] + (OP[3] & 0x7f), 1, State.regs[ OP[1] ]);
727
728 trace_output (OP_STORE16);
729
730 return 2;
731 }
732
733 /* sst.h */
734 int
735 OP_480 ()
736 {
737 trace_input ("sst.h", OP_STORE16, 2);
738
739 store_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2, State.regs[ OP[1] ]);
740
741 trace_output (OP_STORE16);
742
743 return 2;
744 }
745
746 /* sst.w */
747 int
748 OP_501 ()
749 {
750 trace_input ("sst.w", OP_STORE16, 4);
751
752 store_mem (State.regs[30] + ((OP[3] & 0x7e) << 1), 4, State.regs[ OP[1] ]);
753
754 trace_output (OP_STORE16);
755
756 return 2;
757 }
758
759 /* ld.b */
760 int
761 OP_700 ()
762 {
763 int adr;
764
765 trace_input ("ld.b", OP_LOAD32, 1);
766
767 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
768
769 State.regs[ OP[1] ] = EXTEND8 (load_mem (adr, 1));
770
771 trace_output (OP_LOAD32);
772
773 return 4;
774 }
775
776 /* ld.h */
777 int
778 OP_720 ()
779 {
780 int adr;
781
782 trace_input ("ld.h", OP_LOAD32, 2);
783
784 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
785 adr &= ~0x1;
786
787 State.regs[ OP[1] ] = EXTEND16 (load_mem (adr, 2));
788
789 trace_output (OP_LOAD32);
790
791 return 4;
792 }
793
794 /* ld.w */
795 int
796 OP_10720 ()
797 {
798 int adr;
799
800 trace_input ("ld.w", OP_LOAD32, 4);
801
802 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
803 adr &= ~0x3;
804
805 State.regs[ OP[1] ] = load_mem (adr, 4);
806
807 trace_output (OP_LOAD32);
808
809 return 4;
810 }
811
812 /* st.b */
813 int
814 OP_740 ()
815 {
816 trace_input ("st.b", OP_STORE32, 1);
817
818 store_mem (State.regs[ OP[0] ] + EXTEND16 (OP[2]), 1, State.regs[ OP[1] ]);
819
820 trace_output (OP_STORE32);
821
822 return 4;
823 }
824
825 /* st.h */
826 int
827 OP_760 ()
828 {
829 int adr;
830
831 trace_input ("st.h", OP_STORE32, 2);
832
833 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
834 adr &= ~1;
835
836 store_mem (adr, 2, State.regs[ OP[1] ]);
837
838 trace_output (OP_STORE32);
839
840 return 4;
841 }
842
843 /* st.w */
844 int
845 OP_10760 ()
846 {
847 int adr;
848
849 trace_input ("st.w", OP_STORE32, 4);
850
851 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
852 adr &= ~3;
853
854 store_mem (adr, 4, State.regs[ OP[1] ]);
855
856 trace_output (OP_STORE32);
857
858 return 4;
859 }
860
861 static int
862 branch (int code)
863 {
864 trace_input ("Bcond", OP_COND_BR, 0);
865 trace_output (OP_COND_BR);
866
867 if (condition_met (code))
868 return SEXT9 (((OP[3] & 0x70) >> 3) | ((OP[3] & 0xf800) >> 7));
869 else
870 return 2;
871 }
872
873 /* bv disp9 */
874 int
875 OP_580 ()
876 {
877 return branch (0);
878 }
879
880 /* bl disp9 */
881 int
882 OP_581 ()
883 {
884 return branch (1);
885 }
886
887 /* be disp9 */
888 int
889 OP_582 ()
890 {
891 return branch (2);
892 }
893
894 /* bnh disp 9*/
895 int
896 OP_583 ()
897 {
898 return branch (3);
899 }
900
901 /* bn disp9 */
902 int
903 OP_584 ()
904 {
905 return branch (4);
906 }
907
908 /* br disp9 */
909 int
910 OP_585 ()
911 {
912 return branch (5);
913 }
914
915 /* blt disp9 */
916 int
917 OP_586 ()
918 {
919 return branch (6);
920 }
921
922 /* ble disp9 */
923 int
924 OP_587 ()
925 {
926 return branch (7);
927 }
928
929 /* bnv disp9 */
930 int
931 OP_588 ()
932 {
933 return branch (8);
934 }
935
936 /* bnl disp9 */
937 int
938 OP_589 ()
939 {
940 return branch (9);
941 }
942
943 /* bne disp9 */
944 int
945 OP_58A ()
946 {
947 return branch (10);
948 }
949
950 /* bh disp9 */
951 int
952 OP_58B ()
953 {
954 return branch (11);
955 }
956
957 /* bp disp9 */
958 int
959 OP_58C ()
960 {
961 return branch (12);
962 }
963
964 /* bsa disp9 */
965 int
966 OP_58D ()
967 {
968 return branch (13);
969 }
970
971 /* bge disp9 */
972 int
973 OP_58E ()
974 {
975 return branch (14);
976 }
977
978 /* bgt disp9 */
979 int
980 OP_58F ()
981 {
982 return branch (15);
983 }
984
985 /* jmp [reg1] */
986 /* sld.bu disp4[ep], reg2 */
987 int
988 OP_60 ()
989 {
990 if (OP[1] == 0)
991 {
992 trace_input ("jmp", OP_REG, 0);
993
994 PC = State.regs[ OP[0] ];
995
996 trace_output (OP_REG);
997
998 return 0; /* Add nothing to the PC, we have already done it. */
999 }
1000 /* start-sanitize-v850e */
1001 else
1002 {
1003 unsigned long result;
1004
1005 result = load_mem (State.regs[30] + (OP[3] & 0xf), 1);
1006
1007 /* start-sanitize-v850eq */
1008 #ifdef ARCH_v850eq
1009 trace_input ("sld.b", OP_LOAD16, 1);
1010
1011 State.regs[ OP[1] ] = EXTEND8 (result);
1012 #else
1013 /* end-sanitize-v850eq */
1014 trace_input ("sld.bu", OP_LOAD16, 1);
1015
1016 State.regs[ OP[1] ] = result;
1017 /* start-sanitize-v850eq */
1018 #endif
1019 /* end-sanitize-v850eq */
1020
1021 trace_output (OP_LOAD16);
1022
1023 return 2;
1024 }
1025 /* end-sanitize-v850e */
1026 }
1027
1028 /* jarl/jr disp22, reg */
1029 int
1030 OP_780 ()
1031 {
1032 trace_input ("jarl/jr", OP_JUMP, 0);
1033
1034 if (OP[ 1 ] != 0)
1035 State.regs[ OP[1] ] = PC + 4;
1036
1037 trace_output (OP_JUMP);
1038
1039 return SEXT22 (((OP[3] & 0x3f) << 16) | OP[2]);
1040 }
1041
1042 /* add reg, reg */
1043 int
1044 OP_1C0 ()
1045 {
1046 unsigned int op0, op1, result, z, s, cy, ov;
1047
1048 trace_input ("add", OP_REG_REG, 0);
1049
1050 /* Compute the result. */
1051
1052 op0 = State.regs[ OP[0] ];
1053 op1 = State.regs[ OP[1] ];
1054
1055 result = op0 + op1;
1056
1057 /* Compute the condition codes. */
1058 z = (result == 0);
1059 s = (result & 0x80000000);
1060 cy = (result < op0 || result < op1);
1061 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1062 && (op0 & 0x80000000) != (result & 0x80000000));
1063
1064 /* Store the result and condition codes. */
1065 State.regs[OP[1]] = result;
1066 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1067 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1068 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1069 trace_output (OP_REG_REG);
1070
1071 return 2;
1072 }
1073
1074 /* add sign_extend(imm5), reg */
1075 int
1076 OP_240 ()
1077 {
1078 unsigned int op0, op1, result, z, s, cy, ov;
1079 int temp;
1080
1081 trace_input ("add", OP_IMM_REG, 0);
1082
1083 /* Compute the result. */
1084 temp = SEXT5 (OP[0]);
1085 op0 = temp;
1086 op1 = State.regs[OP[1]];
1087 result = op0 + op1;
1088
1089 /* Compute the condition codes. */
1090 z = (result == 0);
1091 s = (result & 0x80000000);
1092 cy = (result < op0 || result < op1);
1093 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1094 && (op0 & 0x80000000) != (result & 0x80000000));
1095
1096 /* Store the result and condition codes. */
1097 State.regs[OP[1]] = result;
1098 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1099 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1100 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1101 trace_output (OP_IMM_REG);
1102
1103 return 2;
1104 }
1105
1106 /* addi sign_extend(imm16), reg, reg */
1107 int
1108 OP_600 ()
1109 {
1110 unsigned int op0, op1, result, z, s, cy, ov;
1111
1112 trace_input ("addi", OP_IMM_REG_REG, 0);
1113
1114 /* Compute the result. */
1115
1116 op0 = EXTEND16 (OP[2]);
1117 op1 = State.regs[ OP[0] ];
1118 result = op0 + op1;
1119
1120 /* Compute the condition codes. */
1121 z = (result == 0);
1122 s = (result & 0x80000000);
1123 cy = (result < op0 || result < op1);
1124 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1125 && (op0 & 0x80000000) != (result & 0x80000000));
1126
1127 /* Store the result and condition codes. */
1128 State.regs[OP[1]] = result;
1129 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1130 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1131 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1132 trace_output (OP_IMM_REG_REG);
1133
1134 return 4;
1135 }
1136
1137 /* sub reg1, reg2 */
1138 int
1139 OP_1A0 ()
1140 {
1141 unsigned int op0, op1, result, z, s, cy, ov;
1142
1143 trace_input ("sub", OP_REG_REG, 0);
1144 /* Compute the result. */
1145 op0 = State.regs[ OP[0] ];
1146 op1 = State.regs[ OP[1] ];
1147 result = op1 - op0;
1148
1149 /* Compute the condition codes. */
1150 z = (result == 0);
1151 s = (result & 0x80000000);
1152 cy = (op1 < op0);
1153 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1154 && (op1 & 0x80000000) != (result & 0x80000000));
1155
1156 /* Store the result and condition codes. */
1157 State.regs[OP[1]] = result;
1158 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1159 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1160 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1161 trace_output (OP_REG_REG);
1162
1163 return 2;
1164 }
1165
1166 /* subr reg1, reg2 */
1167 int
1168 OP_180 ()
1169 {
1170 unsigned int op0, op1, result, z, s, cy, ov;
1171
1172 trace_input ("subr", OP_REG_REG, 0);
1173 /* Compute the result. */
1174 op0 = State.regs[ OP[0] ];
1175 op1 = State.regs[ OP[1] ];
1176 result = op0 - op1;
1177
1178 /* Compute the condition codes. */
1179 z = (result == 0);
1180 s = (result & 0x80000000);
1181 cy = (op0 < op1);
1182 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
1183 && (op0 & 0x80000000) != (result & 0x80000000));
1184
1185 /* Store the result and condition codes. */
1186 State.regs[OP[1]] = result;
1187 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1188 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1189 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1190 trace_output (OP_REG_REG);
1191
1192 return 2;
1193 }
1194
1195 /* sxh reg1 */
1196 /* mulh reg1, reg2 */
1197 int
1198 OP_E0 ()
1199 {
1200 /* start-sanitize-v850e */
1201 if (OP[1] == 0)
1202 {
1203 trace_input ("sxh", OP_REG, 0);
1204
1205 State.regs[ OP[0] ] = EXTEND16 (State.regs[ OP[0] ]);
1206
1207 trace_output (OP_REG);
1208 }
1209 else
1210 /* end-sanitize-v850e */
1211 {
1212 trace_input ("mulh", OP_REG_REG, 0);
1213
1214 State.regs[ OP[1] ] = (EXTEND16 (State.regs[ OP[1] ]) * EXTEND16 (State.regs[ OP[0] ]));
1215
1216 trace_output (OP_REG_REG);
1217 }
1218
1219 return 2;
1220 }
1221
1222 /* mulh sign_extend(imm5), reg2 */
1223 int
1224 OP_2E0 ()
1225 {
1226 trace_input ("mulh", OP_IMM_REG, 0);
1227
1228 State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[1] ]) * SEXT5 (OP[0]);
1229
1230 trace_output (OP_IMM_REG);
1231
1232 return 2;
1233 }
1234
1235 /* mulhi imm16, reg1, reg2 */
1236 int
1237 OP_6E0 ()
1238 {
1239 if (OP[1] == 0)
1240 {
1241 }
1242 else
1243 {
1244 trace_input ("mulhi", OP_IMM_REG_REG, 0);
1245
1246 State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[0] ]) * EXTEND16 (OP[2]);
1247
1248 trace_output (OP_IMM_REG_REG);
1249 }
1250
1251 return 4;
1252 }
1253
1254 /* divh reg1, reg2 */
1255 /* switch reg1 */
1256 int
1257 OP_40 ()
1258 {
1259 /* start-sanitize-v850e */
1260 if (OP[1] == 0)
1261 {
1262 unsigned long adr;
1263
1264 trace_input ("switch", OP_REG, 0);
1265
1266 adr = State.pc + 2 + (State.regs[ OP[0] ] << 1);
1267 State.pc = State.pc + 2 + (EXTEND16 (load_mem (adr, 2)) << 1);
1268
1269 trace_output (OP_REG);
1270 }
1271 else
1272 /* end-sanitize-v850e */
1273 {
1274 unsigned int op0, op1, result, ov, s, z;
1275 int temp;
1276
1277 trace_input ("divh", OP_REG_REG, 0);
1278
1279 /* Compute the result. */
1280 temp = EXTEND16 (State.regs[ OP[0] ]);
1281 op0 = temp;
1282 op1 = State.regs[OP[1]];
1283
1284 if (op0 == 0xffffffff && op1 == 0x80000000)
1285 {
1286 result = 0x80000000;
1287 ov = 1;
1288 }
1289 else if (op0 != 0)
1290 {
1291 result = op1 / op0;
1292 ov = 0;
1293 }
1294 else
1295 {
1296 result = 0x0;
1297 ov = 1;
1298 }
1299
1300 /* Compute the condition codes. */
1301 z = (result == 0);
1302 s = (result & 0x80000000);
1303
1304 /* Store the result and condition codes. */
1305 State.regs[OP[1]] = result;
1306 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1307 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1308 | (ov ? PSW_OV : 0));
1309 trace_output (OP_REG_REG);
1310 }
1311
1312 return 2;
1313 }
1314
1315 /* cmp reg, reg */
1316 int
1317 OP_1E0 ()
1318 {
1319 unsigned int op0, op1, result, z, s, cy, ov;
1320
1321 trace_input ("cmp", OP_REG_REG_CMP, 0);
1322 /* Compute the result. */
1323 op0 = State.regs[ OP[0] ];
1324 op1 = State.regs[ OP[1] ];
1325 result = op1 - op0;
1326
1327 /* Compute the condition codes. */
1328 z = (result == 0);
1329 s = (result & 0x80000000);
1330 cy = (op1 < op0);
1331 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1332 && (op1 & 0x80000000) != (result & 0x80000000));
1333
1334 /* Set condition codes. */
1335 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1336 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1337 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1338 trace_output (OP_REG_REG_CMP);
1339
1340 return 2;
1341 }
1342
1343 /* cmp sign_extend(imm5), reg */
1344 int
1345 OP_260 ()
1346 {
1347 unsigned int op0, op1, result, z, s, cy, ov;
1348 int temp;
1349
1350 /* Compute the result. */
1351 trace_input ("cmp", OP_IMM_REG_CMP, 0);
1352 temp = SEXT5 (OP[0]);
1353 op0 = temp;
1354 op1 = State.regs[OP[1]];
1355 result = op1 - op0;
1356
1357 /* Compute the condition codes. */
1358 z = (result == 0);
1359 s = (result & 0x80000000);
1360 cy = (op1 < op0);
1361 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1362 && (op1 & 0x80000000) != (result & 0x80000000));
1363
1364 /* Set condition codes. */
1365 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1366 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1367 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1368 trace_output (OP_IMM_REG_CMP);
1369
1370 return 2;
1371 }
1372
1373 /* setf cccc,reg2 */
1374 int
1375 OP_7E0 ()
1376 {
1377 trace_input ("setf", OP_EX1, 0);
1378
1379 State.regs[ OP[1] ] = condition_met (OP[0]);
1380
1381 trace_output (OP_EX1);
1382
1383 return 4;
1384 }
1385
1386 /* zxh reg1 */
1387 /* satadd reg,reg */
1388 int
1389 OP_C0 ()
1390 {
1391 /* start-sanitize-v850e */
1392 if (OP[1] == 0)
1393 {
1394 trace_input ("zxh", OP_REG, 0);
1395
1396 State.regs[ OP[0] ] &= 0xffff;
1397
1398 trace_output (OP_REG);
1399 }
1400 else
1401 /* end-sanitize-v850e */
1402 {
1403 unsigned int op0, op1, result, z, s, cy, ov, sat;
1404
1405 trace_input ("satadd", OP_REG_REG, 0);
1406 /* Compute the result. */
1407 op0 = State.regs[ OP[0] ];
1408 op1 = State.regs[ OP[1] ];
1409 result = op0 + op1;
1410
1411 /* Compute the condition codes. */
1412 z = (result == 0);
1413 s = (result & 0x80000000);
1414 cy = (result < op0 || result < op1);
1415 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1416 && (op0 & 0x80000000) != (result & 0x80000000));
1417 sat = ov;
1418
1419 /* Store the result and condition codes. */
1420 State.regs[OP[1]] = result;
1421 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1422 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1423 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1424 | (sat ? PSW_SAT : 0));
1425
1426 /* Handle saturated results. */
1427 if (sat && s)
1428 State.regs[OP[1]] = 0x80000000;
1429 else if (sat)
1430 State.regs[OP[1]] = 0x7fffffff;
1431 trace_output (OP_REG_REG);
1432 }
1433
1434 return 2;
1435 }
1436
1437 /* satadd sign_extend(imm5), reg */
1438 int
1439 OP_220 ()
1440 {
1441 unsigned int op0, op1, result, z, s, cy, ov, sat;
1442
1443 int temp;
1444
1445 trace_input ("satadd", OP_IMM_REG, 0);
1446
1447 /* Compute the result. */
1448 temp = SEXT5 (OP[0]);
1449 op0 = temp;
1450 op1 = State.regs[OP[1]];
1451 result = op0 + op1;
1452
1453 /* Compute the condition codes. */
1454 z = (result == 0);
1455 s = (result & 0x80000000);
1456 cy = (result < op0 || result < op1);
1457 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1458 && (op0 & 0x80000000) != (result & 0x80000000));
1459 sat = ov;
1460
1461 /* Store the result and condition codes. */
1462 State.regs[OP[1]] = result;
1463 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1464 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1465 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1466 | (sat ? PSW_SAT : 0));
1467
1468 /* Handle saturated results. */
1469 if (sat && s)
1470 State.regs[OP[1]] = 0x80000000;
1471 else if (sat)
1472 State.regs[OP[1]] = 0x7fffffff;
1473 trace_output (OP_IMM_REG);
1474
1475 return 2;
1476 }
1477
1478 /* satsub reg1, reg2 */
1479 /* sxb reg1 */
1480 int
1481 OP_A0 ()
1482 {
1483 /* start-sanitize-v850e */
1484 if (OP[1] == 0)
1485 {
1486 trace_input ("sxb", OP_REG, 0);
1487
1488 State.regs[ OP[0] ] = EXTEND8 (State.regs[ OP[0] ]);
1489
1490 trace_output (OP_REG);
1491 }
1492 else
1493 /* end-sanitize-v850e */
1494 {
1495 unsigned int op0, op1, result, z, s, cy, ov, sat;
1496
1497 trace_input ("satsub", OP_REG_REG, 0);
1498
1499 /* Compute the result. */
1500 op0 = State.regs[ OP[0] ];
1501 op1 = State.regs[ OP[1] ];
1502 result = op1 - op0;
1503
1504 /* Compute the condition codes. */
1505 z = (result == 0);
1506 s = (result & 0x80000000);
1507 cy = (op1 < op0);
1508 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1509 && (op1 & 0x80000000) != (result & 0x80000000));
1510 sat = ov;
1511
1512 /* Store the result and condition codes. */
1513 State.regs[OP[1]] = result;
1514 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1515 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1516 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1517 | (sat ? PSW_SAT : 0));
1518
1519 /* Handle saturated results. */
1520 if (sat && s)
1521 State.regs[OP[1]] = 0x80000000;
1522 else if (sat)
1523 State.regs[OP[1]] = 0x7fffffff;
1524 trace_output (OP_REG_REG);
1525 }
1526
1527 return 2;
1528 }
1529
1530 /* satsubi sign_extend(imm16), reg */
1531 int
1532 OP_660 ()
1533 {
1534 unsigned int op0, op1, result, z, s, cy, ov, sat;
1535 int temp;
1536
1537 trace_input ("satsubi", OP_IMM_REG, 0);
1538
1539 /* Compute the result. */
1540 temp = EXTEND16 (OP[2]);
1541 op0 = temp;
1542 op1 = State.regs[ OP[0] ];
1543 result = op1 - op0;
1544
1545 /* Compute the condition codes. */
1546 z = (result == 0);
1547 s = (result & 0x80000000);
1548 cy = (op1 < op0);
1549 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1550 && (op1 & 0x80000000) != (result & 0x80000000));
1551 sat = ov;
1552
1553 /* Store the result and condition codes. */
1554 State.regs[OP[1]] = result;
1555 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1556 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1557 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1558 | (sat ? PSW_SAT : 0));
1559
1560 /* Handle saturated results. */
1561 if (sat && s)
1562 State.regs[OP[1]] = 0x80000000;
1563 else if (sat)
1564 State.regs[OP[1]] = 0x7fffffff;
1565 trace_output (OP_IMM_REG);
1566
1567 return 4;
1568 }
1569
1570 /* satsubr reg,reg */
1571 /* zxb reg1 */
1572 int
1573 OP_80 ()
1574 {
1575 /* start-sanitize-v850e */
1576 if (OP[1] == 0)
1577 {
1578 trace_input ("zxb", OP_REG, 0);
1579
1580 State.regs[ OP[0] ] &= 0xff;
1581
1582 trace_output (OP_REG);
1583 }
1584 else
1585 /* end-sanitize-v850e */
1586 {
1587 unsigned int op0, op1, result, z, s, cy, ov, sat;
1588
1589 trace_input ("satsubr", OP_REG_REG, 0);
1590
1591 /* Compute the result. */
1592 op0 = State.regs[ OP[0] ];
1593 op1 = State.regs[ OP[1] ];
1594 result = op0 - op1;
1595
1596 /* Compute the condition codes. */
1597 z = (result == 0);
1598 s = (result & 0x80000000);
1599 cy = (result < op0);
1600 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1601 && (op1 & 0x80000000) != (result & 0x80000000));
1602 sat = ov;
1603
1604 /* Store the result and condition codes. */
1605 State.regs[OP[1]] = result;
1606 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1607 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1608 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1609 | (sat ? PSW_SAT : 0));
1610
1611 /* Handle saturated results. */
1612 if (sat && s)
1613 State.regs[OP[1]] = 0x80000000;
1614 else if (sat)
1615 State.regs[OP[1]] = 0x7fffffff;
1616 trace_output (OP_REG_REG);
1617 }
1618
1619 return 2;
1620 }
1621
1622 /* tst reg,reg */
1623 int
1624 OP_160 ()
1625 {
1626 unsigned int op0, op1, result, z, s;
1627
1628 trace_input ("tst", OP_REG_REG_CMP, 0);
1629
1630 /* Compute the result. */
1631 op0 = State.regs[ OP[0] ];
1632 op1 = State.regs[ OP[1] ];
1633 result = op0 & op1;
1634
1635 /* Compute the condition codes. */
1636 z = (result == 0);
1637 s = (result & 0x80000000);
1638
1639 /* Store the condition codes. */
1640 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1641 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1642 trace_output (OP_REG_REG_CMP);
1643
1644 return 2;
1645 }
1646
1647 /* mov reg, reg */
1648 int
1649 OP_0 ()
1650 {
1651 trace_input ("mov", OP_REG_REG_MOVE, 0);
1652
1653 State.regs[ OP[1] ] = State.regs[ OP[0] ];
1654
1655 trace_output (OP_REG_REG_MOVE);
1656
1657 return 2;
1658 }
1659
1660 /* mov sign_extend(imm5), reg */
1661 /* callt imm6 */
1662 int
1663 OP_200 ()
1664 {
1665 /* start-sanitize-v850e */
1666 if (OP[1] == 0)
1667 {
1668 unsigned long adr;
1669
1670 trace_input ("callt", OP_LOAD16, 1);
1671
1672 CTPC = PC + 2;
1673 CTPSW = PSW;
1674
1675 adr = CTBP + ((OP[3] & 0x3f) << 1);
1676
1677 PC = CTBP + load_mem (adr, 1);
1678
1679 trace_output (OP_LOAD16);
1680
1681 return 0;
1682 }
1683 else
1684 /* end-sanitize-v850e */
1685 {
1686 int value = SEXT5 (OP[0]);
1687
1688 trace_input ("mov", OP_IMM_REG_MOVE, 0);
1689
1690 State.regs[ OP[1] ] = value;
1691
1692 trace_output (OP_IMM_REG_MOVE);
1693
1694 return 2;
1695 }
1696 }
1697
1698 /* mov imm32, reg1 */
1699 /* movea sign_extend(imm16), reg, reg */
1700 int
1701 OP_620 ()
1702 {
1703 /* start-sanitize-v850e */
1704 if (OP[1] == 0)
1705 {
1706 trace_input ("mov", OP_IMM_REG, 4);
1707
1708 State.regs[ OP[0] ] = load_mem (PC + 2, 4);
1709
1710 trace_output (OP_IMM_REG);
1711
1712 return 6;
1713 }
1714 else
1715 /* end-sanitize-v850e */
1716 {
1717 trace_input ("movea", OP_IMM_REG_REG, 0);
1718
1719 State.regs[ OP[1] ] = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
1720
1721 trace_output (OP_IMM_REG_REG);
1722
1723 return 4;
1724 }
1725 }
1726
1727 /* dispose imm5, list12 [, reg1] */
1728 /* movhi imm16, reg, reg */
1729 int
1730 OP_640 ()
1731 {
1732 /* start-sanitize-v850e */
1733
1734 if (OP[1] == 0)
1735 {
1736 int i;
1737
1738 trace_input ("dispose", OP_PUSHPOP1, 0);
1739
1740 SP += (OP[3] & 0x3e) << 1;
1741
1742 /* Load the registers with lower number registers being retrieved from higher addresses. */
1743 for (i = 12; i--;)
1744 if ((OP[3] & (1 << type1_regs[ i ])))
1745 {
1746 State.regs[ 20 + i ] = load_mem (SP, 4);
1747 SP += 4;
1748 }
1749
1750 if ((OP[3] & 0x1f0000) != 0)
1751 {
1752 PC = State.regs[ (OP[3] >> 16) & 0x1f];
1753 return 0;
1754 }
1755
1756 trace_output (OP_PUSHPOP1);
1757 }
1758 else
1759 /* end-sanitize-v850e */
1760 {
1761 trace_input ("movhi", OP_UIMM_REG_REG, 16);
1762
1763 State.regs[ OP[1] ] = State.regs[ OP[0] ] + (OP[2] << 16);
1764
1765 trace_output (OP_UIMM_REG_REG);
1766 }
1767
1768 return 4;
1769 }
1770
1771 /* sar zero_extend(imm5),reg1 */
1772 int
1773 OP_2A0 ()
1774 {
1775 unsigned int op0, op1, result, z, s, cy;
1776
1777 trace_input ("sar", OP_IMM_REG, 0);
1778 op0 = OP[0];
1779 op1 = State.regs[ OP[1] ];
1780 result = (signed)op1 >> op0;
1781
1782 /* Compute the condition codes. */
1783 z = (result == 0);
1784 s = (result & 0x80000000);
1785 cy = (op1 & (1 << (op0 - 1)));
1786
1787 /* Store the result and condition codes. */
1788 State.regs[ OP[1] ] = result;
1789 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1790 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1791 | (cy ? PSW_CY : 0));
1792 trace_output (OP_IMM_REG);
1793
1794 return 2;
1795 }
1796
1797 /* sar reg1, reg2 */
1798 int
1799 OP_A007E0 ()
1800 {
1801 unsigned int op0, op1, result, z, s, cy;
1802
1803 trace_input ("sar", OP_REG_REG, 0);
1804
1805 op0 = State.regs[ OP[0] ] & 0x1f;
1806 op1 = State.regs[ OP[1] ];
1807 result = (signed)op1 >> op0;
1808
1809 /* Compute the condition codes. */
1810 z = (result == 0);
1811 s = (result & 0x80000000);
1812 cy = (op1 & (1 << (op0 - 1)));
1813
1814 /* Store the result and condition codes. */
1815 State.regs[OP[1]] = result;
1816 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1817 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1818 | (cy ? PSW_CY : 0));
1819 trace_output (OP_REG_REG);
1820
1821 return 4;
1822 }
1823
1824 /* shl zero_extend(imm5),reg1 */
1825 int
1826 OP_2C0 ()
1827 {
1828 unsigned int op0, op1, result, z, s, cy;
1829
1830 trace_input ("shl", OP_IMM_REG, 0);
1831 op0 = OP[0];
1832 op1 = State.regs[ OP[1] ];
1833 result = op1 << op0;
1834
1835 /* Compute the condition codes. */
1836 z = (result == 0);
1837 s = (result & 0x80000000);
1838 cy = (op1 & (1 << (32 - op0)));
1839
1840 /* Store the result and condition codes. */
1841 State.regs[OP[1]] = result;
1842 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1843 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1844 | (cy ? PSW_CY : 0));
1845 trace_output (OP_IMM_REG);
1846
1847 return 2;
1848 }
1849
1850 /* shl reg1, reg2 */
1851 int
1852 OP_C007E0 ()
1853 {
1854 unsigned int op0, op1, result, z, s, cy;
1855
1856 trace_input ("shl", OP_REG_REG, 0);
1857 op0 = State.regs[ OP[0] ] & 0x1f;
1858 op1 = State.regs[ OP[1] ];
1859 result = op1 << op0;
1860
1861 /* Compute the condition codes. */
1862 z = (result == 0);
1863 s = (result & 0x80000000);
1864 cy = (op1 & (1 << (32 - op0)));
1865
1866 /* Store the result and condition codes. */
1867 State.regs[OP[1]] = result;
1868 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1869 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1870 | (cy ? PSW_CY : 0));
1871 trace_output (OP_REG_REG);
1872
1873 return 4;
1874 }
1875
1876 /* shr zero_extend(imm5),reg1 */
1877 int
1878 OP_280 ()
1879 {
1880 unsigned int op0, op1, result, z, s, cy;
1881
1882 trace_input ("shr", OP_IMM_REG, 0);
1883 op0 = OP[0];
1884 op1 = State.regs[ OP[1] ];
1885 result = op1 >> op0;
1886
1887 /* Compute the condition codes. */
1888 z = (result == 0);
1889 s = (result & 0x80000000);
1890 cy = (op1 & (1 << (op0 - 1)));
1891
1892 /* Store the result and condition codes. */
1893 State.regs[OP[1]] = result;
1894 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1895 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1896 | (cy ? PSW_CY : 0));
1897 trace_output (OP_IMM_REG);
1898
1899 return 2;
1900 }
1901
1902 /* shr reg1, reg2 */
1903 int
1904 OP_8007E0 ()
1905 {
1906 unsigned int op0, op1, result, z, s, cy;
1907
1908 trace_input ("shr", OP_REG_REG, 0);
1909 op0 = State.regs[ OP[0] ] & 0x1f;
1910 op1 = State.regs[ OP[1] ];
1911 result = op1 >> op0;
1912
1913 /* Compute the condition codes. */
1914 z = (result == 0);
1915 s = (result & 0x80000000);
1916 cy = (op1 & (1 << (op0 - 1)));
1917
1918 /* Store the result and condition codes. */
1919 State.regs[OP[1]] = result;
1920 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1921 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1922 | (cy ? PSW_CY : 0));
1923 trace_output (OP_REG_REG);
1924
1925 return 4;
1926 }
1927
1928 /* or reg, reg */
1929 int
1930 OP_100 ()
1931 {
1932 unsigned int op0, op1, result, z, s;
1933
1934 trace_input ("or", OP_REG_REG, 0);
1935
1936 /* Compute the result. */
1937 op0 = State.regs[ OP[0] ];
1938 op1 = State.regs[ OP[1] ];
1939 result = op0 | op1;
1940
1941 /* Compute the condition codes. */
1942 z = (result == 0);
1943 s = (result & 0x80000000);
1944
1945 /* Store the result and condition codes. */
1946 State.regs[OP[1]] = result;
1947 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1948 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1949 trace_output (OP_REG_REG);
1950
1951 return 2;
1952 }
1953
1954 /* ori zero_extend(imm16), reg, reg */
1955 int
1956 OP_680 ()
1957 {
1958 unsigned int op0, op1, result, z, s;
1959
1960 trace_input ("ori", OP_UIMM_REG_REG, 0);
1961 op0 = OP[2];
1962 op1 = State.regs[ OP[0] ];
1963 result = op0 | op1;
1964
1965 /* Compute the condition codes. */
1966 z = (result == 0);
1967 s = (result & 0x80000000);
1968
1969 /* Store the result and condition codes. */
1970 State.regs[OP[1]] = result;
1971 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1972 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1973 trace_output (OP_UIMM_REG_REG);
1974
1975 return 4;
1976 }
1977
1978 /* and reg, reg */
1979 int
1980 OP_140 ()
1981 {
1982 unsigned int op0, op1, result, z, s;
1983
1984 trace_input ("and", OP_REG_REG, 0);
1985
1986 /* Compute the result. */
1987 op0 = State.regs[ OP[0] ];
1988 op1 = State.regs[ OP[1] ];
1989 result = op0 & op1;
1990
1991 /* Compute the condition codes. */
1992 z = (result == 0);
1993 s = (result & 0x80000000);
1994
1995 /* Store the result and condition codes. */
1996 State.regs[OP[1]] = result;
1997 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1998 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1999 trace_output (OP_REG_REG);
2000
2001 return 2;
2002 }
2003
2004 /* andi zero_extend(imm16), reg, reg */
2005 int
2006 OP_6C0 ()
2007 {
2008 unsigned int result, z;
2009
2010 trace_input ("andi", OP_UIMM_REG_REG, 0);
2011
2012 result = OP[2] & State.regs[ OP[0] ];
2013
2014 /* Compute the condition codes. */
2015 z = (result == 0);
2016
2017 /* Store the result and condition codes. */
2018 State.regs[ OP[1] ] = result;
2019
2020 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2021 PSW |= (z ? PSW_Z : 0);
2022
2023 trace_output (OP_UIMM_REG_REG);
2024
2025 return 4;
2026 }
2027
2028 /* xor reg, reg */
2029 int
2030 OP_120 ()
2031 {
2032 unsigned int op0, op1, result, z, s;
2033
2034 trace_input ("xor", OP_REG_REG, 0);
2035
2036 /* Compute the result. */
2037 op0 = State.regs[ OP[0] ];
2038 op1 = State.regs[ OP[1] ];
2039 result = op0 ^ op1;
2040
2041 /* Compute the condition codes. */
2042 z = (result == 0);
2043 s = (result & 0x80000000);
2044
2045 /* Store the result and condition codes. */
2046 State.regs[OP[1]] = result;
2047 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2048 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
2049 trace_output (OP_REG_REG);
2050
2051 return 2;
2052 }
2053
2054 /* xori zero_extend(imm16), reg, reg */
2055 int
2056 OP_6A0 ()
2057 {
2058 unsigned int op0, op1, result, z, s;
2059
2060 trace_input ("xori", OP_UIMM_REG_REG, 0);
2061 op0 = OP[2];
2062 op1 = State.regs[ OP[0] ];
2063 result = op0 ^ op1;
2064
2065 /* Compute the condition codes. */
2066 z = (result == 0);
2067 s = (result & 0x80000000);
2068
2069 /* Store the result and condition codes. */
2070 State.regs[OP[1]] = result;
2071 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2072 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
2073 trace_output (OP_UIMM_REG_REG);
2074
2075 return 4;
2076 }
2077
2078 /* not reg1, reg2 */
2079 int
2080 OP_20 ()
2081 {
2082 unsigned int op0, result, z, s;
2083
2084 trace_input ("not", OP_REG_REG_MOVE, 0);
2085 /* Compute the result. */
2086 op0 = State.regs[ OP[0] ];
2087 result = ~op0;
2088
2089 /* Compute the condition codes. */
2090 z = (result == 0);
2091 s = (result & 0x80000000);
2092
2093 /* Store the result and condition codes. */
2094 State.regs[OP[1]] = result;
2095 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2096 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
2097 trace_output (OP_REG_REG_MOVE);
2098
2099 return 2;
2100 }
2101
2102 /* set1 */
2103 int
2104 OP_7C0 ()
2105 {
2106 unsigned int op0, op1, op2;
2107 int temp;
2108
2109 trace_input ("set1", OP_BIT, 0);
2110 op0 = State.regs[ OP[0] ];
2111 op1 = OP[1] & 0x7;
2112 temp = EXTEND16 (OP[2]);
2113 op2 = temp;
2114 temp = load_mem (op0 + op2, 1);
2115 PSW &= ~PSW_Z;
2116 if ((temp & (1 << op1)) == 0)
2117 PSW |= PSW_Z;
2118 temp |= (1 << op1);
2119 store_mem (op0 + op2, 1, temp);
2120 trace_output (OP_BIT);
2121
2122 return 4;
2123 }
2124
2125 /* not1 */
2126 int
2127 OP_47C0 ()
2128 {
2129 unsigned int op0, op1, op2;
2130 int temp;
2131
2132 trace_input ("not1", OP_BIT, 0);
2133 op0 = State.regs[ OP[0] ];
2134 op1 = OP[1] & 0x7;
2135 temp = EXTEND16 (OP[2]);
2136 op2 = temp;
2137 temp = load_mem (op0 + op2, 1);
2138 PSW &= ~PSW_Z;
2139 if ((temp & (1 << op1)) == 0)
2140 PSW |= PSW_Z;
2141 temp ^= (1 << op1);
2142 store_mem (op0 + op2, 1, temp);
2143 trace_output (OP_BIT);
2144
2145 return 4;
2146 }
2147
2148 /* clr1 */
2149 int
2150 OP_87C0 ()
2151 {
2152 unsigned int op0, op1, op2;
2153 int temp;
2154
2155 trace_input ("clr1", OP_BIT, 0);
2156 op0 = State.regs[ OP[0] ];
2157 op1 = OP[1] & 0x7;
2158 temp = EXTEND16 (OP[2]);
2159 op2 = temp;
2160 temp = load_mem (op0 + op2, 1);
2161 PSW &= ~PSW_Z;
2162 if ((temp & (1 << op1)) == 0)
2163 PSW |= PSW_Z;
2164 temp &= ~(1 << op1);
2165 store_mem (op0 + op2, 1, temp);
2166 trace_output (OP_BIT);
2167
2168 return 4;
2169 }
2170
2171 /* tst1 */
2172 int
2173 OP_C7C0 ()
2174 {
2175 unsigned int op0, op1, op2;
2176 int temp;
2177
2178 trace_input ("tst1", OP_BIT, 0);
2179 op0 = State.regs[ OP[0] ];
2180 op1 = OP[1] & 0x7;
2181 temp = EXTEND16 (OP[2]);
2182 op2 = temp;
2183 temp = load_mem (op0 + op2, 1);
2184 PSW &= ~PSW_Z;
2185 if ((temp & (1 << op1)) == 0)
2186 PSW |= PSW_Z;
2187 trace_output (OP_BIT);
2188
2189 return 4;
2190 }
2191
2192 /* breakpoint */
2193 int
2194 OP_FFFF ()
2195 {
2196 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
2197 sim_stopped, SIGTRAP);
2198 return 0;
2199 }
2200
2201 /* di */
2202 int
2203 OP_16007E0 ()
2204 {
2205 trace_input ("di", OP_NONE, 0);
2206 PSW |= PSW_ID;
2207 trace_output (OP_NONE);
2208
2209 return 4;
2210 }
2211
2212 /* ei */
2213 int
2214 OP_16087E0 ()
2215 {
2216 trace_input ("ei", OP_NONE, 0);
2217 PSW &= ~PSW_ID;
2218 trace_output (OP_NONE);
2219
2220 return 4;
2221 }
2222
2223 /* halt */
2224 int
2225 OP_12007E0 ()
2226 {
2227 trace_input ("halt", OP_NONE, 0);
2228 /* FIXME this should put processor into a mode where NMI still handled */
2229 trace_output (OP_NONE);
2230 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
2231 sim_stopped, SIGTRAP);
2232 return 0;
2233 }
2234
2235 /* reti */
2236 int
2237 OP_14007E0 ()
2238 {
2239 trace_input ("reti", OP_NONE, 0);
2240 trace_output (OP_NONE);
2241
2242 /* Restore for NMI if only NP on, otherwise is interrupt or exception. */
2243 if ((PSW & (PSW_NP | PSW_EP)) == PSW_NP)
2244 {
2245 PC = FEPC - 4;
2246 PSW = FEPSW;
2247 }
2248 else
2249 {
2250 PC = EIPC - 4;
2251 PSW = EIPSW;
2252 }
2253
2254 return 0;
2255 }
2256
2257 /* trap */
2258 int
2259 OP_10007E0 ()
2260 {
2261 trace_input ("trap", OP_TRAP, 0);
2262 trace_output (OP_TRAP);
2263
2264 /* Trap 31 is used for simulating OS I/O functions */
2265
2266 if (OP[0] == 31)
2267 {
2268 int save_errno = errno;
2269 errno = 0;
2270
2271 /* Registers passed to trap 0 */
2272
2273 #define FUNC State.regs[6] /* function number, return value */
2274 #define PARM1 State.regs[7] /* optional parm 1 */
2275 #define PARM2 State.regs[8] /* optional parm 2 */
2276 #define PARM3 State.regs[9] /* optional parm 3 */
2277
2278 /* Registers set by trap 0 */
2279
2280 #define RETVAL State.regs[10] /* return value */
2281 #define RETERR State.regs[11] /* return error code */
2282
2283 /* Turn a pointer in a register into a pointer into real memory. */
2284
2285 #define MEMPTR(x) (map (x))
2286
2287 switch (FUNC)
2288 {
2289
2290 #ifdef HAVE_FORK
2291 #ifdef SYS_fork
2292 case SYS_fork:
2293 RETVAL = fork ();
2294 break;
2295 #endif
2296 #endif
2297
2298 #ifdef HAVE_EXECVE
2299 #ifdef SYS_execv
2300 case SYS_execve:
2301 {
2302 char *path = fetch_str (simulator, PARM1);
2303 char **argv = fetch_argv (simulator, PARM2);
2304 char **envp = fetch_argv (simulator, PARM3);
2305 RETVAL = execve (path, argv, envp);
2306 zfree (path);
2307 freeargv (argv);
2308 freeargv (envp);
2309 break;
2310 }
2311 #endif
2312 #endif
2313
2314 #if HAVE_EXECV
2315 #ifdef SYS_execv
2316 case SYS_execv:
2317 {
2318 char *path = fetch_str (simulator, PARM1);
2319 char **argv = fetch_argv (simulator, PARM2);
2320 RETVAL = execv (path, argv);
2321 zfree (path);
2322 freeargv (argv);
2323 break;
2324 }
2325 #endif
2326 #endif
2327
2328 #if 0
2329 #ifdef SYS_pipe
2330 case SYS_pipe:
2331 {
2332 reg_t buf;
2333 int host_fd[2];
2334
2335 buf = PARM1;
2336 RETVAL = pipe (host_fd);
2337 SW (buf, host_fd[0]);
2338 buf += sizeof(uint16);
2339 SW (buf, host_fd[1]);
2340 }
2341 break;
2342 #endif
2343 #endif
2344
2345 #if 0
2346 #ifdef SYS_wait
2347 case SYS_wait:
2348 {
2349 int status;
2350
2351 RETVAL = wait (&status);
2352 SW (PARM1, status);
2353 }
2354 break;
2355 #endif
2356 #endif
2357
2358 #ifdef SYS_read
2359 case SYS_read:
2360 {
2361 char *buf = zalloc (PARM3);
2362 RETVAL = sim_io_read (simulator, PARM1, buf, PARM3);
2363 sim_write (simulator, PARM2, buf, PARM3);
2364 zfree (buf);
2365 break;
2366 }
2367 #endif
2368
2369 #ifdef SYS_write
2370 case SYS_write:
2371 {
2372 char *buf = zalloc (PARM3);
2373 sim_read (simulator, PARM2, buf, PARM3);
2374 if (PARM1 == 1)
2375 RETVAL = sim_io_write_stdout (simulator, buf, PARM3);
2376 else
2377 RETVAL = sim_io_write (simulator, PARM1, buf, PARM3);
2378 zfree (buf);
2379 break;
2380 }
2381 #endif
2382
2383 #ifdef SYS_lseek
2384 case SYS_lseek:
2385 RETVAL = sim_io_lseek (simulator, PARM1, PARM2, PARM3);
2386 break;
2387 #endif
2388
2389 #ifdef SYS_close
2390 case SYS_close:
2391 RETVAL = sim_io_close (simulator, PARM1);
2392 break;
2393 #endif
2394
2395 #ifdef SYS_open
2396 case SYS_open:
2397 {
2398 char *buf = fetch_str (simulator, PARM1);
2399 RETVAL = sim_io_open (simulator, buf, PARM2);
2400 zfree (buf);
2401 break;
2402 }
2403 #endif
2404
2405 #ifdef SYS_exit
2406 case SYS_exit:
2407 if ((PARM1 & 0xffff0000) == 0xdead0000 && (PARM1 & 0xffff) != 0)
2408 /* get signal encoded by kill */
2409 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
2410 sim_signalled, PARM1 & 0xffff);
2411 else if (PARM1 == 0xdead)
2412 /* old libraries */
2413 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
2414 sim_exited, SIGABRT);
2415 else
2416 /* PARM1 has exit status */
2417 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
2418 sim_exited, PARM1);
2419 break;
2420 #endif
2421
2422 #if !defined(__GO32__) && !defined(_WIN32)
2423 #ifdef SYS_stat
2424 case SYS_stat: /* added at hmsi */
2425 /* stat system call */
2426 {
2427 struct stat host_stat;
2428 reg_t buf;
2429 char *path = fetch_str (simulator, PARM1);
2430
2431 RETVAL = stat (path, &host_stat);
2432
2433 zfree (path);
2434 buf = PARM2;
2435
2436 /* Just wild-assed guesses. */
2437 store_mem (buf, 2, host_stat.st_dev);
2438 store_mem (buf + 2, 2, host_stat.st_ino);
2439 store_mem (buf + 4, 4, host_stat.st_mode);
2440 store_mem (buf + 8, 2, host_stat.st_nlink);
2441 store_mem (buf + 10, 2, host_stat.st_uid);
2442 store_mem (buf + 12, 2, host_stat.st_gid);
2443 store_mem (buf + 14, 2, host_stat.st_rdev);
2444 store_mem (buf + 16, 4, host_stat.st_size);
2445 store_mem (buf + 20, 4, host_stat.st_atime);
2446 store_mem (buf + 28, 4, host_stat.st_mtime);
2447 store_mem (buf + 36, 4, host_stat.st_ctime);
2448 }
2449 break;
2450 #endif
2451 #endif
2452
2453 #ifdef HAVE_CHOWN
2454 #ifdef SYS_chown
2455 case SYS_chown:
2456 {
2457 char *path = fetch_str (simulator, PARM1);
2458 RETVAL = chown (path, PARM2, PARM3);
2459 zfree (path);
2460 }
2461 break;
2462 #endif
2463 #endif
2464
2465 #if HAVE_CHMOD
2466 #ifdef SYS_chmod
2467 case SYS_chmod:
2468 {
2469 char *path = fetch_str (simulator, PARM1);
2470 RETVAL = chmod (path, PARM2);
2471 zfree (path);
2472 }
2473 break;
2474 #endif
2475 #endif
2476
2477 #ifdef SYS_time
2478 #if HAVE_TIME
2479 case SYS_time:
2480 {
2481 time_t now;
2482 RETVAL = time (&now);
2483 store_mem (PARM1, 4, now);
2484 }
2485 break;
2486 #endif
2487 #endif
2488
2489 #if !defined(__GO32__) && !defined(_WIN32)
2490 #ifdef SYS_times
2491 case SYS_times:
2492 {
2493 struct tms tms;
2494 RETVAL = times (&tms);
2495 store_mem (PARM1, 4, tms.tms_utime);
2496 store_mem (PARM1 + 4, 4, tms.tms_stime);
2497 store_mem (PARM1 + 8, 4, tms.tms_cutime);
2498 store_mem (PARM1 + 12, 4, tms.tms_cstime);
2499 break;
2500 }
2501 #endif
2502 #endif
2503
2504 #ifdef SYS_gettimeofday
2505 #if !defined(__GO32__) && !defined(_WIN32)
2506 case SYS_gettimeofday:
2507 {
2508 struct timeval t;
2509 struct timezone tz;
2510 RETVAL = gettimeofday (&t, &tz);
2511 store_mem (PARM1, 4, t.tv_sec);
2512 store_mem (PARM1 + 4, 4, t.tv_usec);
2513 store_mem (PARM2, 4, tz.tz_minuteswest);
2514 store_mem (PARM2 + 4, 4, tz.tz_dsttime);
2515 break;
2516 }
2517 #endif
2518 #endif
2519
2520 #ifdef SYS_utime
2521 #if HAVE_UTIME
2522 case SYS_utime:
2523 {
2524 /* Cast the second argument to void *, to avoid type mismatch
2525 if a prototype is present. */
2526 sim_io_error (simulator, "Utime not supported");
2527 /* RETVAL = utime (path, (void *) MEMPTR (PARM2)); */
2528 }
2529 break;
2530 #endif
2531 #endif
2532
2533 default:
2534 abort ();
2535 }
2536 RETERR = errno;
2537 errno = save_errno;
2538
2539 return 4;
2540 }
2541 else
2542 { /* Trap 0 -> 30 */
2543 EIPC = PC + 4;
2544 EIPSW = PSW;
2545 /* Mask out EICC */
2546 ECR &= 0xffff0000;
2547 ECR |= 0x40 + OP[0];
2548 /* Flag that we are now doing exception processing. */
2549 PSW |= PSW_EP | PSW_ID;
2550 PC = ((OP[0] < 0x10) ? 0x40 : 0x50) - 4;
2551
2552 return 0;
2553 }
2554 }
2555
2556 /* ldsr, reg,reg */
2557 int
2558 OP_2007E0 ()
2559 {
2560 trace_input ("ldsr", OP_LDSR, 0);
2561
2562 State.sregs[ OP[1] ] = State.regs[ OP[0] ];
2563
2564 trace_output (OP_LDSR);
2565
2566 return 4;
2567 }
2568
2569 /* stsr */
2570 int
2571 OP_4007E0 ()
2572 {
2573 trace_input ("stsr", OP_STSR, 0);
2574
2575 State.regs[ OP[1] ] = State.sregs[ OP[0] ];
2576
2577 trace_output (OP_STSR);
2578
2579 return 4;
2580 }
2581
2582 /* tst1 reg2, [reg1] */
2583 int
2584 OP_E607E0 (void)
2585 {
2586 int temp;
2587
2588 trace_input ("tst1", OP_BIT, 1);
2589
2590 temp = load_mem (State.regs[ OP[0] ], 1);
2591
2592 PSW &= ~PSW_Z;
2593 if ((temp & (1 << State.regs[ OP[1] & 0x7 ])) == 0)
2594 PSW |= PSW_Z;
2595
2596 trace_output (OP_BIT);
2597
2598 return 4;
2599 }
2600
2601 /* mulu reg1, reg2, reg3 */
2602 int
2603 OP_22207E0 (void)
2604 {
2605 trace_input ("mulu", OP_REG_REG_REG, 0);
2606
2607 Multiply64 (false, State.regs[ OP[0] ]);
2608
2609 trace_output (OP_REG_REG_REG);
2610
2611 return 4;
2612 }
2613
2614 /* start-sanitize-v850e */
2615
2616 #define BIT_CHANGE_OP( name, binop ) \
2617 unsigned int bit; \
2618 unsigned int temp; \
2619 \
2620 trace_input (name, OP_BIT_CHANGE, 0); \
2621 \
2622 bit = 1 << State.regs[ OP[1] & 0x7 ]; \
2623 temp = load_mem (State.regs[ OP[0] ], 1); \
2624 \
2625 PSW &= ~PSW_Z; \
2626 if ((temp & bit) == 0) \
2627 PSW |= PSW_Z; \
2628 temp binop bit; \
2629 \
2630 store_mem (State.regs[ OP[0] ], 1, temp); \
2631 \
2632 trace_output (OP_BIT_CHANGE); \
2633 \
2634 return 4;
2635
2636 /* clr1 reg2, [reg1] */
2637 int
2638 OP_E407E0 (void)
2639 {
2640 BIT_CHANGE_OP ("clr1", &= ~ );
2641 }
2642
2643 /* not1 reg2, [reg1] */
2644 int
2645 OP_E207E0 (void)
2646 {
2647 BIT_CHANGE_OP ("not1", ^= );
2648 }
2649
2650 /* set1 */
2651 int
2652 OP_E007E0 (void)
2653 {
2654 BIT_CHANGE_OP ("set1", |= );
2655 }
2656
2657 /* sasf */
2658 int
2659 OP_20007E0 (void)
2660 {
2661 trace_input ("sasf", OP_EX1, 0);
2662
2663 State.regs[ OP[1] ] = (State.regs[ OP[1] ] << 1) | condition_met (OP[0]);
2664
2665 trace_output (OP_EX1);
2666
2667 return 4;
2668 }
2669 /* end-sanitize-v850e */
2670
2671 /* start-sanitize-v850eq */
2672 /* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
2673 static void
2674 divun
2675 (
2676 unsigned int N,
2677 unsigned long int als,
2678 unsigned long int sfi,
2679 unsigned long int * quotient_ptr,
2680 unsigned long int * remainder_ptr,
2681 boolean * overflow_ptr
2682 )
2683 {
2684 unsigned long ald = sfi >> (N - 1);
2685 unsigned long alo = als;
2686 unsigned int Q = 1;
2687 unsigned int C;
2688 unsigned int S = 0;
2689 unsigned int i;
2690 unsigned int R1 = 1;
2691 unsigned int DBZ = (als == 0) ? 1 : 0;
2692 unsigned long alt = Q ? ~als : als;
2693
2694 /* 1st Loop */
2695 alo = ald + alt + Q;
2696 C = (((alt >> 31) & (ald >> 31))
2697 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2698 C = C ^ Q;
2699 Q = ~(C ^ S) & 1;
2700 R1 = (alo == 0) ? 0 : (R1 & Q);
2701 if ((S ^ (alo>>31)) && !C)
2702 {
2703 DBZ = 1;
2704 }
2705 S = alo >> 31;
2706 sfi = (sfi << (32-N+1)) | Q;
2707 ald = (alo << 1) | (sfi >> 31);
2708
2709 /* 2nd - N-1th Loop */
2710 for (i = 2; i < N; i++)
2711 {
2712 alt = Q ? ~als : als;
2713 alo = ald + alt + Q;
2714 C = (((alt >> 31) & (ald >> 31))
2715 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2716 C = C ^ Q;
2717 Q = ~(C ^ S) & 1;
2718 R1 = (alo == 0) ? 0 : (R1 & Q);
2719 if ((S ^ (alo>>31)) && !C && !DBZ)
2720 {
2721 DBZ = 1;
2722 }
2723 S = alo >> 31;
2724 sfi = (sfi << 1) | Q;
2725 ald = (alo << 1) | (sfi >> 31);
2726 }
2727
2728 /* Nth Loop */
2729 alt = Q ? ~als : als;
2730 alo = ald + alt + Q;
2731 C = (((alt >> 31) & (ald >> 31))
2732 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2733 C = C ^ Q;
2734 Q = ~(C ^ S) & 1;
2735 R1 = (alo == 0) ? 0 : (R1 & Q);
2736 if ((S ^ (alo>>31)) && !C)
2737 {
2738 DBZ = 1;
2739 }
2740
2741 * quotient_ptr = (sfi << 1) | Q;
2742 * remainder_ptr = Q ? alo : (alo + als);
2743 * overflow_ptr = DBZ | R1;
2744 }
2745
2746 /* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
2747 static void
2748 divn
2749 (
2750 unsigned int N,
2751 unsigned long int als,
2752 unsigned long int sfi,
2753 signed long int * quotient_ptr,
2754 signed long int * remainder_ptr,
2755 boolean * overflow_ptr
2756 )
2757 {
2758 unsigned long ald = (signed long) sfi >> (N - 1);
2759 unsigned long alo = als;
2760 unsigned int SS = als >> 31;
2761 unsigned int SD = sfi >> 31;
2762 unsigned int R1 = 1;
2763 unsigned int OV;
2764 unsigned int DBZ = als == 0 ? 1 : 0;
2765 unsigned int Q = ~(SS ^ SD) & 1;
2766 unsigned int C;
2767 unsigned int S;
2768 unsigned int i;
2769 unsigned long alt = Q ? ~als : als;
2770
2771
2772 /* 1st Loop */
2773
2774 alo = ald + alt + Q;
2775 C = (((alt >> 31) & (ald >> 31))
2776 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2777 Q = C ^ SS;
2778 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2779 S = alo >> 31;
2780 sfi = (sfi << (32-N+1)) | Q;
2781 ald = (alo << 1) | (sfi >> 31);
2782 if ((alo >> 31) ^ (ald >> 31))
2783 {
2784 DBZ = 1;
2785 }
2786
2787 /* 2nd - N-1th Loop */
2788
2789 for (i = 2; i < N; i++)
2790 {
2791 alt = Q ? ~als : als;
2792 alo = ald + alt + Q;
2793 C = (((alt >> 31) & (ald >> 31))
2794 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2795 Q = C ^ SS;
2796 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2797 S = alo >> 31;
2798 sfi = (sfi << 1) | Q;
2799 ald = (alo << 1) | (sfi >> 31);
2800 if ((alo >> 31) ^ (ald >> 31))
2801 {
2802 DBZ = 1;
2803 }
2804 }
2805
2806 /* Nth Loop */
2807 alt = Q ? ~als : als;
2808 alo = ald + alt + Q;
2809 C = (((alt >> 31) & (ald >> 31))
2810 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2811 Q = C ^ SS;
2812 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2813 sfi = (sfi << (32-N+1));
2814 ald = alo;
2815
2816 /* End */
2817 if (alo != 0)
2818 {
2819 alt = Q ? ~als : als;
2820 alo = ald + alt + Q;
2821 }
2822 R1 = R1 & ((~alo >> 31) ^ SD);
2823 if ((alo != 0) && ((Q ^ (SS ^ SD)) ^ R1)) alo = ald;
2824 if (N != 32)
2825 ald = sfi = (long) ((sfi >> 1) | (SS ^ SD) << 31) >> (32-N-1) | Q;
2826 else
2827 ald = sfi = sfi | Q;
2828
2829 OV = DBZ | ((alo == 0) ? 0 : R1);
2830
2831 * remainder_ptr = alo;
2832
2833 /* Adj */
2834 if (((alo != 0) && ((SS ^ SD) ^ R1))
2835 || ((alo == 0) && (SS ^ R1)))
2836 alo = ald + 1;
2837 else
2838 alo = ald;
2839
2840 OV = (DBZ | R1) ? OV : ((alo >> 31) & (~ald >> 31));
2841
2842 * quotient_ptr = alo;
2843 * overflow_ptr = OV;
2844 }
2845
2846 /* sdivun imm5, reg1, reg2, reg3 */
2847 int
2848 OP_1C207E0 (void)
2849 {
2850 unsigned long int quotient;
2851 unsigned long int remainder;
2852 unsigned long int divide_by;
2853 unsigned long int divide_this;
2854 boolean overflow = false;
2855 unsigned int imm5;
2856
2857 trace_input ("sdivun", OP_IMM_REG_REG_REG, 0);
2858
2859 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2860
2861 divide_by = State.regs[ OP[0] ];
2862 divide_this = State.regs[ OP[1] ] << imm5;
2863
2864 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2865
2866 State.regs[ OP[1] ] = quotient;
2867 State.regs[ OP[2] >> 11 ] = remainder;
2868
2869 /* Set condition codes. */
2870 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2871
2872 if (overflow) PSW |= PSW_OV;
2873 if (quotient == 0) PSW |= PSW_Z;
2874 if (quotient & 0x80000000) PSW |= PSW_S;
2875
2876 trace_output (OP_IMM_REG_REG_REG);
2877
2878 return 4;
2879 }
2880
2881 /* sdivn imm5, reg1, reg2, reg3 */
2882 int
2883 OP_1C007E0 (void)
2884 {
2885 signed long int quotient;
2886 signed long int remainder;
2887 signed long int divide_by;
2888 signed long int divide_this;
2889 boolean overflow = false;
2890 unsigned int imm5;
2891
2892 trace_input ("sdivn", OP_IMM_REG_REG_REG, 0);
2893
2894 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2895
2896 divide_by = State.regs[ OP[0] ];
2897 divide_this = State.regs[ OP[1] ] << imm5;
2898
2899 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2900
2901 State.regs[ OP[1] ] = quotient;
2902 State.regs[ OP[2] >> 11 ] = remainder;
2903
2904 /* Set condition codes. */
2905 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2906
2907 if (overflow) PSW |= PSW_OV;
2908 if (quotient == 0) PSW |= PSW_Z;
2909 if (quotient < 0) PSW |= PSW_S;
2910
2911 trace_output (OP_IMM_REG_REG_REG);
2912
2913 return 4;
2914 }
2915
2916 /* sdivhun imm5, reg1, reg2, reg3 */
2917 int
2918 OP_18207E0 (void)
2919 {
2920 unsigned long int quotient;
2921 unsigned long int remainder;
2922 unsigned long int divide_by;
2923 unsigned long int divide_this;
2924 boolean overflow = false;
2925 unsigned int imm5;
2926
2927 trace_input ("sdivhun", OP_IMM_REG_REG_REG, 0);
2928
2929 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2930
2931 divide_by = State.regs[ OP[0] ] & 0xffff;
2932 divide_this = State.regs[ OP[1] ] << imm5;
2933
2934 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2935
2936 State.regs[ OP[1] ] = quotient;
2937 State.regs[ OP[2] >> 11 ] = remainder;
2938
2939 /* Set condition codes. */
2940 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2941
2942 if (overflow) PSW |= PSW_OV;
2943 if (quotient == 0) PSW |= PSW_Z;
2944 if (quotient & 0x80000000) PSW |= PSW_S;
2945
2946 trace_output (OP_IMM_REG_REG_REG);
2947
2948 return 4;
2949 }
2950
2951 /* sdivhn imm5, reg1, reg2, reg3 */
2952 int
2953 OP_18007E0 (void)
2954 {
2955 signed long int quotient;
2956 signed long int remainder;
2957 signed long int divide_by;
2958 signed long int divide_this;
2959 boolean overflow = false;
2960 unsigned int imm5;
2961
2962 trace_input ("sdivhn", OP_IMM_REG_REG_REG, 0);
2963
2964 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2965
2966 divide_by = EXTEND16 (State.regs[ OP[0] ]);
2967 divide_this = State.regs[ OP[1] ] << imm5;
2968
2969 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2970
2971 State.regs[ OP[1] ] = quotient;
2972 State.regs[ OP[2] >> 11 ] = remainder;
2973
2974 /* Set condition codes. */
2975 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2976
2977 if (overflow) PSW |= PSW_OV;
2978 if (quotient == 0) PSW |= PSW_Z;
2979 if (quotient < 0) PSW |= PSW_S;
2980
2981 trace_output (OP_IMM_REG_REG_REG);
2982
2983 return 4;
2984 }
2985 /* end-sanitize-v850eq */
2986
2987 /* start-sanitize-v850e */
2988 /* divu reg1, reg2, reg3 */
2989 int
2990 OP_2C207E0 (void)
2991 {
2992 unsigned long int quotient;
2993 unsigned long int remainder;
2994 unsigned long int divide_by;
2995 unsigned long int divide_this;
2996 boolean overflow = false;
2997
2998 if ((OP[3] & 0x3c0000) == 0)
2999 {
3000 trace_input ("divu", OP_REG_REG_REG, 0);
3001
3002 /* Compute the result. */
3003
3004 divide_by = State.regs[ OP[0] ];
3005 divide_this = State.regs[ OP[1] ];
3006
3007 if (divide_by == 0)
3008 {
3009 overflow = true;
3010 divide_by = 1;
3011 }
3012
3013 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
3014 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
3015
3016 /* Set condition codes. */
3017 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3018
3019 if (overflow) PSW |= PSW_OV;
3020 if (quotient == 0) PSW |= PSW_Z;
3021 if (quotient & 0x80000000) PSW |= PSW_S;
3022
3023 trace_output (OP_REG_REG_REG);
3024 }
3025 /* start-sanitize-v850eq */
3026 /* divun imm5, reg1, reg2, reg3 */
3027 else
3028 {
3029 unsigned int imm5;
3030
3031 trace_input ("divun", OP_IMM_REG_REG_REG, 0);
3032
3033 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
3034
3035 divide_by = State.regs[ OP[0] ];
3036 divide_this = State.regs[ OP[1] ];
3037
3038 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
3039
3040 State.regs[ OP[1] ] = quotient;
3041 State.regs[ OP[2] >> 11 ] = remainder;
3042
3043 /* Set condition codes. */
3044 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3045
3046 if (overflow) PSW |= PSW_OV;
3047 if (quotient == 0) PSW |= PSW_Z;
3048 if (quotient & 0x80000000) PSW |= PSW_S;
3049
3050 trace_output (OP_IMM_REG_REG_REG);
3051 }
3052 /* end-sanitize-v850eq */
3053
3054 return 4;
3055 }
3056
3057 /* div reg1, reg2, reg3 */
3058 int
3059 OP_2C007E0 (void)
3060 {
3061 signed long int quotient;
3062 signed long int remainder;
3063 signed long int divide_by;
3064 signed long int divide_this;
3065 boolean overflow = false;
3066
3067 if ((OP[3] & 0x3c0000) == 0)
3068 {
3069 trace_input ("div", OP_REG_REG_REG, 0);
3070
3071 /* Compute the result. */
3072
3073 divide_by = State.regs[ OP[0] ];
3074 divide_this = State.regs[ OP[1] ];
3075
3076 if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
3077 {
3078 overflow = true;
3079 divide_by = 1;
3080 }
3081
3082 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
3083 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
3084
3085 /* Set condition codes. */
3086 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3087
3088 if (overflow) PSW |= PSW_OV;
3089 if (quotient == 0) PSW |= PSW_Z;
3090 if (quotient < 0) PSW |= PSW_S;
3091
3092 trace_output (OP_REG_REG_REG);
3093 }
3094 /* start-sanitize-v850eq */
3095 /* divn imm5, reg1, reg2, reg3 */
3096 else
3097 {
3098 unsigned int imm5;
3099
3100 trace_input ("divn", OP_IMM_REG_REG_REG, 0);
3101
3102 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
3103
3104 divide_by = State.regs[ OP[0] ];
3105 divide_this = State.regs[ OP[1] ];
3106
3107 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
3108
3109 State.regs[ OP[1] ] = quotient;
3110 State.regs[ OP[2] >> 11 ] = remainder;
3111
3112 /* Set condition codes. */
3113 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3114
3115 if (overflow) PSW |= PSW_OV;
3116 if (quotient == 0) PSW |= PSW_Z;
3117 if (quotient < 0) PSW |= PSW_S;
3118
3119 trace_output (OP_IMM_REG_REG_REG);
3120 }
3121 /* end-sanitize-v850eq */
3122
3123 return 4;
3124 }
3125
3126 /* divhu reg1, reg2, reg3 */
3127 int
3128 OP_28207E0 (void)
3129 {
3130 unsigned long int quotient;
3131 unsigned long int remainder;
3132 unsigned long int divide_by;
3133 unsigned long int divide_this;
3134 boolean overflow = false;
3135
3136 if ((OP[3] & 0x3c0000) == 0)
3137 {
3138 trace_input ("divhu", OP_REG_REG_REG, 0);
3139
3140 /* Compute the result. */
3141
3142 divide_by = State.regs[ OP[0] ] & 0xffff;
3143 divide_this = State.regs[ OP[1] ];
3144
3145 if (divide_by == 0)
3146 {
3147 overflow = true;
3148 divide_by = 1;
3149 }
3150
3151 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
3152 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
3153
3154 /* Set condition codes. */
3155 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3156
3157 if (overflow) PSW |= PSW_OV;
3158 if (quotient == 0) PSW |= PSW_Z;
3159 if (quotient & 0x80000000) PSW |= PSW_S;
3160
3161 trace_output (OP_REG_REG_REG);
3162 }
3163 /* start-sanitize-v850eq */
3164 /* divhun imm5, reg1, reg2, reg3 */
3165 else
3166 {
3167 unsigned int imm5;
3168
3169 trace_input ("divhun", OP_IMM_REG_REG_REG, 0);
3170
3171 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
3172
3173 divide_by = State.regs[ OP[0] ] & 0xffff;
3174 divide_this = State.regs[ OP[1] ];
3175
3176 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
3177
3178 State.regs[ OP[1] ] = quotient;
3179 State.regs[ OP[2] >> 11 ] = remainder;
3180
3181 /* Set condition codes. */
3182 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3183
3184 if (overflow) PSW |= PSW_OV;
3185 if (quotient == 0) PSW |= PSW_Z;
3186 if (quotient & 0x80000000) PSW |= PSW_S;
3187
3188 trace_output (OP_IMM_REG_REG_REG);
3189 }
3190 /* end-sanitize-v850eq */
3191
3192 return 4;
3193 }
3194
3195 /* divh reg1, reg2, reg3 */
3196 int
3197 OP_28007E0 (void)
3198 {
3199 signed long int quotient;
3200 signed long int remainder;
3201 signed long int divide_by;
3202 signed long int divide_this;
3203 boolean overflow = false;
3204
3205 if ((OP[3] & 0x3c0000) == 0)
3206 {
3207 trace_input ("divh", OP_REG_REG_REG, 0);
3208
3209 /* Compute the result. */
3210
3211 divide_by = State.regs[ OP[0] ];
3212 divide_this = EXTEND16 (State.regs[ OP[1] ]);
3213
3214 if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
3215 {
3216 overflow = true;
3217 divide_by = 1;
3218 }
3219
3220 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
3221 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
3222
3223 /* Set condition codes. */
3224 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3225
3226 if (overflow) PSW |= PSW_OV;
3227 if (quotient == 0) PSW |= PSW_Z;
3228 if (quotient < 0) PSW |= PSW_S;
3229
3230 trace_output (OP_REG_REG_REG);
3231 }
3232 /* start-sanitize-v850eq */
3233 /* divhn imm5, reg1, reg2, reg3 */
3234 else
3235 {
3236 unsigned int imm5;
3237
3238 trace_input ("divhn", OP_IMM_REG_REG_REG, 0);
3239
3240 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
3241
3242 divide_by = EXTEND16 (State.regs[ OP[0] ]);
3243 divide_this = State.regs[ OP[1] ];
3244
3245 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
3246
3247 State.regs[ OP[1] ] = quotient;
3248 State.regs[ OP[2] >> 11 ] = remainder;
3249
3250 /* Set condition codes. */
3251 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3252
3253 if (overflow) PSW |= PSW_OV;
3254 if (quotient == 0) PSW |= PSW_Z;
3255 if (quotient < 0) PSW |= PSW_S;
3256
3257 trace_output (OP_IMM_REG_REG_REG);
3258 }
3259 /* end-sanitize-v850eq */
3260
3261 return 4;
3262 }
3263
3264 /* mulu imm9, reg2, reg3 */
3265 int
3266 OP_24207E0 (void)
3267 {
3268 trace_input ("mulu", OP_IMM_REG_REG, 0);
3269
3270 Multiply64 (false, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
3271
3272 trace_output (OP_IMM_REG_REG);
3273
3274 return 4;
3275 }
3276
3277 /* mul imm9, reg2, reg3 */
3278 int
3279 OP_24007E0 (void)
3280 {
3281 trace_input ("mul", OP_IMM_REG_REG, 0);
3282
3283 Multiply64 (true, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
3284
3285 trace_output (OP_IMM_REG_REG);
3286
3287 return 4;
3288 }
3289
3290 /* cmov imm5, reg2, reg3 */
3291 int
3292 OP_30007E0 (void)
3293 {
3294 trace_input ("cmov", OP_IMM_REG_REG, 0);
3295
3296 State.regs[ OP[2] >> 11 ] = condition_met (OP[0]) ? SEXT5( OP[0] ) : State.regs[ OP[1] ];
3297
3298 trace_output (OP_IMM_REG_REG);
3299
3300 return 4;
3301
3302 }
3303
3304 /* ctret */
3305 int
3306 OP_14407E0 (void)
3307 {
3308 trace_input ("ctret", OP_NONE, 0);
3309
3310 PC = CTPC;
3311 PSW = CTPSW;
3312
3313 trace_output (OP_NONE);
3314
3315 return 0;
3316 }
3317
3318 /* hsw */
3319 int
3320 OP_34407E0 (void)
3321 {
3322 unsigned long value;
3323
3324 trace_input ("hsw", OP_REG_REG3, 0);
3325
3326 value = State.regs[ OP[ 1 ] ];
3327 value >>= 16;
3328 value |= (State.regs[ OP[ 1 ] ] << 16);
3329
3330 State.regs[ OP[2] >> 11 ] = value;
3331
3332 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
3333
3334 if (value == 0) PSW |= PSW_Z;
3335 if (value & 0x80000000) PSW |= PSW_S;
3336 if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;
3337
3338 trace_output (OP_REG_REG3);
3339
3340 return 4;
3341 }
3342
3343 #define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
3344
3345 /* bsw */
3346 int
3347 OP_34007E0 (void)
3348 {
3349 unsigned long value;
3350
3351 trace_input ("bsw", OP_REG_REG3, 0);
3352
3353 value = State.regs[ OP[ 1 ] ];
3354 value >>= 24;
3355 value |= (State.regs[ OP[ 1 ] ] << 24);
3356 value |= ((State.regs[ OP[ 1 ] ] << 8) & 0x00ff0000);
3357 value |= ((State.regs[ OP[ 1 ] ] >> 8) & 0x0000ff00);
3358
3359 State.regs[ OP[2] >> 11 ] = value;
3360
3361 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
3362
3363 if (value == 0) PSW |= PSW_Z;
3364 if (value & 0x80000000) PSW |= PSW_S;
3365 if (WORDHASNULLBYTE (value)) PSW |= PSW_CY;
3366
3367 trace_output (OP_REG_REG3);
3368
3369 return 4;
3370 }
3371
3372 /* bsh */
3373 int
3374 OP_34207E0 (void)
3375 {
3376 unsigned long value;
3377
3378 trace_input ("bsh", OP_REG_REG3, 0);
3379
3380 value = State.regs[ OP[ 1 ] ];
3381 value >>= 8;
3382 value |= ((State.regs[ OP[ 1 ] ] << 8) & 0xff00ff00);
3383 value |= ((State.regs[ OP[ 1 ] ] >> 8) & 0x000000ff);
3384
3385 State.regs[ OP[2] >> 11 ] = value;
3386
3387 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
3388
3389 if (value == 0) PSW |= PSW_Z;
3390 if (value & 0x80000000) PSW |= PSW_S;
3391 if (((value & 0xff) == 0) || (value & 0x00ff) == 0) PSW |= PSW_CY;
3392
3393 trace_output (OP_REG_REG3);
3394
3395 return 4;
3396 }
3397
3398 /* pushml list18 */
3399 /* ld.hu */
3400 int
3401 OP_107E0 (void)
3402 {
3403 if (OP[ 1 ] == 0)
3404 {
3405 int i;
3406
3407 trace_input ("pushml", OP_PUSHPOP3, 0);
3408
3409 /* Store the registers with lower number registers being placed at higher addresses. */
3410 for (i = 0; i < 15; i++)
3411 if ((OP[3] & (1 << type3_regs[ i ])))
3412 {
3413 SP -= 4;
3414 store_mem (SP & ~ 3, 4, State.regs[ i + 1 ]);
3415 }
3416
3417 if (OP[3] & (1 << 3))
3418 {
3419 SP -= 4;
3420
3421 store_mem (SP & ~ 3, 4, PSW);
3422 }
3423
3424 if (OP[3] & (1 << 19))
3425 {
3426 SP -= 8;
3427
3428 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
3429 {
3430 store_mem ((SP + 4) & ~ 3, 4, FEPC);
3431 store_mem ( SP & ~ 3, 4, FEPSW);
3432 }
3433 else
3434 {
3435 store_mem ((SP + 4) & ~ 3, 4, EIPC);
3436 store_mem ( SP & ~ 3, 4, EIPSW);
3437 }
3438 }
3439
3440 trace_output (OP_PUSHPOP2);
3441 }
3442 else
3443 {
3444 int adr;
3445
3446 trace_input ("ld.hu", OP_LOAD32, 2);
3447
3448 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
3449 adr &= ~0x1;
3450
3451 State.regs[ OP[1] ] = load_mem (adr, 2);
3452
3453 trace_output (OP_LOAD32);
3454 }
3455
3456 return 4;
3457 }
3458
3459 /* prepare list12, imm5 */
3460 /* ld.bu */
3461 int
3462 OP_10780 (void)
3463 {
3464 if (OP[ 1 ] == 0)
3465 {
3466 int i;
3467
3468 trace_input ("prepare", OP_PUSHPOP1, 0);
3469
3470 /* Store the registers with lower number registers being placed at higher addresses. */
3471 for (i = 0; i < 12; i++)
3472 if ((OP[3] & (1 << type1_regs[ i ])))
3473 {
3474 SP -= 4;
3475 store_mem (SP, 4, State.regs[ 20 + i ]);
3476 }
3477
3478 SP -= (OP[3] & 0x3e) << 1;
3479
3480 trace_output (OP_PUSHPOP1);
3481 }
3482 else
3483 {
3484 int adr;
3485
3486 trace_input ("ld.bu", OP_LOAD32, 1);
3487
3488 adr = (State.regs[ OP[0] ]
3489 + (EXTEND16 (OP[2] & ~1) | ((OP[3] >> 5) & 1)));
3490
3491 State.regs[ OP[1] ] = load_mem (adr, 1);
3492
3493 trace_output (OP_LOAD32);
3494 }
3495
3496 return 4;
3497 }
3498
3499 /* prepare list12, imm5, imm32 */
3500 int
3501 OP_1B0780 (void)
3502 {
3503 int i;
3504
3505 trace_input ("prepare", OP_PUSHPOP1, 0);
3506
3507 /* Store the registers with lower number registers being placed at higher addresses. */
3508 for (i = 0; i < 12; i++)
3509 if ((OP[3] & (1 << type1_regs[ i ])))
3510 {
3511 SP -= 4;
3512 store_mem (SP, 4, State.regs[ 20 + i ]);
3513 }
3514
3515 SP -= (OP[3] & 0x3e) << 1;
3516
3517 EP = load_mem (PC + 4, 4);
3518
3519 trace_output (OP_PUSHPOP1);
3520
3521 return 8;
3522 }
3523
3524 /* prepare list12, imm5, imm16-32 */
3525 int
3526 OP_130780 (void)
3527 {
3528 int i;
3529
3530 trace_input ("prepare", OP_PUSHPOP1, 0);
3531
3532 /* Store the registers with lower number registers being placed at higher addresses. */
3533 for (i = 0; i < 12; i++)
3534 if ((OP[3] & (1 << type1_regs[ i ])))
3535 {
3536 SP -= 4;
3537 store_mem (SP, 4, State.regs[ 20 + i ]);
3538 }
3539
3540 SP -= (OP[3] & 0x3e) << 1;
3541
3542 EP = load_mem (PC + 4, 2) << 16;
3543
3544 trace_output (OP_PUSHPOP1);
3545
3546 return 6;
3547 }
3548
3549 /* prepare list12, imm5, imm16 */
3550 int
3551 OP_B0780 (void)
3552 {
3553 int i;
3554
3555 trace_input ("prepare", OP_PUSHPOP1, 0);
3556
3557 /* Store the registers with lower number registers being placed at higher addresses. */
3558 for (i = 0; i < 12; i++)
3559 if ((OP[3] & (1 << type1_regs[ i ])))
3560 {
3561 SP -= 4;
3562 store_mem (SP, 4, State.regs[ 20 + i ]);
3563 }
3564
3565 SP -= (OP[3] & 0x3e) << 1;
3566
3567 EP = EXTEND16 (load_mem (PC + 4, 2));
3568
3569 trace_output (OP_PUSHPOP1);
3570
3571 return 6;
3572 }
3573
3574 /* prepare list12, imm5, sp */
3575 int
3576 OP_30780 (void)
3577 {
3578 int i;
3579
3580 trace_input ("prepare", OP_PUSHPOP1, 0);
3581
3582 /* Store the registers with lower number registers being placed at higher addresses. */
3583 for (i = 0; i < 12; i++)
3584 if ((OP[3] & (1 << type1_regs[ i ])))
3585 {
3586 SP -= 4;
3587 store_mem (SP, 4, State.regs[ 20 + i ]);
3588 }
3589
3590 SP -= (OP[3] & 0x3e) << 1;
3591
3592 EP = SP;
3593
3594 trace_output (OP_PUSHPOP1);
3595
3596 return 4;
3597 }
3598
3599 /* sld.hu */
3600 int
3601 OP_70 (void)
3602 {
3603 unsigned long result;
3604
3605 result = load_mem (State.regs[30] + ((OP[3] & 0xf) << 1), 2);
3606
3607 /* start-sanitize-v850eq */
3608 #ifdef ARCH_v850eq
3609 trace_input ("sld.h", OP_LOAD16, 2);
3610
3611 State.regs[ OP[1] ] = EXTEND16 (result);
3612 #else
3613 /* end-sanitize-v850eq */
3614 trace_input ("sld.hu", OP_LOAD16, 2);
3615
3616 State.regs[ OP[1] ] = result;
3617 /* start-sanitize-v850eq */
3618 #endif
3619 /* end-sanitize-v850eq */
3620
3621 trace_output (OP_LOAD16);
3622
3623 return 2;
3624 }
3625
3626 /* cmov reg1, reg2, reg3 */
3627 int
3628 OP_32007E0 (void)
3629 {
3630 trace_input ("cmov", OP_REG_REG_REG, 0);
3631
3632 State.regs[ OP[2] >> 11 ] = condition_met (OP[0]) ? State.regs[ OP[0] ] : State.regs[ OP[1] ];
3633
3634 trace_output (OP_REG_REG_REG);
3635
3636 return 4;
3637 }
3638
3639 /* mul reg1, reg2, reg3 */
3640 int
3641 OP_22007E0 (void)
3642 {
3643 trace_input ("mul", OP_REG_REG_REG, 0);
3644
3645 Multiply64 (true, State.regs[ OP[0] ]);
3646
3647 trace_output (OP_REG_REG_REG);
3648
3649 return 4;
3650 }
3651
3652 /* end-sanitize-v850e */
3653 /* start-sanitize-v850eq */
3654
3655 /* popmh list18 */
3656 int
3657 OP_307F0 (void)
3658 {
3659 int i;
3660
3661 trace_input ("popmh", OP_PUSHPOP2, 0);
3662
3663 if (OP[3] & (1 << 19))
3664 {
3665 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
3666 {
3667 FEPSW = load_mem ( SP & ~ 3, 4);
3668 FEPC = load_mem ((SP + 4) & ~ 3, 4);
3669 }
3670 else
3671 {
3672 EIPSW = load_mem ( SP & ~ 3, 4);
3673 EIPC = load_mem ((SP + 4) & ~ 3, 4);
3674 }
3675
3676 SP += 8;
3677 }
3678
3679 /* Load the registers with lower number registers being retrieved from higher addresses. */
3680 for (i = 16; i--;)
3681 if ((OP[3] & (1 << type2_regs[ i ])))
3682 {
3683 State.regs[ i + 16 ] = load_mem (SP & ~ 3, 4);
3684 SP += 4;
3685 }
3686
3687 trace_output (OP_PUSHPOP2);
3688
3689 return 4;
3690 }
3691
3692 /* popml lsit18 */
3693 int
3694 OP_107F0 (void)
3695 {
3696 int i;
3697
3698 trace_input ("popml", OP_PUSHPOP3, 0);
3699
3700 if (OP[3] & (1 << 19))
3701 {
3702 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
3703 {
3704 FEPSW = load_mem ( SP & ~ 3, 4);
3705 FEPC = load_mem ((SP + 4) & ~ 3, 4);
3706 }
3707 else
3708 {
3709 EIPSW = load_mem ( SP & ~ 3, 4);
3710 EIPC = load_mem ((SP + 4) & ~ 3, 4);
3711 }
3712
3713 SP += 8;
3714 }
3715
3716 if (OP[3] & (1 << 3))
3717 {
3718 PSW = load_mem (SP & ~ 3, 4);
3719 SP += 4;
3720 }
3721
3722 /* Load the registers with lower number registers being retrieved from higher addresses. */
3723 for (i = 15; i--;)
3724 if ((OP[3] & (1 << type3_regs[ i ])))
3725 {
3726 State.regs[ i + 1 ] = load_mem (SP & ~ 3, 4);
3727 SP += 4;
3728 }
3729
3730 trace_output (OP_PUSHPOP2);
3731
3732 return 4;
3733 }
3734
3735 /* pushmh list18 */
3736 int
3737 OP_307E0 (void)
3738 {
3739 int i;
3740
3741 trace_input ("pushmh", OP_PUSHPOP2, 0);
3742
3743 /* Store the registers with lower number registers being placed at higher addresses. */
3744 for (i = 0; i < 16; i++)
3745 if ((OP[3] & (1 << type2_regs[ i ])))
3746 {
3747 SP -= 4;
3748 store_mem (SP & ~ 3, 4, State.regs[ i + 16 ]);
3749 }
3750
3751 if (OP[3] & (1 << 19))
3752 {
3753 SP -= 8;
3754
3755 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
3756 {
3757 store_mem ((SP + 4) & ~ 3, 4, FEPC);
3758 store_mem ( SP & ~ 3, 4, FEPSW);
3759 }
3760 else
3761 {
3762 store_mem ((SP + 4) & ~ 3, 4, EIPC);
3763 store_mem ( SP & ~ 3, 4, EIPSW);
3764 }
3765 }
3766
3767 trace_output (OP_PUSHPOP2);
3768
3769 return 4;
3770 }
3771
3772 /* end-sanitize-v850eq */
GDB Binutils - Deliverables
This page took 0.107463 seconds and 4 git commands to generate.