27 #include "targ-vals.h"
29 #include "libiberty.h"
32 #if !defined(__GO32__) && !defined(_WIN32)
34 #include <sys/times.h>
38 /* This is an array of the bit positions of registers r20 .. r31 in
39 that order in a prepare/dispose instruction. */
40 int type1_regs
[12] = { 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 0, 21 };
41 /* This is an array of the bit positions of registers r16 .. r31 in
42 that order in a push/pop instruction. */
43 int type2_regs
[16] = { 3, 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
44 /* This is an array of the bit positions of registers r1 .. r15 in
45 that order in a push/pop instruction. */
46 int type3_regs
[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
49 #ifndef SIZE_INSTRUCTION
50 #define SIZE_INSTRUCTION 18
54 #define SIZE_VALUES 11
58 unsigned32 trace_values
[3];
61 const char *trace_name
;
66 trace_input (name
, type
, size
)
72 if (!TRACE_ALU_P (STATE_CPU (simulator
, 0)))
77 trace_module
= TRACE_ALU_IDX
;
90 trace_values
[0] = State
.regs
[OP
[0]];
97 trace_values
[0] = State
.regs
[OP
[1]];
98 trace_values
[1] = State
.regs
[OP
[0]];
104 trace_values
[0] = SEXT5 (OP
[0]);
105 trace_values
[1] = OP
[1];
106 trace_num_values
= 2;
109 case OP_IMM_REG_MOVE
:
110 trace_values
[0] = SEXT5 (OP
[0]);
111 trace_num_values
= 1;
115 trace_values
[0] = State
.pc
;
116 trace_values
[1] = SEXT9 (OP
[0]);
117 trace_values
[2] = PSW
;
118 trace_num_values
= 3;
122 trace_values
[0] = OP
[1] * size
;
123 trace_values
[1] = State
.regs
[30];
124 trace_num_values
= 2;
128 trace_values
[0] = State
.regs
[OP
[0]];
129 trace_values
[1] = OP
[1] * size
;
130 trace_values
[2] = State
.regs
[30];
131 trace_num_values
= 3;
135 trace_values
[0] = EXTEND16 (OP
[2]);
136 trace_values
[1] = State
.regs
[OP
[0]];
137 trace_num_values
= 2;
141 trace_values
[0] = State
.regs
[OP
[1]];
142 trace_values
[1] = EXTEND16 (OP
[2]);
143 trace_values
[2] = State
.regs
[OP
[0]];
144 trace_num_values
= 3;
148 trace_values
[0] = SEXT22 (OP
[0]);
149 trace_values
[1] = State
.pc
;
150 trace_num_values
= 2;
154 trace_values
[0] = EXTEND16 (OP
[0]) << size
;
155 trace_values
[1] = State
.regs
[OP
[1]];
156 trace_num_values
= 2;
159 case OP_IMM16_REG_REG
:
160 trace_values
[0] = EXTEND16 (OP
[2]) << size
;
161 trace_values
[1] = State
.regs
[OP
[1]];
162 trace_num_values
= 2;
165 case OP_UIMM_REG_REG
:
166 trace_values
[0] = (OP
[0] & 0xffff) << size
;
167 trace_values
[1] = State
.regs
[OP
[1]];
168 trace_num_values
= 2;
171 case OP_UIMM16_REG_REG
:
172 trace_values
[0] = (OP
[2]) << size
;
173 trace_values
[1] = State
.regs
[OP
[1]];
174 trace_num_values
= 2;
178 trace_num_values
= 0;
182 trace_values
[0] = PSW
;
183 trace_num_values
= 1;
187 trace_num_values
= 0;
191 trace_values
[0] = State
.regs
[OP
[0]];
192 trace_num_values
= 1;
196 trace_values
[0] = State
.sregs
[OP
[1]];
197 trace_num_values
= 1;
203 trace_result (int has_result
, unsigned32 result
)
211 /* write out the values saved during the trace_input call */
214 for (i
= 0; i
< trace_num_values
; i
++)
216 sprintf (chp
, "%*s0x%.8lx", SIZE_VALUES
- 10, "",
217 (long) trace_values
[i
]);
218 chp
= strchr (chp
, '\0');
222 sprintf (chp
, "%*s", SIZE_VALUES
, "");
223 chp
= strchr (chp
, '\0');
227 /* append any result to the end of the buffer */
229 sprintf (chp
, " :: 0x%.8lx", (unsigned long)result
);
231 trace_generic (simulator
, STATE_CPU (simulator
, 0), trace_module
, buf
);
235 trace_output (result
)
236 enum op_types result
;
238 if (!TRACE_ALU_P (STATE_CPU (simulator
, 0)))
260 trace_result (1, State
.regs
[OP
[0]]);
264 case OP_REG_REG_MOVE
:
266 case OP_IMM_REG_MOVE
:
269 trace_result (1, State
.regs
[OP
[1]]);
273 case OP_UIMM_REG_REG
:
274 case OP_IMM16_REG_REG
:
275 case OP_UIMM16_REG_REG
:
276 trace_result (1, State
.regs
[OP
[1]]);
281 trace_result (1, State
.regs
[OP
[1]]);
287 trace_result (1, State
.sregs
[OP
[1]]);
294 /* Returns 1 if the specific condition is met, returns 0 otherwise. */
296 condition_met (unsigned code
)
298 unsigned int psw
= PSW
;
302 case 0x0: return ((psw
& PSW_OV
) != 0);
303 case 0x1: return ((psw
& PSW_CY
) != 0);
304 case 0x2: return ((psw
& PSW_Z
) != 0);
305 case 0x3: return ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) != 0);
306 case 0x4: return ((psw
& PSW_S
) != 0);
307 /*case 0x5: return 1;*/
308 case 0x6: return ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) != 0);
309 case 0x7: return (((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) || ((psw
& PSW_Z
) != 0)) != 0);
310 case 0x8: return ((psw
& PSW_OV
) == 0);
311 case 0x9: return ((psw
& PSW_CY
) == 0);
312 case 0xa: return ((psw
& PSW_Z
) == 0);
313 case 0xb: return ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) == 0);
314 case 0xc: return ((psw
& PSW_S
) == 0);
315 case 0xd: return ((psw
& PSW_SAT
) != 0);
316 case 0xe: return ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) == 0);
317 case 0xf: return (((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) || ((psw
& PSW_Z
) != 0)) == 0);
324 Add32 (unsigned long a1
, unsigned long a2
, int * carry
)
326 unsigned long result
= (a1
+ a2
);
328 * carry
= (result
< a1
);
334 Multiply64 (int sign
, unsigned long op0
)
345 op1
= State
.regs
[ OP
[1] ];
349 /* Compute sign of result and adjust operands if necessary. */
351 sign
= (op0
^ op1
) & 0x80000000;
353 if (((signed long) op0
) < 0)
356 if (((signed long) op1
) < 0)
360 /* We can split the 32x32 into four 16x16 operations. This ensures
361 that we do not lose precision on 32bit only hosts: */
362 lo
= ( (op0
& 0xFFFF) * (op1
& 0xFFFF));
363 mid1
= ( (op0
& 0xFFFF) * ((op1
>> 16) & 0xFFFF));
364 mid2
= (((op0
>> 16) & 0xFFFF) * (op1
& 0xFFFF));
365 hi
= (((op0
>> 16) & 0xFFFF) * ((op1
>> 16) & 0xFFFF));
367 /* We now need to add all of these results together, taking care
368 to propogate the carries from the additions: */
369 RdLo
= Add32 (lo
, (mid1
<< 16), & carry
);
371 RdLo
= Add32 (RdLo
, (mid2
<< 16), & carry
);
372 RdHi
+= (carry
+ ((mid1
>> 16) & 0xFFFF) + ((mid2
>> 16) & 0xFFFF) + hi
);
376 /* Negate result if necessary. */
380 if (RdLo
== 0xFFFFFFFF)
389 /* Don't store into register 0. */
391 State
.regs
[ OP
[1] ] = RdLo
;
393 State
.regs
[ OP
[2] >> 11 ] = RdHi
;
399 /* Read a null terminated string from memory, return in a buffer */
407 while (sim_core_read_1 (STATE_CPU (sd
, 0),
408 PC
, read_map
, addr
+ nr
) != 0)
410 buf
= NZALLOC (char, nr
+ 1);
411 sim_read (simulator
, addr
, buf
, nr
);
415 /* Read a null terminated argument vector from memory, return in a
418 fetch_argv (sd
, addr
)
424 char **buf
= xmalloc (max_nr
* sizeof (char*));
427 unsigned32 a
= sim_core_read_4 (STATE_CPU (sd
, 0),
428 PC
, read_map
, addr
+ nr
* 4);
430 buf
[nr
] = fetch_str (sd
, a
);
432 if (nr
== max_nr
- 1)
435 buf
= xrealloc (buf
, max_nr
* sizeof (char*));
447 trace_input ("sst.b", OP_STORE16
, 1);
449 store_mem (State
.regs
[30] + (OP
[3] & 0x7f), 1, State
.regs
[ OP
[1] ]);
451 trace_output (OP_STORE16
);
460 trace_input ("sst.h", OP_STORE16
, 2);
462 store_mem (State
.regs
[30] + ((OP
[3] & 0x7f) << 1), 2, State
.regs
[ OP
[1] ]);
464 trace_output (OP_STORE16
);
473 trace_input ("sst.w", OP_STORE16
, 4);
475 store_mem (State
.regs
[30] + ((OP
[3] & 0x7e) << 1), 4, State
.regs
[ OP
[1] ]);
477 trace_output (OP_STORE16
);
488 trace_input ("ld.b", OP_LOAD32
, 1);
490 adr
= State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2]);
492 State
.regs
[ OP
[1] ] = EXTEND8 (load_mem (adr
, 1));
494 trace_output (OP_LOAD32
);
505 trace_input ("ld.h", OP_LOAD32
, 2);
507 adr
= State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2]);
510 State
.regs
[ OP
[1] ] = EXTEND16 (load_mem (adr
, 2));
512 trace_output (OP_LOAD32
);
523 trace_input ("ld.w", OP_LOAD32
, 4);
525 adr
= State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2] & ~1);
528 State
.regs
[ OP
[1] ] = load_mem (adr
, 4);
530 trace_output (OP_LOAD32
);
539 trace_input ("st.b", OP_STORE32
, 1);
541 store_mem (State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2]), 1, State
.regs
[ OP
[1] ]);
543 trace_output (OP_STORE32
);
554 trace_input ("st.h", OP_STORE32
, 2);
556 adr
= State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2]);
559 store_mem (adr
, 2, State
.regs
[ OP
[1] ]);
561 trace_output (OP_STORE32
);
572 trace_input ("st.w", OP_STORE32
, 4);
574 adr
= State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2] & ~1);
577 store_mem (adr
, 4, State
.regs
[ OP
[1] ]);
579 trace_output (OP_STORE32
);
588 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
590 trace_input ("add", OP_REG_REG
, 0);
592 /* Compute the result. */
594 op0
= State
.regs
[ OP
[0] ];
595 op1
= State
.regs
[ OP
[1] ];
599 /* Compute the condition codes. */
601 s
= (result
& 0x80000000);
602 cy
= (result
< op0
|| result
< op1
);
603 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
604 && (op0
& 0x80000000) != (result
& 0x80000000));
606 /* Store the result and condition codes. */
607 State
.regs
[OP
[1]] = result
;
608 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
609 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
610 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
611 trace_output (OP_REG_REG
);
616 /* add sign_extend(imm5), reg */
620 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
623 trace_input ("add", OP_IMM_REG
, 0);
625 /* Compute the result. */
626 temp
= SEXT5 (OP
[0]);
628 op1
= State
.regs
[OP
[1]];
631 /* Compute the condition codes. */
633 s
= (result
& 0x80000000);
634 cy
= (result
< op0
|| result
< op1
);
635 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
636 && (op0
& 0x80000000) != (result
& 0x80000000));
638 /* Store the result and condition codes. */
639 State
.regs
[OP
[1]] = result
;
640 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
641 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
642 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
643 trace_output (OP_IMM_REG
);
648 /* addi sign_extend(imm16), reg, reg */
652 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
654 trace_input ("addi", OP_IMM16_REG_REG
, 0);
656 /* Compute the result. */
658 op0
= EXTEND16 (OP
[2]);
659 op1
= State
.regs
[ OP
[0] ];
662 /* Compute the condition codes. */
664 s
= (result
& 0x80000000);
665 cy
= (result
< op0
|| result
< op1
);
666 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
667 && (op0
& 0x80000000) != (result
& 0x80000000));
669 /* Store the result and condition codes. */
670 State
.regs
[OP
[1]] = result
;
671 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
672 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
673 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
674 trace_output (OP_IMM16_REG_REG
);
683 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
685 trace_input ("sub", OP_REG_REG
, 0);
686 /* Compute the result. */
687 op0
= State
.regs
[ OP
[0] ];
688 op1
= State
.regs
[ OP
[1] ];
691 /* Compute the condition codes. */
693 s
= (result
& 0x80000000);
695 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
696 && (op1
& 0x80000000) != (result
& 0x80000000));
698 /* Store the result and condition codes. */
699 State
.regs
[OP
[1]] = result
;
700 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
701 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
702 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
703 trace_output (OP_REG_REG
);
708 /* subr reg1, reg2 */
712 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
714 trace_input ("subr", OP_REG_REG
, 0);
715 /* Compute the result. */
716 op0
= State
.regs
[ OP
[0] ];
717 op1
= State
.regs
[ OP
[1] ];
720 /* Compute the condition codes. */
722 s
= (result
& 0x80000000);
724 ov
= ((op0
& 0x80000000) != (op1
& 0x80000000)
725 && (op0
& 0x80000000) != (result
& 0x80000000));
727 /* Store the result and condition codes. */
728 State
.regs
[OP
[1]] = result
;
729 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
730 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
731 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
732 trace_output (OP_REG_REG
);
741 trace_input ("mulh", OP_REG_REG
, 0);
743 State
.regs
[ OP
[1] ] = (EXTEND16 (State
.regs
[ OP
[1] ]) * EXTEND16 (State
.regs
[ OP
[0] ]));
745 trace_output (OP_REG_REG
);
750 /* mulh sign_extend(imm5), reg2 */
754 trace_input ("mulh", OP_IMM_REG
, 0);
756 State
.regs
[ OP
[1] ] = EXTEND16 (State
.regs
[ OP
[1] ]) * SEXT5 (OP
[0]);
758 trace_output (OP_IMM_REG
);
763 /* mulhi imm16, reg1, reg2 */
767 trace_input ("mulhi", OP_IMM16_REG_REG
, 0);
769 State
.regs
[ OP
[1] ] = EXTEND16 (State
.regs
[ OP
[0] ]) * EXTEND16 (OP
[2]);
771 trace_output (OP_IMM16_REG_REG
);
780 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
782 trace_input ("cmp", OP_REG_REG_CMP
, 0);
783 /* Compute the result. */
784 op0
= State
.regs
[ OP
[0] ];
785 op1
= State
.regs
[ OP
[1] ];
788 /* Compute the condition codes. */
790 s
= (result
& 0x80000000);
792 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
793 && (op1
& 0x80000000) != (result
& 0x80000000));
795 /* Set condition codes. */
796 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
797 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
798 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
799 trace_output (OP_REG_REG_CMP
);
804 /* cmp sign_extend(imm5), reg */
808 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
811 /* Compute the result. */
812 trace_input ("cmp", OP_IMM_REG_CMP
, 0);
813 temp
= SEXT5 (OP
[0]);
815 op1
= State
.regs
[OP
[1]];
818 /* Compute the condition codes. */
820 s
= (result
& 0x80000000);
822 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
823 && (op1
& 0x80000000) != (result
& 0x80000000));
825 /* Set condition codes. */
826 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
827 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
828 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
829 trace_output (OP_IMM_REG_CMP
);
838 trace_input ("setf", OP_EX1
, 0);
840 State
.regs
[ OP
[1] ] = condition_met (OP
[0]);
842 trace_output (OP_EX1
);
851 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
853 trace_input ("satadd", OP_REG_REG
, 0);
854 /* Compute the result. */
855 op0
= State
.regs
[ OP
[0] ];
856 op1
= State
.regs
[ OP
[1] ];
859 /* Compute the condition codes. */
861 s
= (result
& 0x80000000);
862 cy
= (result
< op0
|| result
< op1
);
863 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
864 && (op0
& 0x80000000) != (result
& 0x80000000));
867 /* Store the result and condition codes. */
868 State
.regs
[OP
[1]] = result
;
869 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
870 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
871 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
872 | (sat
? PSW_SAT
: 0));
874 /* Handle saturated results. */
876 State
.regs
[OP
[1]] = 0x80000000;
878 State
.regs
[OP
[1]] = 0x7fffffff;
879 trace_output (OP_REG_REG
);
884 /* satadd sign_extend(imm5), reg */
888 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
892 trace_input ("satadd", OP_IMM_REG
, 0);
894 /* Compute the result. */
895 temp
= SEXT5 (OP
[0]);
897 op1
= State
.regs
[OP
[1]];
900 /* Compute the condition codes. */
902 s
= (result
& 0x80000000);
903 cy
= (result
< op0
|| result
< op1
);
904 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
905 && (op0
& 0x80000000) != (result
& 0x80000000));
908 /* Store the result and condition codes. */
909 State
.regs
[OP
[1]] = result
;
910 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
911 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
912 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
913 | (sat
? PSW_SAT
: 0));
915 /* Handle saturated results. */
917 State
.regs
[OP
[1]] = 0x80000000;
919 State
.regs
[OP
[1]] = 0x7fffffff;
920 trace_output (OP_IMM_REG
);
925 /* satsub reg1, reg2 */
929 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
931 trace_input ("satsub", OP_REG_REG
, 0);
933 /* Compute the result. */
934 op0
= State
.regs
[ OP
[0] ];
935 op1
= State
.regs
[ OP
[1] ];
938 /* Compute the condition codes. */
940 s
= (result
& 0x80000000);
942 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
943 && (op1
& 0x80000000) != (result
& 0x80000000));
946 /* Store the result and condition codes. */
947 State
.regs
[OP
[1]] = result
;
948 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
949 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
950 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
951 | (sat
? PSW_SAT
: 0));
953 /* Handle saturated results. */
955 State
.regs
[OP
[1]] = 0x80000000;
957 State
.regs
[OP
[1]] = 0x7fffffff;
958 trace_output (OP_REG_REG
);
962 /* satsubi sign_extend(imm16), reg */
966 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
969 trace_input ("satsubi", OP_IMM_REG
, 0);
971 /* Compute the result. */
972 temp
= EXTEND16 (OP
[2]);
974 op1
= State
.regs
[ OP
[0] ];
977 /* Compute the condition codes. */
979 s
= (result
& 0x80000000);
981 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
982 && (op1
& 0x80000000) != (result
& 0x80000000));
985 /* Store the result and condition codes. */
986 State
.regs
[OP
[1]] = result
;
987 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
988 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
989 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
990 | (sat
? PSW_SAT
: 0));
992 /* Handle saturated results. */
994 State
.regs
[OP
[1]] = 0x80000000;
996 State
.regs
[OP
[1]] = 0x7fffffff;
997 trace_output (OP_IMM_REG
);
1002 /* satsubr reg,reg */
1006 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1008 trace_input ("satsubr", OP_REG_REG
, 0);
1010 /* Compute the result. */
1011 op0
= State
.regs
[ OP
[0] ];
1012 op1
= State
.regs
[ OP
[1] ];
1015 /* Compute the condition codes. */
1017 s
= (result
& 0x80000000);
1018 cy
= (result
< op0
);
1019 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1020 && (op1
& 0x80000000) != (result
& 0x80000000));
1023 /* Store the result and condition codes. */
1024 State
.regs
[OP
[1]] = result
;
1025 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1026 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1027 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1028 | (sat
? PSW_SAT
: 0));
1030 /* Handle saturated results. */
1032 State
.regs
[OP
[1]] = 0x80000000;
1034 State
.regs
[OP
[1]] = 0x7fffffff;
1035 trace_output (OP_REG_REG
);
1044 unsigned int op0
, op1
, result
, z
, s
;
1046 trace_input ("tst", OP_REG_REG_CMP
, 0);
1048 /* Compute the result. */
1049 op0
= State
.regs
[ OP
[0] ];
1050 op1
= State
.regs
[ OP
[1] ];
1053 /* Compute the condition codes. */
1055 s
= (result
& 0x80000000);
1057 /* Store the condition codes. */
1058 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1059 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1060 trace_output (OP_REG_REG_CMP
);
1065 /* mov sign_extend(imm5), reg */
1069 int value
= SEXT5 (OP
[0]);
1071 trace_input ("mov", OP_IMM_REG_MOVE
, 0);
1073 State
.regs
[ OP
[1] ] = value
;
1075 trace_output (OP_IMM_REG_MOVE
);
1080 /* movhi imm16, reg, reg */
1084 trace_input ("movhi", OP_UIMM16_REG_REG
, 16);
1086 State
.regs
[ OP
[1] ] = State
.regs
[ OP
[0] ] + (OP
[2] << 16);
1088 trace_output (OP_UIMM16_REG_REG
);
1093 /* sar zero_extend(imm5),reg1 */
1097 unsigned int op0
, op1
, result
, z
, s
, cy
;
1099 trace_input ("sar", OP_IMM_REG
, 0);
1101 op1
= State
.regs
[ OP
[1] ];
1102 result
= (signed)op1
>> op0
;
1104 /* Compute the condition codes. */
1106 s
= (result
& 0x80000000);
1107 cy
= (op1
& (1 << (op0
- 1)));
1109 /* Store the result and condition codes. */
1110 State
.regs
[ OP
[1] ] = result
;
1111 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1112 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1113 | (cy
? PSW_CY
: 0));
1114 trace_output (OP_IMM_REG
);
1119 /* sar reg1, reg2 */
1123 unsigned int op0
, op1
, result
, z
, s
, cy
;
1125 trace_input ("sar", OP_REG_REG
, 0);
1127 op0
= State
.regs
[ OP
[0] ] & 0x1f;
1128 op1
= State
.regs
[ OP
[1] ];
1129 result
= (signed)op1
>> op0
;
1131 /* Compute the condition codes. */
1133 s
= (result
& 0x80000000);
1134 cy
= (op1
& (1 << (op0
- 1)));
1136 /* Store the result and condition codes. */
1137 State
.regs
[OP
[1]] = result
;
1138 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1139 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1140 | (cy
? PSW_CY
: 0));
1141 trace_output (OP_REG_REG
);
1146 /* shl zero_extend(imm5),reg1 */
1150 unsigned int op0
, op1
, result
, z
, s
, cy
;
1152 trace_input ("shl", OP_IMM_REG
, 0);
1154 op1
= State
.regs
[ OP
[1] ];
1155 result
= op1
<< op0
;
1157 /* Compute the condition codes. */
1159 s
= (result
& 0x80000000);
1160 cy
= (op1
& (1 << (32 - op0
)));
1162 /* Store the result and condition codes. */
1163 State
.regs
[OP
[1]] = result
;
1164 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1165 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1166 | (cy
? PSW_CY
: 0));
1167 trace_output (OP_IMM_REG
);
1172 /* shl reg1, reg2 */
1176 unsigned int op0
, op1
, result
, z
, s
, cy
;
1178 trace_input ("shl", OP_REG_REG
, 0);
1179 op0
= State
.regs
[ OP
[0] ] & 0x1f;
1180 op1
= State
.regs
[ OP
[1] ];
1181 result
= op1
<< op0
;
1183 /* Compute the condition codes. */
1185 s
= (result
& 0x80000000);
1186 cy
= (op1
& (1 << (32 - op0
)));
1188 /* Store the result and condition codes. */
1189 State
.regs
[OP
[1]] = result
;
1190 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1191 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1192 | (cy
? PSW_CY
: 0));
1193 trace_output (OP_REG_REG
);
1198 /* shr zero_extend(imm5),reg1 */
1202 unsigned int op0
, op1
, result
, z
, s
, cy
;
1204 trace_input ("shr", OP_IMM_REG
, 0);
1206 op1
= State
.regs
[ OP
[1] ];
1207 result
= op1
>> op0
;
1209 /* Compute the condition codes. */
1211 s
= (result
& 0x80000000);
1212 cy
= (op1
& (1 << (op0
- 1)));
1214 /* Store the result and condition codes. */
1215 State
.regs
[OP
[1]] = result
;
1216 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1217 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1218 | (cy
? PSW_CY
: 0));
1219 trace_output (OP_IMM_REG
);
1224 /* shr reg1, reg2 */
1228 unsigned int op0
, op1
, result
, z
, s
, cy
;
1230 trace_input ("shr", OP_REG_REG
, 0);
1231 op0
= State
.regs
[ OP
[0] ] & 0x1f;
1232 op1
= State
.regs
[ OP
[1] ];
1233 result
= op1
>> op0
;
1235 /* Compute the condition codes. */
1237 s
= (result
& 0x80000000);
1238 cy
= (op1
& (1 << (op0
- 1)));
1240 /* Store the result and condition codes. */
1241 State
.regs
[OP
[1]] = result
;
1242 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1243 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1244 | (cy
? PSW_CY
: 0));
1245 trace_output (OP_REG_REG
);
1254 unsigned int op0
, op1
, result
, z
, s
;
1256 trace_input ("or", OP_REG_REG
, 0);
1258 /* Compute the result. */
1259 op0
= State
.regs
[ OP
[0] ];
1260 op1
= State
.regs
[ OP
[1] ];
1263 /* Compute the condition codes. */
1265 s
= (result
& 0x80000000);
1267 /* Store the result and condition codes. */
1268 State
.regs
[OP
[1]] = result
;
1269 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1270 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1271 trace_output (OP_REG_REG
);
1276 /* ori zero_extend(imm16), reg, reg */
1280 unsigned int op0
, op1
, result
, z
, s
;
1282 trace_input ("ori", OP_UIMM16_REG_REG
, 0);
1284 op1
= State
.regs
[ OP
[0] ];
1287 /* Compute the condition codes. */
1289 s
= (result
& 0x80000000);
1291 /* Store the result and condition codes. */
1292 State
.regs
[OP
[1]] = result
;
1293 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1294 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1295 trace_output (OP_UIMM16_REG_REG
);
1304 unsigned int op0
, op1
, result
, z
, s
;
1306 trace_input ("and", OP_REG_REG
, 0);
1308 /* Compute the result. */
1309 op0
= State
.regs
[ OP
[0] ];
1310 op1
= State
.regs
[ OP
[1] ];
1313 /* Compute the condition codes. */
1315 s
= (result
& 0x80000000);
1317 /* Store the result and condition codes. */
1318 State
.regs
[OP
[1]] = result
;
1319 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1320 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1321 trace_output (OP_REG_REG
);
1326 /* andi zero_extend(imm16), reg, reg */
1330 unsigned int result
, z
;
1332 trace_input ("andi", OP_UIMM16_REG_REG
, 0);
1334 result
= OP
[2] & State
.regs
[ OP
[0] ];
1336 /* Compute the condition codes. */
1339 /* Store the result and condition codes. */
1340 State
.regs
[ OP
[1] ] = result
;
1342 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1343 PSW
|= (z
? PSW_Z
: 0);
1345 trace_output (OP_UIMM16_REG_REG
);
1354 unsigned int op0
, op1
, result
, z
, s
;
1356 trace_input ("xor", OP_REG_REG
, 0);
1358 /* Compute the result. */
1359 op0
= State
.regs
[ OP
[0] ];
1360 op1
= State
.regs
[ OP
[1] ];
1363 /* Compute the condition codes. */
1365 s
= (result
& 0x80000000);
1367 /* Store the result and condition codes. */
1368 State
.regs
[OP
[1]] = result
;
1369 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1370 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1371 trace_output (OP_REG_REG
);
1376 /* xori zero_extend(imm16), reg, reg */
1380 unsigned int op0
, op1
, result
, z
, s
;
1382 trace_input ("xori", OP_UIMM16_REG_REG
, 0);
1384 op1
= State
.regs
[ OP
[0] ];
1387 /* Compute the condition codes. */
1389 s
= (result
& 0x80000000);
1391 /* Store the result and condition codes. */
1392 State
.regs
[OP
[1]] = result
;
1393 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1394 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1395 trace_output (OP_UIMM16_REG_REG
);
1400 /* not reg1, reg2 */
1404 unsigned int op0
, result
, z
, s
;
1406 trace_input ("not", OP_REG_REG_MOVE
, 0);
1407 /* Compute the result. */
1408 op0
= State
.regs
[ OP
[0] ];
1411 /* Compute the condition codes. */
1413 s
= (result
& 0x80000000);
1415 /* Store the result and condition codes. */
1416 State
.regs
[OP
[1]] = result
;
1417 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1418 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1419 trace_output (OP_REG_REG_MOVE
);
1428 unsigned int op0
, op1
, op2
;
1431 trace_input ("set1", OP_BIT
, 0);
1432 op0
= State
.regs
[ OP
[0] ];
1434 temp
= EXTEND16 (OP
[2]);
1436 temp
= load_mem (op0
+ op2
, 1);
1438 if ((temp
& (1 << op1
)) == 0)
1441 store_mem (op0
+ op2
, 1, temp
);
1442 trace_output (OP_BIT
);
1451 unsigned int op0
, op1
, op2
;
1454 trace_input ("not1", OP_BIT
, 0);
1455 op0
= State
.regs
[ OP
[0] ];
1457 temp
= EXTEND16 (OP
[2]);
1459 temp
= load_mem (op0
+ op2
, 1);
1461 if ((temp
& (1 << op1
)) == 0)
1464 store_mem (op0
+ op2
, 1, temp
);
1465 trace_output (OP_BIT
);
1474 unsigned int op0
, op1
, op2
;
1477 trace_input ("clr1", OP_BIT
, 0);
1478 op0
= State
.regs
[ OP
[0] ];
1480 temp
= EXTEND16 (OP
[2]);
1482 temp
= load_mem (op0
+ op2
, 1);
1484 if ((temp
& (1 << op1
)) == 0)
1486 temp
&= ~(1 << op1
);
1487 store_mem (op0
+ op2
, 1, temp
);
1488 trace_output (OP_BIT
);
1497 unsigned int op0
, op1
, op2
;
1500 trace_input ("tst1", OP_BIT
, 0);
1501 op0
= State
.regs
[ OP
[0] ];
1503 temp
= EXTEND16 (OP
[2]);
1505 temp
= load_mem (op0
+ op2
, 1);
1507 if ((temp
& (1 << op1
)) == 0)
1509 trace_output (OP_BIT
);
1518 trace_input ("di", OP_NONE
, 0);
1520 trace_output (OP_NONE
);
1529 trace_input ("ei", OP_NONE
, 0);
1531 trace_output (OP_NONE
);
1540 trace_input ("halt", OP_NONE
, 0);
1541 /* FIXME this should put processor into a mode where NMI still handled */
1542 trace_output (OP_NONE
);
1543 sim_engine_halt (simulator
, STATE_CPU (simulator
, 0), NULL
, PC
,
1544 sim_stopped
, SIM_SIGTRAP
);
1552 trace_input ("trap", OP_TRAP
, 0);
1553 trace_output (OP_TRAP
);
1555 /* Trap 31 is used for simulating OS I/O functions */
1559 int save_errno
= errno
;
1562 /* Registers passed to trap 0 */
1564 #define FUNC State.regs[6] /* function number, return value */
1565 #define PARM1 State.regs[7] /* optional parm 1 */
1566 #define PARM2 State.regs[8] /* optional parm 2 */
1567 #define PARM3 State.regs[9] /* optional parm 3 */
1569 /* Registers set by trap 0 */
1571 #define RETVAL State.regs[10] /* return value */
1572 #define RETERR State.regs[11] /* return error code */
1574 /* Turn a pointer in a register into a pointer into real memory. */
1576 #define MEMPTR(x) (map (x))
1582 #ifdef TARGET_SYS_fork
1583 case TARGET_SYS_fork
:
1590 #ifdef TARGET_SYS_execv
1591 case TARGET_SYS_execve
:
1593 char *path
= fetch_str (simulator
, PARM1
);
1594 char **argv
= fetch_argv (simulator
, PARM2
);
1595 char **envp
= fetch_argv (simulator
, PARM3
);
1596 RETVAL
= execve (path
, argv
, envp
);
1606 #ifdef TARGET_SYS_execv
1607 case TARGET_SYS_execv
:
1609 char *path
= fetch_str (simulator
, PARM1
);
1610 char **argv
= fetch_argv (simulator
, PARM2
);
1611 RETVAL
= execv (path
, argv
);
1620 #ifdef TARGET_SYS_pipe
1621 case TARGET_SYS_pipe
:
1627 RETVAL
= pipe (host_fd
);
1628 SW (buf
, host_fd
[0]);
1629 buf
+= sizeof(uint16
);
1630 SW (buf
, host_fd
[1]);
1637 #ifdef TARGET_SYS_wait
1638 case TARGET_SYS_wait
:
1642 RETVAL
= wait (&status
);
1649 #ifdef TARGET_SYS_read
1650 case TARGET_SYS_read
:
1652 char *buf
= zalloc (PARM3
);
1653 RETVAL
= sim_io_read (simulator
, PARM1
, buf
, PARM3
);
1654 sim_write (simulator
, PARM2
, buf
, PARM3
);
1660 #ifdef TARGET_SYS_write
1661 case TARGET_SYS_write
:
1663 char *buf
= zalloc (PARM3
);
1664 sim_read (simulator
, PARM2
, buf
, PARM3
);
1666 RETVAL
= sim_io_write_stdout (simulator
, buf
, PARM3
);
1668 RETVAL
= sim_io_write (simulator
, PARM1
, buf
, PARM3
);
1674 #ifdef TARGET_SYS_lseek
1675 case TARGET_SYS_lseek
:
1676 RETVAL
= sim_io_lseek (simulator
, PARM1
, PARM2
, PARM3
);
1680 #ifdef TARGET_SYS_close
1681 case TARGET_SYS_close
:
1682 RETVAL
= sim_io_close (simulator
, PARM1
);
1686 #ifdef TARGET_SYS_open
1687 case TARGET_SYS_open
:
1689 char *buf
= fetch_str (simulator
, PARM1
);
1690 RETVAL
= sim_io_open (simulator
, buf
, PARM2
);
1696 #ifdef TARGET_SYS_exit
1697 case TARGET_SYS_exit
:
1698 if ((PARM1
& 0xffff0000) == 0xdead0000 && (PARM1
& 0xffff) != 0)
1699 /* get signal encoded by kill */
1700 sim_engine_halt (simulator
, STATE_CPU (simulator
, 0), NULL
, PC
,
1701 sim_signalled
, PARM1
& 0xffff);
1702 else if (PARM1
== 0xdead)
1704 sim_engine_halt (simulator
, STATE_CPU (simulator
, 0), NULL
, PC
,
1705 sim_stopped
, SIM_SIGABRT
);
1707 /* PARM1 has exit status */
1708 sim_engine_halt (simulator
, STATE_CPU (simulator
, 0), NULL
, PC
,
1713 #if !defined(__GO32__) && !defined(_WIN32)
1714 #ifdef TARGET_SYS_stat
1715 case TARGET_SYS_stat
: /* added at hmsi */
1716 /* stat system call */
1718 struct stat host_stat
;
1720 char *path
= fetch_str (simulator
, PARM1
);
1722 RETVAL
= stat (path
, &host_stat
);
1727 /* Just wild-assed guesses. */
1728 store_mem (buf
, 2, host_stat
.st_dev
);
1729 store_mem (buf
+ 2, 2, host_stat
.st_ino
);
1730 store_mem (buf
+ 4, 4, host_stat
.st_mode
);
1731 store_mem (buf
+ 8, 2, host_stat
.st_nlink
);
1732 store_mem (buf
+ 10, 2, host_stat
.st_uid
);
1733 store_mem (buf
+ 12, 2, host_stat
.st_gid
);
1734 store_mem (buf
+ 14, 2, host_stat
.st_rdev
);
1735 store_mem (buf
+ 16, 4, host_stat
.st_size
);
1736 store_mem (buf
+ 20, 4, host_stat
.st_atime
);
1737 store_mem (buf
+ 28, 4, host_stat
.st_mtime
);
1738 store_mem (buf
+ 36, 4, host_stat
.st_ctime
);
1745 #ifdef TARGET_SYS_chown
1746 case TARGET_SYS_chown
:
1748 char *path
= fetch_str (simulator
, PARM1
);
1749 RETVAL
= chown (path
, PARM2
, PARM3
);
1757 #ifdef TARGET_SYS_chmod
1758 case TARGET_SYS_chmod
:
1760 char *path
= fetch_str (simulator
, PARM1
);
1761 RETVAL
= chmod (path
, PARM2
);
1768 #ifdef TARGET_SYS_time
1770 case TARGET_SYS_time
:
1773 RETVAL
= time (&now
);
1774 store_mem (PARM1
, 4, now
);
1780 #if !defined(__GO32__) && !defined(_WIN32)
1781 #ifdef TARGET_SYS_times
1782 case TARGET_SYS_times
:
1785 RETVAL
= times (&tms
);
1786 store_mem (PARM1
, 4, tms
.tms_utime
);
1787 store_mem (PARM1
+ 4, 4, tms
.tms_stime
);
1788 store_mem (PARM1
+ 8, 4, tms
.tms_cutime
);
1789 store_mem (PARM1
+ 12, 4, tms
.tms_cstime
);
1795 #ifdef TARGET_SYS_gettimeofday
1796 #if !defined(__GO32__) && !defined(_WIN32)
1797 case TARGET_SYS_gettimeofday
:
1801 RETVAL
= gettimeofday (&t
, &tz
);
1802 store_mem (PARM1
, 4, t
.tv_sec
);
1803 store_mem (PARM1
+ 4, 4, t
.tv_usec
);
1804 store_mem (PARM2
, 4, tz
.tz_minuteswest
);
1805 store_mem (PARM2
+ 4, 4, tz
.tz_dsttime
);
1811 #ifdef TARGET_SYS_utime
1813 case TARGET_SYS_utime
:
1815 /* Cast the second argument to void *, to avoid type mismatch
1816 if a prototype is present. */
1817 sim_io_error (simulator
, "Utime not supported");
1818 /* RETVAL = utime (path, (void *) MEMPTR (PARM2)); */
1833 { /* Trap 0 -> 30 */
1838 ECR
|= 0x40 + OP
[0];
1839 /* Flag that we are now doing exception processing. */
1840 PSW
|= PSW_EP
| PSW_ID
;
1841 PC
= (OP
[0] < 0x10) ? 0x40 : 0x50;
1847 /* tst1 reg2, [reg1] */
1853 trace_input ("tst1", OP_BIT
, 1);
1855 temp
= load_mem (State
.regs
[ OP
[0] ], 1);
1858 if ((temp
& (1 << (State
.regs
[ OP
[1] ] & 0x7))) == 0)
1861 trace_output (OP_BIT
);
1866 /* mulu reg1, reg2, reg3 */
1870 trace_input ("mulu", OP_REG_REG_REG
, 0);
1872 Multiply64 (0, State
.regs
[ OP
[0] ]);
1874 trace_output (OP_REG_REG_REG
);
1879 #define BIT_CHANGE_OP( name, binop ) \
1881 unsigned int temp; \
1883 trace_input (name, OP_BIT_CHANGE, 0); \
1885 bit = 1 << (State.regs[ OP[1] ] & 0x7); \
1886 temp = load_mem (State.regs[ OP[0] ], 1); \
1889 if ((temp & bit) == 0) \
1893 store_mem (State.regs[ OP[0] ], 1, temp); \
1895 trace_output (OP_BIT_CHANGE); \
1899 /* clr1 reg2, [reg1] */
1903 BIT_CHANGE_OP ("clr1", &= ~ );
1906 /* not1 reg2, [reg1] */
1910 BIT_CHANGE_OP ("not1", ^= );
1917 BIT_CHANGE_OP ("set1", |= );
1924 trace_input ("sasf", OP_EX1
, 0);
1926 State
.regs
[ OP
[1] ] = (State
.regs
[ OP
[1] ] << 1) | condition_met (OP
[0]);
1928 trace_output (OP_EX1
);
1933 /* This function is courtesy of Sugimoto at NEC, via Seow Tan
1934 (Soew_Tan@el.nec.com) */
1939 unsigned long int als
,
1940 unsigned long int sfi
,
1941 unsigned32
/*unsigned long int*/ * quotient_ptr
,
1942 unsigned32
/*unsigned long int*/ * remainder_ptr
,
1946 unsigned long ald
= sfi
>> (N
- 1);
1947 unsigned long alo
= als
;
1952 unsigned int R1
= 1;
1953 unsigned int DBZ
= (als
== 0) ? 1 : 0;
1954 unsigned long alt
= Q
? ~als
: als
;
1957 alo
= ald
+ alt
+ Q
;
1958 C
= (((alt
>> 31) & (ald
>> 31))
1959 | (((alt
>> 31) ^ (ald
>> 31)) & (~alo
>> 31)));
1962 R1
= (alo
== 0) ? 0 : (R1
& Q
);
1963 if ((S
^ (alo
>>31)) && !C
)
1968 sfi
= (sfi
<< (32-N
+1)) | Q
;
1969 ald
= (alo
<< 1) | (sfi
>> 31);
1971 /* 2nd - N-1th Loop */
1972 for (i
= 2; i
< N
; i
++)
1974 alt
= Q
? ~als
: als
;
1975 alo
= ald
+ alt
+ Q
;
1976 C
= (((alt
>> 31) & (ald
>> 31))
1977 | (((alt
>> 31) ^ (ald
>> 31)) & (~alo
>> 31)));
1980 R1
= (alo
== 0) ? 0 : (R1
& Q
);
1981 if ((S
^ (alo
>>31)) && !C
&& !DBZ
)
1986 sfi
= (sfi
<< 1) | Q
;
1987 ald
= (alo
<< 1) | (sfi
>> 31);
1991 alt
= Q
? ~als
: als
;
1992 alo
= ald
+ alt
+ Q
;
1993 C
= (((alt
>> 31) & (ald
>> 31))
1994 | (((alt
>> 31) ^ (ald
>> 31)) & (~alo
>> 31)));
1997 R1
= (alo
== 0) ? 0 : (R1
& Q
);
1998 if ((S
^ (alo
>>31)) && !C
)
2003 * quotient_ptr
= (sfi
<< 1) | Q
;
2004 * remainder_ptr
= Q
? alo
: (alo
+ als
);
2005 * overflow_ptr
= DBZ
| R1
;
2008 /* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
2013 unsigned long int als
,
2014 unsigned long int sfi
,
2015 signed32
/*signed long int*/ * quotient_ptr
,
2016 signed32
/*signed long int*/ * remainder_ptr
,
2020 unsigned long ald
= (signed long) sfi
>> (N
- 1);
2021 unsigned long alo
= als
;
2022 unsigned int SS
= als
>> 31;
2023 unsigned int SD
= sfi
>> 31;
2024 unsigned int R1
= 1;
2026 unsigned int DBZ
= als
== 0 ? 1 : 0;
2027 unsigned int Q
= ~(SS
^ SD
) & 1;
2031 unsigned long alt
= Q
? ~als
: als
;
2036 alo
= ald
+ alt
+ Q
;
2037 C
= (((alt
>> 31) & (ald
>> 31))
2038 | (((alt
>> 31) ^ (ald
>> 31)) & (~alo
>> 31)));
2040 R1
= (alo
== 0) ? 0 : (R1
& (Q
^ (SS
^ SD
)));
2042 sfi
= (sfi
<< (32-N
+1)) | Q
;
2043 ald
= (alo
<< 1) | (sfi
>> 31);
2044 if ((alo
>> 31) ^ (ald
>> 31))
2049 /* 2nd - N-1th Loop */
2051 for (i
= 2; i
< N
; i
++)
2053 alt
= Q
? ~als
: als
;
2054 alo
= ald
+ alt
+ Q
;
2055 C
= (((alt
>> 31) & (ald
>> 31))
2056 | (((alt
>> 31) ^ (ald
>> 31)) & (~alo
>> 31)));
2058 R1
= (alo
== 0) ? 0 : (R1
& (Q
^ (SS
^ SD
)));
2060 sfi
= (sfi
<< 1) | Q
;
2061 ald
= (alo
<< 1) | (sfi
>> 31);
2062 if ((alo
>> 31) ^ (ald
>> 31))
2069 alt
= Q
? ~als
: als
;
2070 alo
= ald
+ alt
+ Q
;
2071 C
= (((alt
>> 31) & (ald
>> 31))
2072 | (((alt
>> 31) ^ (ald
>> 31)) & (~alo
>> 31)));
2074 R1
= (alo
== 0) ? 0 : (R1
& (Q
^ (SS
^ SD
)));
2075 sfi
= (sfi
<< (32-N
+1));
2081 alt
= Q
? ~als
: als
;
2082 alo
= ald
+ alt
+ Q
;
2084 R1
= R1
& ((~alo
>> 31) ^ SD
);
2085 if ((alo
!= 0) && ((Q
^ (SS
^ SD
)) ^ R1
)) alo
= ald
;
2087 ald
= sfi
= (long) ((sfi
>> 1) | (SS
^ SD
) << 31) >> (32-N
-1) | Q
;
2089 ald
= sfi
= sfi
| Q
;
2091 OV
= DBZ
| ((alo
== 0) ? 0 : R1
);
2093 * remainder_ptr
= alo
;
2096 if (((alo
!= 0) && ((SS
^ SD
) ^ R1
))
2097 || ((alo
== 0) && (SS
^ R1
)))
2102 OV
= (DBZ
| R1
) ? OV
: ((alo
>> 31) & (~ald
>> 31));
2104 * quotient_ptr
= alo
;
2105 * overflow_ptr
= OV
;
2108 /* sdivun imm5, reg1, reg2, reg3 */
2112 unsigned32
/*unsigned long int*/ quotient
;
2113 unsigned32
/*unsigned long int*/ remainder
;
2114 unsigned long int divide_by
;
2115 unsigned long int divide_this
;
2119 trace_input ("sdivun", OP_IMM_REG_REG_REG
, 0);
2121 imm5
= 32 - ((OP
[3] & 0x3c0000) >> 17);
2123 divide_by
= State
.regs
[ OP
[0] ];
2124 divide_this
= State
.regs
[ OP
[1] ] << imm5
;
2126 divun (imm5
, divide_by
, divide_this
, & quotient
, & remainder
, & overflow
);
2128 State
.regs
[ OP
[1] ] = quotient
;
2129 State
.regs
[ OP
[2] >> 11 ] = remainder
;
2131 /* Set condition codes. */
2132 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2134 if (overflow
) PSW
|= PSW_OV
;
2135 if (quotient
== 0) PSW
|= PSW_Z
;
2136 if (quotient
& 0x80000000) PSW
|= PSW_S
;
2138 trace_output (OP_IMM_REG_REG_REG
);
2143 /* sdivn imm5, reg1, reg2, reg3 */
2147 signed32
/*signed long int*/ quotient
;
2148 signed32
/*signed long int*/ remainder
;
2149 signed long int divide_by
;
2150 signed long int divide_this
;
2154 trace_input ("sdivn", OP_IMM_REG_REG_REG
, 0);
2156 imm5
= 32 - ((OP
[3] & 0x3c0000) >> 17);
2158 divide_by
= State
.regs
[ OP
[0] ];
2159 divide_this
= State
.regs
[ OP
[1] ] << imm5
;
2161 divn (imm5
, divide_by
, divide_this
, & quotient
, & remainder
, & overflow
);
2163 State
.regs
[ OP
[1] ] = quotient
;
2164 State
.regs
[ OP
[2] >> 11 ] = remainder
;
2166 /* Set condition codes. */
2167 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2169 if (overflow
) PSW
|= PSW_OV
;
2170 if (quotient
== 0) PSW
|= PSW_Z
;
2171 if (quotient
< 0) PSW
|= PSW_S
;
2173 trace_output (OP_IMM_REG_REG_REG
);
2178 /* sdivhun imm5, reg1, reg2, reg3 */
2182 unsigned32
/*unsigned long int*/ quotient
;
2183 unsigned32
/*unsigned long int*/ remainder
;
2184 unsigned long int divide_by
;
2185 unsigned long int divide_this
;
2189 trace_input ("sdivhun", OP_IMM_REG_REG_REG
, 0);
2191 imm5
= 32 - ((OP
[3] & 0x3c0000) >> 17);
2193 divide_by
= State
.regs
[ OP
[0] ] & 0xffff;
2194 divide_this
= State
.regs
[ OP
[1] ] << imm5
;
2196 divun (imm5
, divide_by
, divide_this
, & quotient
, & remainder
, & overflow
);
2198 State
.regs
[ OP
[1] ] = quotient
;
2199 State
.regs
[ OP
[2] >> 11 ] = remainder
;
2201 /* Set condition codes. */
2202 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2204 if (overflow
) PSW
|= PSW_OV
;
2205 if (quotient
== 0) PSW
|= PSW_Z
;
2206 if (quotient
& 0x80000000) PSW
|= PSW_S
;
2208 trace_output (OP_IMM_REG_REG_REG
);
2213 /* sdivhn imm5, reg1, reg2, reg3 */
2217 signed32
/*signed long int*/ quotient
;
2218 signed32
/*signed long int*/ remainder
;
2219 signed long int divide_by
;
2220 signed long int divide_this
;
2224 trace_input ("sdivhn", OP_IMM_REG_REG_REG
, 0);
2226 imm5
= 32 - ((OP
[3] & 0x3c0000) >> 17);
2228 divide_by
= EXTEND16 (State
.regs
[ OP
[0] ]);
2229 divide_this
= State
.regs
[ OP
[1] ] << imm5
;
2231 divn (imm5
, divide_by
, divide_this
, & quotient
, & remainder
, & overflow
);
2233 State
.regs
[ OP
[1] ] = quotient
;
2234 State
.regs
[ OP
[2] >> 11 ] = remainder
;
2236 /* Set condition codes. */
2237 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2239 if (overflow
) PSW
|= PSW_OV
;
2240 if (quotient
== 0) PSW
|= PSW_Z
;
2241 if (quotient
< 0) PSW
|= PSW_S
;
2243 trace_output (OP_IMM_REG_REG_REG
);
2248 /* divu reg1, reg2, reg3 */
2252 unsigned long int quotient
;
2253 unsigned long int remainder
;
2254 unsigned long int divide_by
;
2255 unsigned long int divide_this
;
2258 trace_input ("divu", OP_REG_REG_REG
, 0);
2260 /* Compute the result. */
2262 divide_by
= State
.regs
[ OP
[0] ];
2263 divide_this
= State
.regs
[ OP
[1] ];
2271 State
.regs
[ OP
[1] ] = quotient
= divide_this
/ divide_by
;
2272 State
.regs
[ OP
[2] >> 11 ] = remainder
= divide_this
% divide_by
;
2274 /* Set condition codes. */
2275 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2277 if (overflow
) PSW
|= PSW_OV
;
2278 if (quotient
== 0) PSW
|= PSW_Z
;
2279 if (quotient
& 0x80000000) PSW
|= PSW_S
;
2281 trace_output (OP_REG_REG_REG
);
2286 /* div reg1, reg2, reg3 */
2290 signed long int quotient
;
2291 signed long int remainder
;
2292 signed long int divide_by
;
2293 signed long int divide_this
;
2296 trace_input ("div", OP_REG_REG_REG
, 0);
2298 /* Compute the result. */
2300 divide_by
= State
.regs
[ OP
[0] ];
2301 divide_this
= State
.regs
[ OP
[1] ];
2303 if (divide_by
== 0 || (divide_by
== -1 && divide_this
== (1 << 31)))
2309 State
.regs
[ OP
[1] ] = quotient
= divide_this
/ divide_by
;
2310 State
.regs
[ OP
[2] >> 11 ] = remainder
= divide_this
% divide_by
;
2312 /* Set condition codes. */
2313 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2315 if (overflow
) PSW
|= PSW_OV
;
2316 if (quotient
== 0) PSW
|= PSW_Z
;
2317 if (quotient
< 0) PSW
|= PSW_S
;
2319 trace_output (OP_REG_REG_REG
);
2324 /* divhu reg1, reg2, reg3 */
2328 unsigned long int quotient
;
2329 unsigned long int remainder
;
2330 unsigned long int divide_by
;
2331 unsigned long int divide_this
;
2334 trace_input ("divhu", OP_REG_REG_REG
, 0);
2336 /* Compute the result. */
2338 divide_by
= State
.regs
[ OP
[0] ] & 0xffff;
2339 divide_this
= State
.regs
[ OP
[1] ];
2347 State
.regs
[ OP
[1] ] = quotient
= divide_this
/ divide_by
;
2348 State
.regs
[ OP
[2] >> 11 ] = remainder
= divide_this
% divide_by
;
2350 /* Set condition codes. */
2351 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2353 if (overflow
) PSW
|= PSW_OV
;
2354 if (quotient
== 0) PSW
|= PSW_Z
;
2355 if (quotient
& 0x80000000) PSW
|= PSW_S
;
2357 trace_output (OP_REG_REG_REG
);
2362 /* divh reg1, reg2, reg3 */
2366 signed long int quotient
;
2367 signed long int remainder
;
2368 signed long int divide_by
;
2369 signed long int divide_this
;
2372 trace_input ("divh", OP_REG_REG_REG
, 0);
2374 /* Compute the result. */
2376 divide_by
= State
.regs
[ OP
[0] ];
2377 divide_this
= EXTEND16 (State
.regs
[ OP
[1] ]);
2379 if (divide_by
== 0 || (divide_by
== -1 && divide_this
== (1 << 31)))
2385 State
.regs
[ OP
[1] ] = quotient
= divide_this
/ divide_by
;
2386 State
.regs
[ OP
[2] >> 11 ] = remainder
= divide_this
% divide_by
;
2388 /* Set condition codes. */
2389 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2391 if (overflow
) PSW
|= PSW_OV
;
2392 if (quotient
== 0) PSW
|= PSW_Z
;
2393 if (quotient
< 0) PSW
|= PSW_S
;
2395 trace_output (OP_REG_REG_REG
);
2400 /* mulu imm9, reg2, reg3 */
2404 trace_input ("mulu", OP_IMM_REG_REG
, 0);
2406 Multiply64 (0, (OP
[3] & 0x1f) | ((OP
[3] >> 13) & 0x1e0));
2408 trace_output (OP_IMM_REG_REG
);
2413 /* mul imm9, reg2, reg3 */
2417 trace_input ("mul", OP_IMM_REG_REG
, 0);
2419 Multiply64 (1, SEXT9 ((OP
[3] & 0x1f) | ((OP
[3] >> 13) & 0x1e0)));
2421 trace_output (OP_IMM_REG_REG
);
2432 trace_input ("ld.hu", OP_LOAD32
, 2);
2434 adr
= State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2] & ~1);
2437 State
.regs
[ OP
[1] ] = load_mem (adr
, 2);
2439 trace_output (OP_LOAD32
);
2451 trace_input ("ld.bu", OP_LOAD32
, 1);
2453 adr
= (State
.regs
[ OP
[0] ]
2454 + (EXTEND16 (OP
[2] & ~1) | ((OP
[3] >> 5) & 1)));
2456 State
.regs
[ OP
[1] ] = load_mem (adr
, 1);
2458 trace_output (OP_LOAD32
);
2463 /* prepare list12, imm5, imm32 */
2469 trace_input ("prepare", OP_PUSHPOP1
, 0);
2471 /* Store the registers with lower number registers being placed at higher addresses. */
2472 for (i
= 0; i
< 12; i
++)
2473 if ((OP
[3] & (1 << type1_regs
[ i
])))
2476 store_mem (SP
, 4, State
.regs
[ 20 + i
]);
2479 SP
-= (OP
[3] & 0x3e) << 1;
2481 EP
= load_mem (PC
+ 4, 4);
2483 trace_output (OP_PUSHPOP1
);
2488 /* prepare list12, imm5, imm16-32 */
2494 trace_input ("prepare", OP_PUSHPOP1
, 0);
2496 /* Store the registers with lower number registers being placed at higher addresses. */
2497 for (i
= 0; i
< 12; i
++)
2498 if ((OP
[3] & (1 << type1_regs
[ i
])))
2501 store_mem (SP
, 4, State
.regs
[ 20 + i
]);
2504 SP
-= (OP
[3] & 0x3e) << 1;
2506 EP
= load_mem (PC
+ 4, 2) << 16;
2508 trace_output (OP_PUSHPOP1
);
2513 /* prepare list12, imm5, imm16 */
2519 trace_input ("prepare", OP_PUSHPOP1
, 0);
2521 /* Store the registers with lower number registers being placed at higher addresses. */
2522 for (i
= 0; i
< 12; i
++)
2523 if ((OP
[3] & (1 << type1_regs
[ i
])))
2526 store_mem (SP
, 4, State
.regs
[ 20 + i
]);
2529 SP
-= (OP
[3] & 0x3e) << 1;
2531 EP
= EXTEND16 (load_mem (PC
+ 4, 2));
2533 trace_output (OP_PUSHPOP1
);
2538 /* prepare list12, imm5, sp */
2544 trace_input ("prepare", OP_PUSHPOP1
, 0);
2546 /* Store the registers with lower number registers being placed at higher addresses. */
2547 for (i
= 0; i
< 12; i
++)
2548 if ((OP
[3] & (1 << type1_regs
[ i
])))
2551 store_mem (SP
, 4, State
.regs
[ 20 + i
]);
2554 SP
-= (OP
[3] & 0x3e) << 1;
2558 trace_output (OP_PUSHPOP1
);
2563 /* mul reg1, reg2, reg3 */
2567 trace_input ("mul", OP_REG_REG_REG
, 0);
2569 Multiply64 (1, State
.regs
[ OP
[0] ]);
2571 trace_output (OP_REG_REG_REG
);
2582 trace_input ("popmh", OP_PUSHPOP2
, 0);
2584 if (OP
[3] & (1 << 19))
2586 if ((PSW
& PSW_NP
) && ((PSW
& PSW_EP
) == 0))
2588 FEPSW
= load_mem ( SP
& ~ 3, 4);
2589 FEPC
= load_mem ((SP
+ 4) & ~ 3, 4);
2593 EIPSW
= load_mem ( SP
& ~ 3, 4);
2594 EIPC
= load_mem ((SP
+ 4) & ~ 3, 4);
2600 /* Load the registers with lower number registers being retrieved from higher addresses. */
2602 if ((OP
[3] & (1 << type2_regs
[ i
])))
2604 State
.regs
[ i
+ 16 ] = load_mem (SP
& ~ 3, 4);
2608 trace_output (OP_PUSHPOP2
);
2619 trace_input ("popml", OP_PUSHPOP3
, 0);
2621 if (OP
[3] & (1 << 19))
2623 if ((PSW
& PSW_NP
) && ((PSW
& PSW_EP
) == 0))
2625 FEPSW
= load_mem ( SP
& ~ 3, 4);
2626 FEPC
= load_mem ((SP
+ 4) & ~ 3, 4);
2630 EIPSW
= load_mem ( SP
& ~ 3, 4);
2631 EIPC
= load_mem ((SP
+ 4) & ~ 3, 4);
2637 if (OP
[3] & (1 << 3))
2639 PSW
= load_mem (SP
& ~ 3, 4);
2643 /* Load the registers with lower number registers being retrieved from higher addresses. */
2645 if ((OP
[3] & (1 << type3_regs
[ i
])))
2647 State
.regs
[ i
+ 1 ] = load_mem (SP
& ~ 3, 4);
2651 trace_output (OP_PUSHPOP2
);
2662 trace_input ("pushmh", OP_PUSHPOP2
, 0);
2664 /* Store the registers with lower number registers being placed at higher addresses. */
2665 for (i
= 0; i
< 16; i
++)
2666 if ((OP
[3] & (1 << type2_regs
[ i
])))
2669 store_mem (SP
& ~ 3, 4, State
.regs
[ i
+ 16 ]);
2672 if (OP
[3] & (1 << 19))
2676 if ((PSW
& PSW_NP
) && ((PSW
& PSW_EP
) == 0))
2678 store_mem ((SP
+ 4) & ~ 3, 4, FEPC
);
2679 store_mem ( SP
& ~ 3, 4, FEPSW
);
2683 store_mem ((SP
+ 4) & ~ 3, 4, EIPC
);
2684 store_mem ( SP
& ~ 3, 4, EIPSW
);
2688 trace_output (OP_PUSHPOP2
);
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