27 #include "targ-vals.h"
29 #include "libiberty.h"
32 #if !defined(__GO32__) && !defined(_WIN32)
34 #include <sys/times.h>
38 /* This is an array of the bit positions of registers r20 .. r31 in
39 that order in a prepare/dispose instruction. */
40 int type1_regs
[12] = { 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 0, 21 };
41 /* This is an array of the bit positions of registers r16 .. r31 in
42 that order in a push/pop instruction. */
43 int type2_regs
[16] = { 3, 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
44 /* This is an array of the bit positions of registers r1 .. r15 in
45 that order in a push/pop instruction. */
46 int type3_regs
[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
49 #ifndef SIZE_INSTRUCTION
50 #define SIZE_INSTRUCTION 18
54 #define SIZE_VALUES 11
58 unsigned32 trace_values
[3];
61 const char *trace_name
;
66 trace_input (name
, type
, size
)
72 if (!TRACE_ALU_P (STATE_CPU (simulator
, 0)))
77 trace_module
= TRACE_ALU_IDX
;
90 trace_values
[0] = State
.regs
[OP
[0]];
97 trace_values
[0] = State
.regs
[OP
[1]];
98 trace_values
[1] = State
.regs
[OP
[0]];
104 trace_values
[0] = SEXT5 (OP
[0]);
105 trace_values
[1] = OP
[1];
106 trace_num_values
= 2;
109 case OP_IMM_REG_MOVE
:
110 trace_values
[0] = SEXT5 (OP
[0]);
111 trace_num_values
= 1;
115 trace_values
[0] = State
.pc
;
116 trace_values
[1] = SEXT9 (OP
[0]);
117 trace_values
[2] = PSW
;
118 trace_num_values
= 3;
122 trace_values
[0] = OP
[1] * size
;
123 trace_values
[1] = State
.regs
[30];
124 trace_num_values
= 2;
128 trace_values
[0] = State
.regs
[OP
[0]];
129 trace_values
[1] = OP
[1] * size
;
130 trace_values
[2] = State
.regs
[30];
131 trace_num_values
= 3;
135 trace_values
[0] = EXTEND16 (OP
[2]);
136 trace_values
[1] = State
.regs
[OP
[0]];
137 trace_num_values
= 2;
141 trace_values
[0] = State
.regs
[OP
[1]];
142 trace_values
[1] = EXTEND16 (OP
[2]);
143 trace_values
[2] = State
.regs
[OP
[0]];
144 trace_num_values
= 3;
148 trace_values
[0] = SEXT22 (OP
[0]);
149 trace_values
[1] = State
.pc
;
150 trace_num_values
= 2;
154 trace_values
[0] = EXTEND16 (OP
[0]) << size
;
155 trace_values
[1] = State
.regs
[OP
[1]];
156 trace_num_values
= 2;
159 case OP_IMM16_REG_REG
:
160 trace_values
[0] = EXTEND16 (OP
[2]) << size
;
161 trace_values
[1] = State
.regs
[OP
[1]];
162 trace_num_values
= 2;
165 case OP_UIMM_REG_REG
:
166 trace_values
[0] = (OP
[0] & 0xffff) << size
;
167 trace_values
[1] = State
.regs
[OP
[1]];
168 trace_num_values
= 2;
171 case OP_UIMM16_REG_REG
:
172 trace_values
[0] = (OP
[2]) << size
;
173 trace_values
[1] = State
.regs
[OP
[1]];
174 trace_num_values
= 2;
178 trace_num_values
= 0;
182 trace_values
[0] = PSW
;
183 trace_num_values
= 1;
187 trace_num_values
= 0;
191 trace_values
[0] = State
.regs
[OP
[0]];
192 trace_num_values
= 1;
196 trace_values
[0] = State
.sregs
[OP
[1]];
197 trace_num_values
= 1;
203 trace_result (int has_result
, unsigned32 result
)
211 /* write out the values saved during the trace_input call */
214 for (i
= 0; i
< trace_num_values
; i
++)
216 sprintf (chp
, "%*s0x%.8lx", SIZE_VALUES
- 10, "",
217 (long) trace_values
[i
]);
218 chp
= strchr (chp
, '\0');
222 sprintf (chp
, "%*s", SIZE_VALUES
, "");
223 chp
= strchr (chp
, '\0');
227 /* append any result to the end of the buffer */
229 sprintf (chp
, " :: 0x%.8lx", (unsigned long)result
);
231 trace_generic (simulator
, STATE_CPU (simulator
, 0), trace_module
, buf
);
235 trace_output (result
)
236 enum op_types result
;
238 if (!TRACE_ALU_P (STATE_CPU (simulator
, 0)))
260 trace_result (1, State
.regs
[OP
[0]]);
264 case OP_REG_REG_MOVE
:
266 case OP_IMM_REG_MOVE
:
269 trace_result (1, State
.regs
[OP
[1]]);
273 case OP_UIMM_REG_REG
:
274 case OP_IMM16_REG_REG
:
275 case OP_UIMM16_REG_REG
:
276 trace_result (1, State
.regs
[OP
[1]]);
281 trace_result (1, State
.regs
[OP
[1]]);
287 trace_result (1, State
.sregs
[OP
[1]]);
294 /* Returns 1 if the specific condition is met, returns 0 otherwise. */
296 condition_met (unsigned code
)
298 unsigned int psw
= PSW
;
302 case 0x0: return ((psw
& PSW_OV
) != 0);
303 case 0x1: return ((psw
& PSW_CY
) != 0);
304 case 0x2: return ((psw
& PSW_Z
) != 0);
305 case 0x3: return ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) != 0);
306 case 0x4: return ((psw
& PSW_S
) != 0);
307 /*case 0x5: return 1;*/
308 case 0x6: return ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) != 0);
309 case 0x7: return (((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) || ((psw
& PSW_Z
) != 0)) != 0);
310 case 0x8: return ((psw
& PSW_OV
) == 0);
311 case 0x9: return ((psw
& PSW_CY
) == 0);
312 case 0xa: return ((psw
& PSW_Z
) == 0);
313 case 0xb: return ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) == 0);
314 case 0xc: return ((psw
& PSW_S
) == 0);
315 case 0xd: return ((psw
& PSW_SAT
) != 0);
316 case 0xe: return ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) == 0);
317 case 0xf: return (((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) || ((psw
& PSW_Z
) != 0)) == 0);
324 Add32 (unsigned long a1
, unsigned long a2
, int * carry
)
326 unsigned long result
= (a1
+ a2
);
328 * carry
= (result
< a1
);
334 Multiply64 (int sign
, unsigned long op0
)
345 op1
= State
.regs
[ OP
[1] ];
349 /* Compute sign of result and adjust operands if necessary. */
351 sign
= (op0
^ op1
) & 0x80000000;
353 if (((signed long) op0
) < 0)
356 if (((signed long) op1
) < 0)
360 /* We can split the 32x32 into four 16x16 operations. This ensures
361 that we do not lose precision on 32bit only hosts: */
362 lo
= ( (op0
& 0xFFFF) * (op1
& 0xFFFF));
363 mid1
= ( (op0
& 0xFFFF) * ((op1
>> 16) & 0xFFFF));
364 mid2
= (((op0
>> 16) & 0xFFFF) * (op1
& 0xFFFF));
365 hi
= (((op0
>> 16) & 0xFFFF) * ((op1
>> 16) & 0xFFFF));
367 /* We now need to add all of these results together, taking care
368 to propogate the carries from the additions: */
369 RdLo
= Add32 (lo
, (mid1
<< 16), & carry
);
371 RdLo
= Add32 (RdLo
, (mid2
<< 16), & carry
);
372 RdHi
+= (carry
+ ((mid1
>> 16) & 0xFFFF) + ((mid2
>> 16) & 0xFFFF) + hi
);
376 /* Negate result if necessary. */
380 if (RdLo
== 0xFFFFFFFF)
389 /* Don't store into register 0. */
391 State
.regs
[ OP
[1] ] = RdLo
;
393 State
.regs
[ OP
[2] >> 11 ] = RdHi
;
399 /* Read a null terminated string from memory, return in a buffer */
407 while (sim_core_read_1 (STATE_CPU (sd
, 0),
408 PC
, read_map
, addr
+ nr
) != 0)
410 buf
= NZALLOC (char, nr
+ 1);
411 sim_read (simulator
, addr
, buf
, nr
);
415 /* Read a null terminated argument vector from memory, return in a
418 fetch_argv (sd
, addr
)
424 char **buf
= xmalloc (max_nr
* sizeof (char*));
427 unsigned32 a
= sim_core_read_4 (STATE_CPU (sd
, 0),
428 PC
, read_map
, addr
+ nr
* 4);
430 buf
[nr
] = fetch_str (sd
, a
);
432 if (nr
== max_nr
- 1)
435 buf
= xrealloc (buf
, max_nr
* sizeof (char*));
447 trace_input ("sst.b", OP_STORE16
, 1);
449 store_mem (State
.regs
[30] + (OP
[3] & 0x7f), 1, State
.regs
[ OP
[1] ]);
451 trace_output (OP_STORE16
);
460 trace_input ("sst.h", OP_STORE16
, 2);
462 store_mem (State
.regs
[30] + ((OP
[3] & 0x7f) << 1), 2, State
.regs
[ OP
[1] ]);
464 trace_output (OP_STORE16
);
473 trace_input ("sst.w", OP_STORE16
, 4);
475 store_mem (State
.regs
[30] + ((OP
[3] & 0x7e) << 1), 4, State
.regs
[ OP
[1] ]);
477 trace_output (OP_STORE16
);
488 trace_input ("ld.b", OP_LOAD32
, 1);
490 adr
= State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2]);
492 State
.regs
[ OP
[1] ] = EXTEND8 (load_mem (adr
, 1));
494 trace_output (OP_LOAD32
);
505 trace_input ("ld.h", OP_LOAD32
, 2);
507 adr
= State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2]);
510 State
.regs
[ OP
[1] ] = EXTEND16 (load_mem (adr
, 2));
512 trace_output (OP_LOAD32
);
523 trace_input ("ld.w", OP_LOAD32
, 4);
525 adr
= State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2] & ~1);
528 State
.regs
[ OP
[1] ] = load_mem (adr
, 4);
530 trace_output (OP_LOAD32
);
539 trace_input ("st.b", OP_STORE32
, 1);
541 store_mem (State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2]), 1, State
.regs
[ OP
[1] ]);
543 trace_output (OP_STORE32
);
554 trace_input ("st.h", OP_STORE32
, 2);
556 adr
= State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2]);
559 store_mem (adr
, 2, State
.regs
[ OP
[1] ]);
561 trace_output (OP_STORE32
);
572 trace_input ("st.w", OP_STORE32
, 4);
574 adr
= State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2] & ~1);
577 store_mem (adr
, 4, State
.regs
[ OP
[1] ]);
579 trace_output (OP_STORE32
);
588 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
590 trace_input ("add", OP_REG_REG
, 0);
592 /* Compute the result. */
594 op0
= State
.regs
[ OP
[0] ];
595 op1
= State
.regs
[ OP
[1] ];
599 /* Compute the condition codes. */
601 s
= (result
& 0x80000000);
602 cy
= (result
< op0
|| result
< op1
);
603 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
604 && (op0
& 0x80000000) != (result
& 0x80000000));
606 /* Store the result and condition codes. */
607 State
.regs
[OP
[1]] = result
;
608 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
609 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
610 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
611 trace_output (OP_REG_REG
);
616 /* add sign_extend(imm5), reg */
620 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
623 trace_input ("add", OP_IMM_REG
, 0);
625 /* Compute the result. */
626 temp
= SEXT5 (OP
[0]);
628 op1
= State
.regs
[OP
[1]];
631 /* Compute the condition codes. */
633 s
= (result
& 0x80000000);
634 cy
= (result
< op0
|| result
< op1
);
635 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
636 && (op0
& 0x80000000) != (result
& 0x80000000));
638 /* Store the result and condition codes. */
639 State
.regs
[OP
[1]] = result
;
640 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
641 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
642 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
643 trace_output (OP_IMM_REG
);
648 /* addi sign_extend(imm16), reg, reg */
652 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
654 trace_input ("addi", OP_IMM16_REG_REG
, 0);
656 /* Compute the result. */
658 op0
= EXTEND16 (OP
[2]);
659 op1
= State
.regs
[ OP
[0] ];
662 /* Compute the condition codes. */
664 s
= (result
& 0x80000000);
665 cy
= (result
< op0
|| result
< op1
);
666 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
667 && (op0
& 0x80000000) != (result
& 0x80000000));
669 /* Store the result and condition codes. */
670 State
.regs
[OP
[1]] = result
;
671 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
672 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
673 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
674 trace_output (OP_IMM16_REG_REG
);
683 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
685 trace_input ("sub", OP_REG_REG
, 0);
686 /* Compute the result. */
687 op0
= State
.regs
[ OP
[0] ];
688 op1
= State
.regs
[ OP
[1] ];
691 /* Compute the condition codes. */
693 s
= (result
& 0x80000000);
695 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
696 && (op1
& 0x80000000) != (result
& 0x80000000));
698 /* Store the result and condition codes. */
699 State
.regs
[OP
[1]] = result
;
700 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
701 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
702 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
703 trace_output (OP_REG_REG
);
708 /* subr reg1, reg2 */
712 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
714 trace_input ("subr", OP_REG_REG
, 0);
715 /* Compute the result. */
716 op0
= State
.regs
[ OP
[0] ];
717 op1
= State
.regs
[ OP
[1] ];
720 /* Compute the condition codes. */
722 s
= (result
& 0x80000000);
724 ov
= ((op0
& 0x80000000) != (op1
& 0x80000000)
725 && (op0
& 0x80000000) != (result
& 0x80000000));
727 /* Store the result and condition codes. */
728 State
.regs
[OP
[1]] = result
;
729 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
730 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
731 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
732 trace_output (OP_REG_REG
);
741 trace_input ("mulh", OP_REG_REG
, 0);
743 State
.regs
[ OP
[1] ] = (EXTEND16 (State
.regs
[ OP
[1] ]) * EXTEND16 (State
.regs
[ OP
[0] ]));
745 trace_output (OP_REG_REG
);
750 /* mulh sign_extend(imm5), reg2 */
754 trace_input ("mulh", OP_IMM_REG
, 0);
756 State
.regs
[ OP
[1] ] = EXTEND16 (State
.regs
[ OP
[1] ]) * SEXT5 (OP
[0]);
758 trace_output (OP_IMM_REG
);
763 /* mulhi imm16, reg1, reg2 */
767 trace_input ("mulhi", OP_IMM16_REG_REG
, 0);
769 State
.regs
[ OP
[1] ] = EXTEND16 (State
.regs
[ OP
[0] ]) * EXTEND16 (OP
[2]);
771 trace_output (OP_IMM16_REG_REG
);
780 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
782 trace_input ("cmp", OP_REG_REG_CMP
, 0);
783 /* Compute the result. */
784 op0
= State
.regs
[ OP
[0] ];
785 op1
= State
.regs
[ OP
[1] ];
788 /* Compute the condition codes. */
790 s
= (result
& 0x80000000);
792 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
793 && (op1
& 0x80000000) != (result
& 0x80000000));
795 /* Set condition codes. */
796 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
797 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
798 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
799 trace_output (OP_REG_REG_CMP
);
804 /* cmp sign_extend(imm5), reg */
808 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
811 /* Compute the result. */
812 trace_input ("cmp", OP_IMM_REG_CMP
, 0);
813 temp
= SEXT5 (OP
[0]);
815 op1
= State
.regs
[OP
[1]];
818 /* Compute the condition codes. */
820 s
= (result
& 0x80000000);
822 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
823 && (op1
& 0x80000000) != (result
& 0x80000000));
825 /* Set condition codes. */
826 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
827 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
828 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
829 trace_output (OP_IMM_REG_CMP
);
838 trace_input ("setf", OP_EX1
, 0);
840 State
.regs
[ OP
[1] ] = condition_met (OP
[0]);
842 trace_output (OP_EX1
);
851 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
853 trace_input ("satadd", OP_REG_REG
, 0);
854 /* Compute the result. */
855 op0
= State
.regs
[ OP
[0] ];
856 op1
= State
.regs
[ OP
[1] ];
859 /* Compute the condition codes. */
861 s
= (result
& 0x80000000);
862 cy
= (result
< op0
|| result
< op1
);
863 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
864 && (op0
& 0x80000000) != (result
& 0x80000000));
867 /* Handle saturated results. */
870 /* An overflow that results in a negative result implies that we
871 became too positive. */
877 /* Any other overflow must have thus been too negative. */
883 /* Store the result and condition codes. */
884 State
.regs
[OP
[1]] = result
;
885 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
886 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
887 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
888 | (sat
? PSW_SAT
: 0));
890 trace_output (OP_REG_REG
);
895 /* satadd sign_extend(imm5), reg */
899 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
903 trace_input ("satadd", OP_IMM_REG
, 0);
905 /* Compute the result. */
906 temp
= SEXT5 (OP
[0]);
908 op1
= State
.regs
[OP
[1]];
911 /* Compute the condition codes. */
913 s
= (result
& 0x80000000);
914 cy
= (result
< op0
|| result
< op1
);
915 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
916 && (op0
& 0x80000000) != (result
& 0x80000000));
919 /* Handle saturated results. */
922 /* An overflow that results in a negative result implies that we
923 became too positive. */
929 /* Any other overflow must have thus been too negative. */
935 /* Store the result and condition codes. */
936 State
.regs
[OP
[1]] = result
;
937 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
938 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
939 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
940 | (sat
? PSW_SAT
: 0));
941 trace_output (OP_IMM_REG
);
946 /* satsub reg1, reg2 */
950 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
952 trace_input ("satsub", OP_REG_REG
, 0);
954 /* Compute the result. */
955 op0
= State
.regs
[ OP
[0] ];
956 op1
= State
.regs
[ OP
[1] ];
959 /* Compute the condition codes. */
961 s
= (result
& 0x80000000);
963 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
964 && (op1
& 0x80000000) != (result
& 0x80000000));
967 /* Handle saturated results. */
970 /* An overflow that results in a negative result implies that we
971 became too positive. */
977 /* Any other overflow must have thus been too negative. */
983 /* Store the result and condition codes. */
984 State
.regs
[OP
[1]] = result
;
985 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
986 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
987 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
988 | (sat
? PSW_SAT
: 0));
990 trace_output (OP_REG_REG
);
994 /* satsubi sign_extend(imm16), reg */
998 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1001 trace_input ("satsubi", OP_IMM_REG
, 0);
1003 /* Compute the result. */
1004 temp
= EXTEND16 (OP
[2]);
1006 op1
= State
.regs
[ OP
[0] ];
1009 /* Compute the condition codes. */
1011 s
= (result
& 0x80000000);
1013 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1014 && (op1
& 0x80000000) != (result
& 0x80000000));
1017 /* Handle saturated results. */
1020 /* An overflow that results in a negative result implies that we
1021 became too positive. */
1022 result
= 0x7fffffff;
1027 /* Any other overflow must have thus been too negative. */
1028 result
= 0x80000000;
1033 /* Store the result and condition codes. */
1034 State
.regs
[OP
[1]] = result
;
1035 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1036 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1037 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1038 | (sat
? PSW_SAT
: 0));
1040 trace_output (OP_IMM_REG
);
1045 /* satsubr reg,reg */
1049 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1051 trace_input ("satsubr", OP_REG_REG
, 0);
1053 /* Compute the result. */
1054 op0
= State
.regs
[ OP
[0] ];
1055 op1
= State
.regs
[ OP
[1] ];
1058 /* Compute the condition codes. */
1060 s
= (result
& 0x80000000);
1062 ov
= ((op0
& 0x80000000) != (op1
& 0x80000000)
1063 && (op0
& 0x80000000) != (result
& 0x80000000));
1066 /* Handle saturated results. */
1069 /* An overflow that results in a negative result implies that we
1070 became too positive. */
1071 result
= 0x7fffffff;
1076 /* Any other overflow must have thus been too negative. */
1077 result
= 0x80000000;
1082 /* Store the result and condition codes. */
1083 State
.regs
[OP
[1]] = result
;
1084 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1085 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1086 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1087 | (sat
? PSW_SAT
: 0));
1089 trace_output (OP_REG_REG
);
1098 unsigned int op0
, op1
, result
, z
, s
;
1100 trace_input ("tst", OP_REG_REG_CMP
, 0);
1102 /* Compute the result. */
1103 op0
= State
.regs
[ OP
[0] ];
1104 op1
= State
.regs
[ OP
[1] ];
1107 /* Compute the condition codes. */
1109 s
= (result
& 0x80000000);
1111 /* Store the condition codes. */
1112 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1113 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1114 trace_output (OP_REG_REG_CMP
);
1119 /* mov sign_extend(imm5), reg */
1123 int value
= SEXT5 (OP
[0]);
1125 trace_input ("mov", OP_IMM_REG_MOVE
, 0);
1127 State
.regs
[ OP
[1] ] = value
;
1129 trace_output (OP_IMM_REG_MOVE
);
1134 /* movhi imm16, reg, reg */
1138 trace_input ("movhi", OP_UIMM16_REG_REG
, 16);
1140 State
.regs
[ OP
[1] ] = State
.regs
[ OP
[0] ] + (OP
[2] << 16);
1142 trace_output (OP_UIMM16_REG_REG
);
1147 /* sar zero_extend(imm5),reg1 */
1151 unsigned int op0
, op1
, result
, z
, s
, cy
;
1153 trace_input ("sar", OP_IMM_REG
, 0);
1155 op1
= State
.regs
[ OP
[1] ];
1156 result
= (signed)op1
>> op0
;
1158 /* Compute the condition codes. */
1160 s
= (result
& 0x80000000);
1161 cy
= op0
? (op1
& (1 << (op0
- 1))) : 0;
1163 /* Store the result and condition codes. */
1164 State
.regs
[ OP
[1] ] = result
;
1165 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1166 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1167 | (cy
? PSW_CY
: 0));
1168 trace_output (OP_IMM_REG
);
1173 /* sar reg1, reg2 */
1177 unsigned int op0
, op1
, result
, z
, s
, cy
;
1179 trace_input ("sar", OP_REG_REG
, 0);
1181 op0
= State
.regs
[ OP
[0] ] & 0x1f;
1182 op1
= State
.regs
[ OP
[1] ];
1183 result
= (signed)op1
>> op0
;
1185 /* Compute the condition codes. */
1187 s
= (result
& 0x80000000);
1188 cy
= op0
? (op1
& (1 << (op0
- 1))) : 0;
1190 /* Store the result and condition codes. */
1191 State
.regs
[OP
[1]] = result
;
1192 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1193 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1194 | (cy
? PSW_CY
: 0));
1195 trace_output (OP_REG_REG
);
1200 /* shl zero_extend(imm5),reg1 */
1204 unsigned int op0
, op1
, result
, z
, s
, cy
;
1206 trace_input ("shl", OP_IMM_REG
, 0);
1208 op1
= State
.regs
[ OP
[1] ];
1209 result
= op1
<< op0
;
1211 /* Compute the condition codes. */
1213 s
= (result
& 0x80000000);
1214 cy
= op0
? (op1
& (1 << (32 - op0
))) : 0;
1216 /* Store the result and condition codes. */
1217 State
.regs
[OP
[1]] = result
;
1218 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1219 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1220 | (cy
? PSW_CY
: 0));
1221 trace_output (OP_IMM_REG
);
1226 /* shl reg1, reg2 */
1230 unsigned int op0
, op1
, result
, z
, s
, cy
;
1232 trace_input ("shl", OP_REG_REG
, 0);
1233 op0
= State
.regs
[ OP
[0] ] & 0x1f;
1234 op1
= State
.regs
[ OP
[1] ];
1235 result
= op1
<< op0
;
1237 /* Compute the condition codes. */
1239 s
= (result
& 0x80000000);
1240 cy
= op0
? (op1
& (1 << (32 - op0
))) : 0;
1242 /* Store the result and condition codes. */
1243 State
.regs
[OP
[1]] = result
;
1244 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1245 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1246 | (cy
? PSW_CY
: 0));
1247 trace_output (OP_REG_REG
);
1252 /* shr zero_extend(imm5),reg1 */
1256 unsigned int op0
, op1
, result
, z
, s
, cy
;
1258 trace_input ("shr", OP_IMM_REG
, 0);
1260 op1
= State
.regs
[ OP
[1] ];
1261 result
= op1
>> op0
;
1263 /* Compute the condition codes. */
1265 s
= (result
& 0x80000000);
1266 cy
= op0
? (op1
& (1 << (op0
- 1))) : 0;
1268 /* Store the result and condition codes. */
1269 State
.regs
[OP
[1]] = result
;
1270 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1271 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1272 | (cy
? PSW_CY
: 0));
1273 trace_output (OP_IMM_REG
);
1278 /* shr reg1, reg2 */
1282 unsigned int op0
, op1
, result
, z
, s
, cy
;
1284 trace_input ("shr", OP_REG_REG
, 0);
1285 op0
= State
.regs
[ OP
[0] ] & 0x1f;
1286 op1
= State
.regs
[ OP
[1] ];
1287 result
= op1
>> op0
;
1289 /* Compute the condition codes. */
1291 s
= (result
& 0x80000000);
1292 cy
= op0
? (op1
& (1 << (op0
- 1))) : 0;
1294 /* Store the result and condition codes. */
1295 State
.regs
[OP
[1]] = result
;
1296 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1297 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1298 | (cy
? PSW_CY
: 0));
1299 trace_output (OP_REG_REG
);
1308 unsigned int op0
, op1
, result
, z
, s
;
1310 trace_input ("or", OP_REG_REG
, 0);
1312 /* Compute the result. */
1313 op0
= State
.regs
[ OP
[0] ];
1314 op1
= State
.regs
[ OP
[1] ];
1317 /* Compute the condition codes. */
1319 s
= (result
& 0x80000000);
1321 /* Store the result and condition codes. */
1322 State
.regs
[OP
[1]] = result
;
1323 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1324 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1325 trace_output (OP_REG_REG
);
1330 /* ori zero_extend(imm16), reg, reg */
1334 unsigned int op0
, op1
, result
, z
, s
;
1336 trace_input ("ori", OP_UIMM16_REG_REG
, 0);
1338 op1
= State
.regs
[ OP
[0] ];
1341 /* Compute the condition codes. */
1343 s
= (result
& 0x80000000);
1345 /* Store the result and condition codes. */
1346 State
.regs
[OP
[1]] = result
;
1347 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1348 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1349 trace_output (OP_UIMM16_REG_REG
);
1358 unsigned int op0
, op1
, result
, z
, s
;
1360 trace_input ("and", OP_REG_REG
, 0);
1362 /* Compute the result. */
1363 op0
= State
.regs
[ OP
[0] ];
1364 op1
= State
.regs
[ OP
[1] ];
1367 /* Compute the condition codes. */
1369 s
= (result
& 0x80000000);
1371 /* Store the result and condition codes. */
1372 State
.regs
[OP
[1]] = result
;
1373 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1374 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1375 trace_output (OP_REG_REG
);
1380 /* andi zero_extend(imm16), reg, reg */
1384 unsigned int result
, z
;
1386 trace_input ("andi", OP_UIMM16_REG_REG
, 0);
1388 result
= OP
[2] & State
.regs
[ OP
[0] ];
1390 /* Compute the condition codes. */
1393 /* Store the result and condition codes. */
1394 State
.regs
[ OP
[1] ] = result
;
1396 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1397 PSW
|= (z
? PSW_Z
: 0);
1399 trace_output (OP_UIMM16_REG_REG
);
1408 unsigned int op0
, op1
, result
, z
, s
;
1410 trace_input ("xor", OP_REG_REG
, 0);
1412 /* Compute the result. */
1413 op0
= State
.regs
[ OP
[0] ];
1414 op1
= State
.regs
[ OP
[1] ];
1417 /* Compute the condition codes. */
1419 s
= (result
& 0x80000000);
1421 /* Store the result and condition codes. */
1422 State
.regs
[OP
[1]] = result
;
1423 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1424 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1425 trace_output (OP_REG_REG
);
1430 /* xori zero_extend(imm16), reg, reg */
1434 unsigned int op0
, op1
, result
, z
, s
;
1436 trace_input ("xori", OP_UIMM16_REG_REG
, 0);
1438 op1
= State
.regs
[ OP
[0] ];
1441 /* Compute the condition codes. */
1443 s
= (result
& 0x80000000);
1445 /* Store the result and condition codes. */
1446 State
.regs
[OP
[1]] = result
;
1447 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1448 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1449 trace_output (OP_UIMM16_REG_REG
);
1454 /* not reg1, reg2 */
1458 unsigned int op0
, result
, z
, s
;
1460 trace_input ("not", OP_REG_REG_MOVE
, 0);
1461 /* Compute the result. */
1462 op0
= State
.regs
[ OP
[0] ];
1465 /* Compute the condition codes. */
1467 s
= (result
& 0x80000000);
1469 /* Store the result and condition codes. */
1470 State
.regs
[OP
[1]] = result
;
1471 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1472 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1473 trace_output (OP_REG_REG_MOVE
);
1482 unsigned int op0
, op1
, op2
;
1485 trace_input ("set1", OP_BIT
, 0);
1486 op0
= State
.regs
[ OP
[0] ];
1488 temp
= EXTEND16 (OP
[2]);
1490 temp
= load_mem (op0
+ op2
, 1);
1492 if ((temp
& (1 << op1
)) == 0)
1495 store_mem (op0
+ op2
, 1, temp
);
1496 trace_output (OP_BIT
);
1505 unsigned int op0
, op1
, op2
;
1508 trace_input ("not1", OP_BIT
, 0);
1509 op0
= State
.regs
[ OP
[0] ];
1511 temp
= EXTEND16 (OP
[2]);
1513 temp
= load_mem (op0
+ op2
, 1);
1515 if ((temp
& (1 << op1
)) == 0)
1518 store_mem (op0
+ op2
, 1, temp
);
1519 trace_output (OP_BIT
);
1528 unsigned int op0
, op1
, op2
;
1531 trace_input ("clr1", OP_BIT
, 0);
1532 op0
= State
.regs
[ OP
[0] ];
1534 temp
= EXTEND16 (OP
[2]);
1536 temp
= load_mem (op0
+ op2
, 1);
1538 if ((temp
& (1 << op1
)) == 0)
1540 temp
&= ~(1 << op1
);
1541 store_mem (op0
+ op2
, 1, temp
);
1542 trace_output (OP_BIT
);
1551 unsigned int op0
, op1
, op2
;
1554 trace_input ("tst1", OP_BIT
, 0);
1555 op0
= State
.regs
[ OP
[0] ];
1557 temp
= EXTEND16 (OP
[2]);
1559 temp
= load_mem (op0
+ op2
, 1);
1561 if ((temp
& (1 << op1
)) == 0)
1563 trace_output (OP_BIT
);
1572 trace_input ("di", OP_NONE
, 0);
1574 trace_output (OP_NONE
);
1583 trace_input ("ei", OP_NONE
, 0);
1585 trace_output (OP_NONE
);
1594 trace_input ("halt", OP_NONE
, 0);
1595 /* FIXME this should put processor into a mode where NMI still handled */
1596 trace_output (OP_NONE
);
1597 sim_engine_halt (simulator
, STATE_CPU (simulator
, 0), NULL
, PC
,
1598 sim_stopped
, SIM_SIGTRAP
);
1606 trace_input ("trap", OP_TRAP
, 0);
1607 trace_output (OP_TRAP
);
1609 /* Trap 31 is used for simulating OS I/O functions */
1613 int save_errno
= errno
;
1616 /* Registers passed to trap 0 */
1618 #define FUNC State.regs[6] /* function number, return value */
1619 #define PARM1 State.regs[7] /* optional parm 1 */
1620 #define PARM2 State.regs[8] /* optional parm 2 */
1621 #define PARM3 State.regs[9] /* optional parm 3 */
1623 /* Registers set by trap 0 */
1625 #define RETVAL State.regs[10] /* return value */
1626 #define RETERR State.regs[11] /* return error code */
1628 /* Turn a pointer in a register into a pointer into real memory. */
1630 #define MEMPTR(x) (map (x))
1636 #ifdef TARGET_SYS_fork
1637 case TARGET_SYS_fork
:
1644 #ifdef TARGET_SYS_execv
1645 case TARGET_SYS_execve
:
1647 char *path
= fetch_str (simulator
, PARM1
);
1648 char **argv
= fetch_argv (simulator
, PARM2
);
1649 char **envp
= fetch_argv (simulator
, PARM3
);
1650 RETVAL
= execve (path
, argv
, envp
);
1660 #ifdef TARGET_SYS_execv
1661 case TARGET_SYS_execv
:
1663 char *path
= fetch_str (simulator
, PARM1
);
1664 char **argv
= fetch_argv (simulator
, PARM2
);
1665 RETVAL
= execv (path
, argv
);
1674 #ifdef TARGET_SYS_pipe
1675 case TARGET_SYS_pipe
:
1681 RETVAL
= pipe (host_fd
);
1682 SW (buf
, host_fd
[0]);
1683 buf
+= sizeof(uint16
);
1684 SW (buf
, host_fd
[1]);
1691 #ifdef TARGET_SYS_wait
1692 case TARGET_SYS_wait
:
1696 RETVAL
= wait (&status
);
1703 #ifdef TARGET_SYS_read
1704 case TARGET_SYS_read
:
1706 char *buf
= zalloc (PARM3
);
1707 RETVAL
= sim_io_read (simulator
, PARM1
, buf
, PARM3
);
1708 sim_write (simulator
, PARM2
, buf
, PARM3
);
1714 #ifdef TARGET_SYS_write
1715 case TARGET_SYS_write
:
1717 char *buf
= zalloc (PARM3
);
1718 sim_read (simulator
, PARM2
, buf
, PARM3
);
1720 RETVAL
= sim_io_write_stdout (simulator
, buf
, PARM3
);
1722 RETVAL
= sim_io_write (simulator
, PARM1
, buf
, PARM3
);
1728 #ifdef TARGET_SYS_lseek
1729 case TARGET_SYS_lseek
:
1730 RETVAL
= sim_io_lseek (simulator
, PARM1
, PARM2
, PARM3
);
1734 #ifdef TARGET_SYS_close
1735 case TARGET_SYS_close
:
1736 RETVAL
= sim_io_close (simulator
, PARM1
);
1740 #ifdef TARGET_SYS_open
1741 case TARGET_SYS_open
:
1743 char *buf
= fetch_str (simulator
, PARM1
);
1744 RETVAL
= sim_io_open (simulator
, buf
, PARM2
);
1750 #ifdef TARGET_SYS_exit
1751 case TARGET_SYS_exit
:
1752 if ((PARM1
& 0xffff0000) == 0xdead0000 && (PARM1
& 0xffff) != 0)
1753 /* get signal encoded by kill */
1754 sim_engine_halt (simulator
, STATE_CPU (simulator
, 0), NULL
, PC
,
1755 sim_signalled
, PARM1
& 0xffff);
1756 else if (PARM1
== 0xdead)
1758 sim_engine_halt (simulator
, STATE_CPU (simulator
, 0), NULL
, PC
,
1759 sim_stopped
, SIM_SIGABRT
);
1761 /* PARM1 has exit status */
1762 sim_engine_halt (simulator
, STATE_CPU (simulator
, 0), NULL
, PC
,
1767 #if !defined(__GO32__) && !defined(_WIN32)
1768 #ifdef TARGET_SYS_stat
1769 case TARGET_SYS_stat
: /* added at hmsi */
1770 /* stat system call */
1772 struct stat host_stat
;
1774 char *path
= fetch_str (simulator
, PARM1
);
1776 RETVAL
= stat (path
, &host_stat
);
1781 /* Just wild-assed guesses. */
1782 store_mem (buf
, 2, host_stat
.st_dev
);
1783 store_mem (buf
+ 2, 2, host_stat
.st_ino
);
1784 store_mem (buf
+ 4, 4, host_stat
.st_mode
);
1785 store_mem (buf
+ 8, 2, host_stat
.st_nlink
);
1786 store_mem (buf
+ 10, 2, host_stat
.st_uid
);
1787 store_mem (buf
+ 12, 2, host_stat
.st_gid
);
1788 store_mem (buf
+ 14, 2, host_stat
.st_rdev
);
1789 store_mem (buf
+ 16, 4, host_stat
.st_size
);
1790 store_mem (buf
+ 20, 4, host_stat
.st_atime
);
1791 store_mem (buf
+ 28, 4, host_stat
.st_mtime
);
1792 store_mem (buf
+ 36, 4, host_stat
.st_ctime
);
1799 #ifdef TARGET_SYS_chown
1800 case TARGET_SYS_chown
:
1802 char *path
= fetch_str (simulator
, PARM1
);
1803 RETVAL
= chown (path
, PARM2
, PARM3
);
1811 #ifdef TARGET_SYS_chmod
1812 case TARGET_SYS_chmod
:
1814 char *path
= fetch_str (simulator
, PARM1
);
1815 RETVAL
= chmod (path
, PARM2
);
1822 #ifdef TARGET_SYS_time
1824 case TARGET_SYS_time
:
1827 RETVAL
= time (&now
);
1828 store_mem (PARM1
, 4, now
);
1834 #if !defined(__GO32__) && !defined(_WIN32)
1835 #ifdef TARGET_SYS_times
1836 case TARGET_SYS_times
:
1839 RETVAL
= times (&tms
);
1840 store_mem (PARM1
, 4, tms
.tms_utime
);
1841 store_mem (PARM1
+ 4, 4, tms
.tms_stime
);
1842 store_mem (PARM1
+ 8, 4, tms
.tms_cutime
);
1843 store_mem (PARM1
+ 12, 4, tms
.tms_cstime
);
1849 #ifdef TARGET_SYS_gettimeofday
1850 #if !defined(__GO32__) && !defined(_WIN32)
1851 case TARGET_SYS_gettimeofday
:
1855 RETVAL
= gettimeofday (&t
, &tz
);
1856 store_mem (PARM1
, 4, t
.tv_sec
);
1857 store_mem (PARM1
+ 4, 4, t
.tv_usec
);
1858 store_mem (PARM2
, 4, tz
.tz_minuteswest
);
1859 store_mem (PARM2
+ 4, 4, tz
.tz_dsttime
);
1865 #ifdef TARGET_SYS_utime
1867 case TARGET_SYS_utime
:
1869 /* Cast the second argument to void *, to avoid type mismatch
1870 if a prototype is present. */
1871 sim_io_error (simulator
, "Utime not supported");
1872 /* RETVAL = utime (path, (void *) MEMPTR (PARM2)); */
1887 { /* Trap 0 -> 30 */
1892 ECR
|= 0x40 + OP
[0];
1893 /* Flag that we are now doing exception processing. */
1894 PSW
|= PSW_EP
| PSW_ID
;
1895 PC
= (OP
[0] < 0x10) ? 0x40 : 0x50;
1901 /* tst1 reg2, [reg1] */
1907 trace_input ("tst1", OP_BIT
, 1);
1909 temp
= load_mem (State
.regs
[ OP
[0] ], 1);
1912 if ((temp
& (1 << (State
.regs
[ OP
[1] ] & 0x7))) == 0)
1915 trace_output (OP_BIT
);
1920 /* mulu reg1, reg2, reg3 */
1924 trace_input ("mulu", OP_REG_REG_REG
, 0);
1926 Multiply64 (0, State
.regs
[ OP
[0] ]);
1928 trace_output (OP_REG_REG_REG
);
1933 #define BIT_CHANGE_OP( name, binop ) \
1935 unsigned int temp; \
1937 trace_input (name, OP_BIT_CHANGE, 0); \
1939 bit = 1 << (State.regs[ OP[1] ] & 0x7); \
1940 temp = load_mem (State.regs[ OP[0] ], 1); \
1943 if ((temp & bit) == 0) \
1947 store_mem (State.regs[ OP[0] ], 1, temp); \
1949 trace_output (OP_BIT_CHANGE); \
1953 /* clr1 reg2, [reg1] */
1957 BIT_CHANGE_OP ("clr1", &= ~ );
1960 /* not1 reg2, [reg1] */
1964 BIT_CHANGE_OP ("not1", ^= );
1971 BIT_CHANGE_OP ("set1", |= );
1978 trace_input ("sasf", OP_EX1
, 0);
1980 State
.regs
[ OP
[1] ] = (State
.regs
[ OP
[1] ] << 1) | condition_met (OP
[0]);
1982 trace_output (OP_EX1
);
1987 /* This function is courtesy of Sugimoto at NEC, via Seow Tan
1988 (Soew_Tan@el.nec.com) */
1993 unsigned long int als
,
1994 unsigned long int sfi
,
1995 unsigned32
/*unsigned long int*/ * quotient_ptr
,
1996 unsigned32
/*unsigned long int*/ * remainder_ptr
,
2000 unsigned long ald
= sfi
>> (N
- 1);
2001 unsigned long alo
= als
;
2006 unsigned int R1
= 1;
2007 unsigned int DBZ
= (als
== 0) ? 1 : 0;
2008 unsigned long alt
= Q
? ~als
: als
;
2011 alo
= ald
+ alt
+ Q
;
2012 C
= (((alt
>> 31) & (ald
>> 31))
2013 | (((alt
>> 31) ^ (ald
>> 31)) & (~alo
>> 31)));
2016 R1
= (alo
== 0) ? 0 : (R1
& Q
);
2017 if ((S
^ (alo
>>31)) && !C
)
2022 sfi
= (sfi
<< (32-N
+1)) | Q
;
2023 ald
= (alo
<< 1) | (sfi
>> 31);
2025 /* 2nd - N-1th Loop */
2026 for (i
= 2; i
< N
; i
++)
2028 alt
= Q
? ~als
: als
;
2029 alo
= ald
+ alt
+ Q
;
2030 C
= (((alt
>> 31) & (ald
>> 31))
2031 | (((alt
>> 31) ^ (ald
>> 31)) & (~alo
>> 31)));
2034 R1
= (alo
== 0) ? 0 : (R1
& Q
);
2035 if ((S
^ (alo
>>31)) && !C
&& !DBZ
)
2040 sfi
= (sfi
<< 1) | Q
;
2041 ald
= (alo
<< 1) | (sfi
>> 31);
2045 alt
= Q
? ~als
: als
;
2046 alo
= ald
+ alt
+ Q
;
2047 C
= (((alt
>> 31) & (ald
>> 31))
2048 | (((alt
>> 31) ^ (ald
>> 31)) & (~alo
>> 31)));
2051 R1
= (alo
== 0) ? 0 : (R1
& Q
);
2052 if ((S
^ (alo
>>31)) && !C
)
2057 * quotient_ptr
= (sfi
<< 1) | Q
;
2058 * remainder_ptr
= Q
? alo
: (alo
+ als
);
2059 * overflow_ptr
= DBZ
| R1
;
2062 /* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
2067 unsigned long int als
,
2068 unsigned long int sfi
,
2069 signed32
/*signed long int*/ * quotient_ptr
,
2070 signed32
/*signed long int*/ * remainder_ptr
,
2074 unsigned long ald
= (signed long) sfi
>> (N
- 1);
2075 unsigned long alo
= als
;
2076 unsigned int SS
= als
>> 31;
2077 unsigned int SD
= sfi
>> 31;
2078 unsigned int R1
= 1;
2080 unsigned int DBZ
= als
== 0 ? 1 : 0;
2081 unsigned int Q
= ~(SS
^ SD
) & 1;
2085 unsigned long alt
= Q
? ~als
: als
;
2090 alo
= ald
+ alt
+ Q
;
2091 C
= (((alt
>> 31) & (ald
>> 31))
2092 | (((alt
>> 31) ^ (ald
>> 31)) & (~alo
>> 31)));
2094 R1
= (alo
== 0) ? 0 : (R1
& (Q
^ (SS
^ SD
)));
2096 sfi
= (sfi
<< (32-N
+1)) | Q
;
2097 ald
= (alo
<< 1) | (sfi
>> 31);
2098 if ((alo
>> 31) ^ (ald
>> 31))
2103 /* 2nd - N-1th Loop */
2105 for (i
= 2; i
< N
; i
++)
2107 alt
= Q
? ~als
: als
;
2108 alo
= ald
+ alt
+ Q
;
2109 C
= (((alt
>> 31) & (ald
>> 31))
2110 | (((alt
>> 31) ^ (ald
>> 31)) & (~alo
>> 31)));
2112 R1
= (alo
== 0) ? 0 : (R1
& (Q
^ (SS
^ SD
)));
2114 sfi
= (sfi
<< 1) | Q
;
2115 ald
= (alo
<< 1) | (sfi
>> 31);
2116 if ((alo
>> 31) ^ (ald
>> 31))
2123 alt
= Q
? ~als
: als
;
2124 alo
= ald
+ alt
+ Q
;
2125 C
= (((alt
>> 31) & (ald
>> 31))
2126 | (((alt
>> 31) ^ (ald
>> 31)) & (~alo
>> 31)));
2128 R1
= (alo
== 0) ? 0 : (R1
& (Q
^ (SS
^ SD
)));
2129 sfi
= (sfi
<< (32-N
+1));
2135 alt
= Q
? ~als
: als
;
2136 alo
= ald
+ alt
+ Q
;
2138 R1
= R1
& ((~alo
>> 31) ^ SD
);
2139 if ((alo
!= 0) && ((Q
^ (SS
^ SD
)) ^ R1
)) alo
= ald
;
2141 ald
= sfi
= (long) ((sfi
>> 1) | (SS
^ SD
) << 31) >> (32-N
-1) | Q
;
2143 ald
= sfi
= sfi
| Q
;
2145 OV
= DBZ
| ((alo
== 0) ? 0 : R1
);
2147 * remainder_ptr
= alo
;
2150 if (((alo
!= 0) && ((SS
^ SD
) ^ R1
))
2151 || ((alo
== 0) && (SS
^ R1
)))
2156 OV
= (DBZ
| R1
) ? OV
: ((alo
>> 31) & (~ald
>> 31));
2158 * quotient_ptr
= alo
;
2159 * overflow_ptr
= OV
;
2162 /* sdivun imm5, reg1, reg2, reg3 */
2166 unsigned32
/*unsigned long int*/ quotient
;
2167 unsigned32
/*unsigned long int*/ remainder
;
2168 unsigned long int divide_by
;
2169 unsigned long int divide_this
;
2173 trace_input ("sdivun", OP_IMM_REG_REG_REG
, 0);
2175 imm5
= 32 - ((OP
[3] & 0x3c0000) >> 17);
2177 divide_by
= State
.regs
[ OP
[0] ];
2178 divide_this
= State
.regs
[ OP
[1] ] << imm5
;
2180 divun (imm5
, divide_by
, divide_this
, & quotient
, & remainder
, & overflow
);
2182 State
.regs
[ OP
[1] ] = quotient
;
2183 State
.regs
[ OP
[2] >> 11 ] = remainder
;
2185 /* Set condition codes. */
2186 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2188 if (overflow
) PSW
|= PSW_OV
;
2189 if (quotient
== 0) PSW
|= PSW_Z
;
2190 if (quotient
& 0x80000000) PSW
|= PSW_S
;
2192 trace_output (OP_IMM_REG_REG_REG
);
2197 /* sdivn imm5, reg1, reg2, reg3 */
2201 signed32
/*signed long int*/ quotient
;
2202 signed32
/*signed long int*/ remainder
;
2203 signed long int divide_by
;
2204 signed long int divide_this
;
2208 trace_input ("sdivn", OP_IMM_REG_REG_REG
, 0);
2210 imm5
= 32 - ((OP
[3] & 0x3c0000) >> 17);
2212 divide_by
= (signed32
) State
.regs
[ OP
[0] ];
2213 divide_this
= (signed32
) (State
.regs
[ OP
[1] ] << imm5
);
2215 divn (imm5
, divide_by
, divide_this
, & quotient
, & remainder
, & overflow
);
2217 State
.regs
[ OP
[1] ] = quotient
;
2218 State
.regs
[ OP
[2] >> 11 ] = remainder
;
2220 /* Set condition codes. */
2221 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2223 if (overflow
) PSW
|= PSW_OV
;
2224 if (quotient
== 0) PSW
|= PSW_Z
;
2225 if (quotient
< 0) PSW
|= PSW_S
;
2227 trace_output (OP_IMM_REG_REG_REG
);
2232 /* sdivhun imm5, reg1, reg2, reg3 */
2236 unsigned32
/*unsigned long int*/ quotient
;
2237 unsigned32
/*unsigned long int*/ remainder
;
2238 unsigned long int divide_by
;
2239 unsigned long int divide_this
;
2243 trace_input ("sdivhun", OP_IMM_REG_REG_REG
, 0);
2245 imm5
= 32 - ((OP
[3] & 0x3c0000) >> 17);
2247 divide_by
= State
.regs
[ OP
[0] ] & 0xffff;
2248 divide_this
= State
.regs
[ OP
[1] ] << imm5
;
2250 divun (imm5
, divide_by
, divide_this
, & quotient
, & remainder
, & overflow
);
2252 State
.regs
[ OP
[1] ] = quotient
;
2253 State
.regs
[ OP
[2] >> 11 ] = remainder
;
2255 /* Set condition codes. */
2256 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2258 if (overflow
) PSW
|= PSW_OV
;
2259 if (quotient
== 0) PSW
|= PSW_Z
;
2260 if (quotient
& 0x80000000) PSW
|= PSW_S
;
2262 trace_output (OP_IMM_REG_REG_REG
);
2267 /* sdivhn imm5, reg1, reg2, reg3 */
2271 signed32
/*signed long int*/ quotient
;
2272 signed32
/*signed long int*/ remainder
;
2273 signed long int divide_by
;
2274 signed long int divide_this
;
2278 trace_input ("sdivhn", OP_IMM_REG_REG_REG
, 0);
2280 imm5
= 32 - ((OP
[3] & 0x3c0000) >> 17);
2282 divide_by
= EXTEND16 (State
.regs
[ OP
[0] ]);
2283 divide_this
= (signed32
) (State
.regs
[ OP
[1] ] << imm5
);
2285 divn (imm5
, divide_by
, divide_this
, & quotient
, & remainder
, & overflow
);
2287 State
.regs
[ OP
[1] ] = quotient
;
2288 State
.regs
[ OP
[2] >> 11 ] = remainder
;
2290 /* Set condition codes. */
2291 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2293 if (overflow
) PSW
|= PSW_OV
;
2294 if (quotient
== 0) PSW
|= PSW_Z
;
2295 if (quotient
< 0) PSW
|= PSW_S
;
2297 trace_output (OP_IMM_REG_REG_REG
);
2302 /* divu reg1, reg2, reg3 */
2306 unsigned long int quotient
;
2307 unsigned long int remainder
;
2308 unsigned long int divide_by
;
2309 unsigned long int divide_this
;
2312 trace_input ("divu", OP_REG_REG_REG
, 0);
2314 /* Compute the result. */
2316 divide_by
= State
.regs
[ OP
[0] ];
2317 divide_this
= State
.regs
[ OP
[1] ];
2325 State
.regs
[ OP
[1] ] = quotient
= divide_this
/ divide_by
;
2326 State
.regs
[ OP
[2] >> 11 ] = remainder
= divide_this
% divide_by
;
2328 /* Set condition codes. */
2329 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2331 if (overflow
) PSW
|= PSW_OV
;
2332 if (quotient
== 0) PSW
|= PSW_Z
;
2333 if (quotient
& 0x80000000) PSW
|= PSW_S
;
2336 trace_output (OP_REG_REG_REG
);
2341 /* div reg1, reg2, reg3 */
2345 signed long int quotient
;
2346 signed long int remainder
;
2347 signed long int divide_by
;
2348 signed long int divide_this
;
2350 trace_input ("div", OP_REG_REG_REG
, 0);
2352 /* Compute the result. */
2354 divide_by
= (signed32
) State
.regs
[ OP
[0] ];
2355 divide_this
= State
.regs
[ OP
[1] ];
2361 else if (divide_by
== -1 && divide_this
== (1L << 31))
2364 PSW
|= PSW_OV
| PSW_S
;
2365 State
.regs
[ OP
[1] ] = (1 << 31);
2366 State
.regs
[ OP
[2] >> 11 ] = 0;
2370 divide_this
= (signed32
) divide_this
;
2371 State
.regs
[ OP
[1] ] = quotient
= divide_this
/ divide_by
;
2372 State
.regs
[ OP
[2] >> 11 ] = remainder
= divide_this
% divide_by
;
2374 /* Set condition codes. */
2375 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2377 if (quotient
== 0) PSW
|= PSW_Z
;
2378 if (quotient
< 0) PSW
|= PSW_S
;
2381 trace_output (OP_REG_REG_REG
);
2386 /* divhu reg1, reg2, reg3 */
2390 unsigned long int quotient
;
2391 unsigned long int remainder
;
2392 unsigned long int divide_by
;
2393 unsigned long int divide_this
;
2396 trace_input ("divhu", OP_REG_REG_REG
, 0);
2398 /* Compute the result. */
2400 divide_by
= State
.regs
[ OP
[0] ] & 0xffff;
2401 divide_this
= State
.regs
[ OP
[1] ];
2409 State
.regs
[ OP
[1] ] = quotient
= divide_this
/ divide_by
;
2410 State
.regs
[ OP
[2] >> 11 ] = remainder
= divide_this
% divide_by
;
2412 /* Set condition codes. */
2413 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2415 if (overflow
) PSW
|= PSW_OV
;
2416 if (quotient
== 0) PSW
|= PSW_Z
;
2417 if (quotient
& 0x80000000) PSW
|= PSW_S
;
2420 trace_output (OP_REG_REG_REG
);
2425 /* divh reg1, reg2, reg3 */
2429 signed long int quotient
;
2430 signed long int remainder
;
2431 signed long int divide_by
;
2432 signed long int divide_this
;
2435 trace_input ("divh", OP_REG_REG_REG
, 0);
2437 /* Compute the result. */
2439 divide_by
= EXTEND16 (State
.regs
[ OP
[0] ]);
2440 divide_this
= State
.regs
[ OP
[1] ];
2446 else if (divide_by
== -1 && divide_this
== (1L << 31))
2449 PSW
|= PSW_OV
| PSW_S
;
2450 State
.regs
[ OP
[1] ] = (1 << 31);
2451 State
.regs
[ OP
[2] >> 11 ] = 0;
2455 divide_this
= (signed32
) divide_this
;
2456 State
.regs
[ OP
[1] ] = quotient
= divide_this
/ divide_by
;
2457 State
.regs
[ OP
[2] >> 11 ] = remainder
= divide_this
% divide_by
;
2459 /* Set condition codes. */
2460 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2462 if (quotient
== 0) PSW
|= PSW_Z
;
2463 if (quotient
< 0) PSW
|= PSW_S
;
2466 trace_output (OP_REG_REG_REG
);
2471 /* mulu imm9, reg2, reg3 */
2475 trace_input ("mulu", OP_IMM_REG_REG
, 0);
2477 Multiply64 (0, (OP
[3] & 0x1f) | ((OP
[3] >> 13) & 0x1e0));
2479 trace_output (OP_IMM_REG_REG
);
2484 /* mul imm9, reg2, reg3 */
2488 trace_input ("mul", OP_IMM_REG_REG
, 0);
2490 Multiply64 (1, SEXT9 ((OP
[3] & 0x1f) | ((OP
[3] >> 13) & 0x1e0)));
2492 trace_output (OP_IMM_REG_REG
);
2503 trace_input ("ld.hu", OP_LOAD32
, 2);
2505 adr
= State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2] & ~1);
2508 State
.regs
[ OP
[1] ] = load_mem (adr
, 2);
2510 trace_output (OP_LOAD32
);
2522 trace_input ("ld.bu", OP_LOAD32
, 1);
2524 adr
= (State
.regs
[ OP
[0] ]
2525 + (EXTEND16 (OP
[2] & ~1) | ((OP
[3] >> 5) & 1)));
2527 State
.regs
[ OP
[1] ] = load_mem (adr
, 1);
2529 trace_output (OP_LOAD32
);
2534 /* prepare list12, imm5, imm32 */
2540 trace_input ("prepare", OP_PUSHPOP1
, 0);
2542 /* Store the registers with lower number registers being placed at higher addresses. */
2543 for (i
= 0; i
< 12; i
++)
2544 if ((OP
[3] & (1 << type1_regs
[ i
])))
2547 store_mem (SP
, 4, State
.regs
[ 20 + i
]);
2550 SP
-= (OP
[3] & 0x3e) << 1;
2552 EP
= load_mem (PC
+ 4, 4);
2554 trace_output (OP_PUSHPOP1
);
2559 /* prepare list12, imm5, imm16-32 */
2565 trace_input ("prepare", OP_PUSHPOP1
, 0);
2567 /* Store the registers with lower number registers being placed at higher addresses. */
2568 for (i
= 0; i
< 12; i
++)
2569 if ((OP
[3] & (1 << type1_regs
[ i
])))
2572 store_mem (SP
, 4, State
.regs
[ 20 + i
]);
2575 SP
-= (OP
[3] & 0x3e) << 1;
2577 EP
= load_mem (PC
+ 4, 2) << 16;
2579 trace_output (OP_PUSHPOP1
);
2584 /* prepare list12, imm5, imm16 */
2590 trace_input ("prepare", OP_PUSHPOP1
, 0);
2592 /* Store the registers with lower number registers being placed at higher addresses. */
2593 for (i
= 0; i
< 12; i
++)
2594 if ((OP
[3] & (1 << type1_regs
[ i
])))
2597 store_mem (SP
, 4, State
.regs
[ 20 + i
]);
2600 SP
-= (OP
[3] & 0x3e) << 1;
2602 EP
= EXTEND16 (load_mem (PC
+ 4, 2));
2604 trace_output (OP_PUSHPOP1
);
2609 /* prepare list12, imm5, sp */
2615 trace_input ("prepare", OP_PUSHPOP1
, 0);
2617 /* Store the registers with lower number registers being placed at higher addresses. */
2618 for (i
= 0; i
< 12; i
++)
2619 if ((OP
[3] & (1 << type1_regs
[ i
])))
2622 store_mem (SP
, 4, State
.regs
[ 20 + i
]);
2625 SP
-= (OP
[3] & 0x3e) << 1;
2629 trace_output (OP_PUSHPOP1
);
2634 /* mul reg1, reg2, reg3 */
2638 trace_input ("mul", OP_REG_REG_REG
, 0);
2640 Multiply64 (1, State
.regs
[ OP
[0] ]);
2642 trace_output (OP_REG_REG_REG
);
2653 trace_input ("popmh", OP_PUSHPOP2
, 0);
2655 if (OP
[3] & (1 << 19))
2657 if ((PSW
& PSW_NP
) && ((PSW
& PSW_EP
) == 0))
2659 FEPSW
= load_mem ( SP
& ~ 3, 4);
2660 FEPC
= load_mem ((SP
+ 4) & ~ 3, 4);
2664 EIPSW
= load_mem ( SP
& ~ 3, 4);
2665 EIPC
= load_mem ((SP
+ 4) & ~ 3, 4);
2671 /* Load the registers with lower number registers being retrieved from higher addresses. */
2673 if ((OP
[3] & (1 << type2_regs
[ i
])))
2675 State
.regs
[ i
+ 16 ] = load_mem (SP
& ~ 3, 4);
2679 trace_output (OP_PUSHPOP2
);
2690 trace_input ("popml", OP_PUSHPOP3
, 0);
2692 if (OP
[3] & (1 << 19))
2694 if ((PSW
& PSW_NP
) && ((PSW
& PSW_EP
) == 0))
2696 FEPSW
= load_mem ( SP
& ~ 3, 4);
2697 FEPC
= load_mem ((SP
+ 4) & ~ 3, 4);
2701 EIPSW
= load_mem ( SP
& ~ 3, 4);
2702 EIPC
= load_mem ((SP
+ 4) & ~ 3, 4);
2708 if (OP
[3] & (1 << 3))
2710 PSW
= load_mem (SP
& ~ 3, 4);
2714 /* Load the registers with lower number registers being retrieved from higher addresses. */
2716 if ((OP
[3] & (1 << type3_regs
[ i
])))
2718 State
.regs
[ i
+ 1 ] = load_mem (SP
& ~ 3, 4);
2722 trace_output (OP_PUSHPOP2
);
2733 trace_input ("pushmh", OP_PUSHPOP2
, 0);
2735 /* Store the registers with lower number registers being placed at higher addresses. */
2736 for (i
= 0; i
< 16; i
++)
2737 if ((OP
[3] & (1 << type2_regs
[ i
])))
2740 store_mem (SP
& ~ 3, 4, State
.regs
[ i
+ 16 ]);
2743 if (OP
[3] & (1 << 19))
2747 if ((PSW
& PSW_NP
) && ((PSW
& PSW_EP
) == 0))
2749 store_mem ((SP
+ 4) & ~ 3, 4, FEPC
);
2750 store_mem ( SP
& ~ 3, 4, FEPSW
);
2754 store_mem ((SP
+ 4) & ~ 3, 4, EIPC
);
2755 store_mem ( SP
& ~ 3, 4, EIPSW
);
2759 trace_output (OP_PUSHPOP2
);
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