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* gx prototype: simulator I/O bug fix
[deliverable/binutils-gdb.git] / sim / v850 / simops.c
1 #include <signal.h>
2 #include "sim-main.h"
3 #include "v850_sim.h"
4 #include "simops.h"
5
6 #ifdef HAVE_UTIME_H
7 #include <utime.h>
8 #endif
9
10 #ifdef HAVE_TIME_H
11 #include <time.h>
12 #endif
13
14 #ifdef HAVE_UNISTD_H
15 #include <unistd.h>
16 #endif
17
18 #ifdef HAVE_STRING_H
19 #include <string.h>
20 #else
21 #ifdef HAVE_STRINGS_H
22 #include <strings.h>
23 #endif
24 #endif
25
26
27
28
29
30 /* FIXME - should be including a version of syscall.h that does not
31 pollute the name space */
32 #include "../../libgloss/v850/sys/syscall.h"
33
34 #include "libiberty.h"
35
36 #include <errno.h>
37 #if !defined(__GO32__) && !defined(_WIN32)
38 #include <sys/stat.h>
39 #include <sys/times.h>
40 #include <sys/time.h>
41 #endif
42
43 /* start-sanitize-v850e */
44 /* This is an array of the bit positions of registers r20 .. r31 in
45 that order in a prepare/dispose instruction. */
46 int type1_regs[12] = { 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 0, 21 };
47 /* end-sanitize-v850e */
48 /* start-sanitize-v850eq */
49 /* This is an array of the bit positions of registers r16 .. r31 in
50 that order in a push/pop instruction. */
51 int type2_regs[16] = { 3, 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
52 /* This is an array of the bit positions of registers r1 .. r15 in
53 that order in a push/pop instruction. */
54 int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
55 /* end-sanitize-v850eq */
56
57 #ifdef DEBUG
58 #ifndef SIZE_INSTRUCTION
59 #define SIZE_INSTRUCTION 18
60 #endif
61
62 #ifndef SIZE_VALUES
63 #define SIZE_VALUES 11
64 #endif
65
66
67 unsigned32 trace_values[3];
68 int trace_num_values;
69 unsigned32 trace_pc;
70 const char *trace_name;
71 const char *trace_module;
72
73
74 void
75 trace_input (name, type, size)
76 char *name;
77 enum op_types type;
78 int size;
79 {
80
81 if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
82 return;
83
84 trace_pc = PC;
85 trace_name = name;
86 trace_module = "alu";
87
88 switch (type)
89 {
90 default:
91 case OP_UNKNOWN:
92 case OP_NONE:
93 case OP_TRAP:
94 trace_num_values = 0;
95 break;
96
97 case OP_REG:
98 case OP_REG_REG_MOVE:
99 trace_values[0] = State.regs[OP[0]];
100 trace_num_values = 1;
101 break;
102
103 /* start-sanitize-v850e */
104 case OP_BIT_CHANGE:
105 /* end-sanitize-v850e */
106 case OP_REG_REG:
107 case OP_REG_REG_CMP:
108 trace_values[0] = State.regs[OP[1]];
109 trace_values[1] = State.regs[OP[0]];
110 trace_num_values = 2;
111 break;
112
113 case OP_IMM_REG:
114 case OP_IMM_REG_CMP:
115 trace_values[0] = SEXT5 (OP[0]);
116 trace_values[1] = OP[1];
117 trace_num_values = 2;
118 break;
119
120 case OP_IMM_REG_MOVE:
121 trace_values[0] = SEXT5 (OP[0]);
122 trace_num_values = 1;
123 break;
124
125 case OP_COND_BR:
126 trace_values[0] = State.pc;
127 trace_values[1] = SEXT9 (OP[0]);
128 trace_values[2] = PSW;
129 trace_num_values = 3;
130 break;
131
132 case OP_LOAD16:
133 trace_values[0] = OP[1] * size;
134 trace_values[1] = State.regs[30];
135 trace_num_values = 2;
136 break;
137
138 case OP_STORE16:
139 trace_values[0] = State.regs[OP[0]];
140 trace_values[1] = OP[1] * size;
141 trace_values[2] = State.regs[30];
142 trace_num_values = 3;
143 break;
144
145 case OP_LOAD32:
146 trace_values[0] = EXTEND16 (OP[2]);
147 trace_values[1] = State.regs[OP[0]];
148 trace_num_values = 2;
149 break;
150
151 case OP_STORE32:
152 trace_values[0] = State.regs[OP[1]];
153 trace_values[1] = EXTEND16 (OP[2]);
154 trace_values[2] = State.regs[OP[0]];
155 trace_num_values = 3;
156 break;
157
158 case OP_JUMP:
159 trace_values[0] = SEXT22 (OP[0]);
160 trace_values[1] = State.pc;
161 trace_num_values = 2;
162 break;
163
164 case OP_IMM_REG_REG:
165 trace_values[0] = EXTEND16 (OP[0]) << size;
166 trace_values[1] = State.regs[OP[1]];
167 trace_num_values = 2;
168 break;
169
170 case OP_IMM16_REG_REG:
171 trace_values[0] = EXTEND16 (OP[2]) << size;
172 trace_values[1] = State.regs[OP[1]];
173 trace_num_values = 2;
174 break;
175
176 case OP_UIMM_REG_REG:
177 trace_values[0] = (OP[0] & 0xffff) << size;
178 trace_values[1] = State.regs[OP[1]];
179 trace_num_values = 2;
180 break;
181
182 case OP_UIMM16_REG_REG:
183 trace_values[0] = (OP[2]) << size;
184 trace_values[1] = State.regs[OP[1]];
185 trace_num_values = 2;
186 break;
187
188 case OP_BIT:
189 trace_num_values = 0;
190 break;
191
192 case OP_EX1:
193 trace_values[0] = PSW;
194 trace_num_values = 1;
195 break;
196
197 case OP_EX2:
198 trace_num_values = 0;
199 break;
200
201 case OP_LDSR:
202 trace_values[0] = State.regs[OP[0]];
203 trace_num_values = 1;
204 break;
205
206 case OP_STSR:
207 trace_values[0] = State.sregs[OP[1]];
208 trace_num_values = 1;
209 }
210
211 }
212
213 void
214 trace_result (int has_result, unsigned32 result)
215 {
216 char buf[1000];
217 char *chp;
218
219 buf[0] = '\0';
220 chp = buf;
221
222 /* write out the values saved during the trace_input call */
223 {
224 int i;
225 for (i = 0; i < trace_num_values; i++)
226 {
227 sprintf (chp, "%*s0x%.8lx", SIZE_VALUES - 10, "", trace_values[i]);
228 chp = strchr (chp, '\0');
229 }
230 while (i++ < 3)
231 {
232 sprintf (chp, "%*s", SIZE_VALUES, "");
233 chp = strchr (chp, '\0');
234 }
235 }
236
237 /* append any result to the end of the buffer */
238 if (has_result)
239 sprintf (chp, " :: 0x%.8lx", (unsigned long)result);
240
241 trace_one_insn (simulator, STATE_CPU (simulator, 0), trace_pc,
242 TRACE_LINENUM_P (STATE_CPU (simulator, 0)),
243 "simops", __LINE__, trace_module,
244 "%-*s -%s", SIZE_INSTRUCTION, trace_name, buf);
245 }
246
247 void
248 trace_output (result)
249 enum op_types result;
250 {
251 if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
252 return;
253
254 switch (result)
255 {
256 default:
257 case OP_UNKNOWN:
258 case OP_NONE:
259 case OP_TRAP:
260 case OP_REG:
261 case OP_REG_REG_CMP:
262 case OP_IMM_REG_CMP:
263 case OP_COND_BR:
264 case OP_STORE16:
265 case OP_STORE32:
266 case OP_BIT:
267 case OP_EX2:
268 trace_result (0, 0);
269 break;
270
271 case OP_LOAD16:
272 case OP_STSR:
273 trace_result (1, State.regs[OP[0]]);
274 break;
275
276 case OP_REG_REG:
277 case OP_REG_REG_MOVE:
278 case OP_IMM_REG:
279 case OP_IMM_REG_MOVE:
280 case OP_LOAD32:
281 case OP_EX1:
282 trace_result (1, State.regs[OP[1]]);
283 break;
284
285 case OP_IMM_REG_REG:
286 case OP_UIMM_REG_REG:
287 case OP_IMM16_REG_REG:
288 case OP_UIMM16_REG_REG:
289 trace_result (1, State.regs[OP[1]]);
290 break;
291
292 case OP_JUMP:
293 if (OP[1] != 0)
294 trace_result (1, State.regs[OP[1]]);
295 else
296 trace_result (0, 0);
297 break;
298
299 case OP_LDSR:
300 trace_result (1, State.sregs[OP[1]]);
301 break;
302 }
303 }
304 #endif
305
306 \f
307 /* Returns 1 if the specific condition is met, returns 0 otherwise. */
308 int
309 condition_met (unsigned code)
310 {
311 unsigned int psw = PSW;
312
313 switch (code & 0xf)
314 {
315 case 0x0: return ((psw & PSW_OV) != 0);
316 case 0x1: return ((psw & PSW_CY) != 0);
317 case 0x2: return ((psw & PSW_Z) != 0);
318 case 0x3: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
319 case 0x4: return ((psw & PSW_S) != 0);
320 /*case 0x5: return 1;*/
321 case 0x6: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
322 case 0x7: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) != 0);
323 case 0x8: return ((psw & PSW_OV) == 0);
324 case 0x9: return ((psw & PSW_CY) == 0);
325 case 0xa: return ((psw & PSW_Z) == 0);
326 case 0xb: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
327 case 0xc: return ((psw & PSW_S) == 0);
328 case 0xd: return ((psw & PSW_SAT) != 0);
329 case 0xe: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
330 case 0xf: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) == 0);
331 }
332
333 return 1;
334 }
335 /* start-sanitize-v850e */
336
337 static unsigned long
338 Add32 (unsigned long a1, unsigned long a2, int * carry)
339 {
340 unsigned long result = (a1 + a2);
341
342 * carry = (result < a1);
343
344 return result;
345 }
346
347 static void
348 Multiply64 (boolean sign, unsigned long op0)
349 {
350 unsigned long op1;
351 unsigned long lo;
352 unsigned long mid1;
353 unsigned long mid2;
354 unsigned long hi;
355 unsigned long RdLo;
356 unsigned long RdHi;
357 int carry;
358
359 op1 = State.regs[ OP[1] ];
360
361 if (sign)
362 {
363 /* Compute sign of result and adjust operands if necessary. */
364
365 sign = (op0 ^ op1) & 0x80000000;
366
367 if (((signed long) op0) < 0)
368 op0 = - op0;
369
370 if (((signed long) op1) < 0)
371 op1 = - op1;
372 }
373
374 /* We can split the 32x32 into four 16x16 operations. This ensures
375 that we do not lose precision on 32bit only hosts: */
376 lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF));
377 mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
378 mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF));
379 hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
380
381 /* We now need to add all of these results together, taking care
382 to propogate the carries from the additions: */
383 RdLo = Add32 (lo, (mid1 << 16), & carry);
384 RdHi = carry;
385 RdLo = Add32 (RdLo, (mid2 << 16), & carry);
386 RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi);
387
388 if (sign)
389 {
390 /* Negate result if necessary. */
391
392 RdLo = ~ RdLo;
393 RdHi = ~ RdHi;
394 if (RdLo == 0xFFFFFFFF)
395 {
396 RdLo = 0;
397 RdHi += 1;
398 }
399 else
400 RdLo += 1;
401 }
402
403 /* Don't store into register 0. */
404 if (OP[1])
405 State.regs[ OP[1] ] = RdLo;
406 if (OP[2] >> 11)
407 State.regs[ OP[2] >> 11 ] = RdHi;
408
409 return;
410 }
411
412 /* end-sanitize-v850e */
413 \f
414 /* Read a null terminated string from memory, return in a buffer */
415 static char *
416 fetch_str (sd, addr)
417 SIM_DESC sd;
418 address_word addr;
419 {
420 char *buf;
421 int nr = 0;
422 while (sim_core_read_1 (STATE_CPU (sd, 0),
423 PC, sim_core_read_map, addr + nr) != 0)
424 nr++;
425 buf = NZALLOC (char, nr + 1);
426 sim_read (simulator, addr, buf, nr);
427 return buf;
428 }
429
430 /* Read a null terminated argument vector from memory, return in a
431 buffer */
432 static char **
433 fetch_argv (sd, addr)
434 SIM_DESC sd;
435 address_word addr;
436 {
437 int max_nr = 64;
438 int nr = 0;
439 char **buf = xmalloc (max_nr * sizeof (char*));
440 while (1)
441 {
442 unsigned32 a = sim_core_read_4 (STATE_CPU (sd, 0),
443 PC, sim_core_read_map, addr + nr * 4);
444 if (a == 0) break;
445 buf[nr] = fetch_str (sd, a);
446 nr ++;
447 if (nr == max_nr - 1)
448 {
449 max_nr += 50;
450 buf = xrealloc (buf, max_nr * sizeof (char*));
451 }
452 }
453 buf[nr] = 0;
454 return buf;
455 }
456
457 \f
458 /* sst.b */
459 int
460 OP_380 ()
461 {
462 trace_input ("sst.b", OP_STORE16, 1);
463
464 store_mem (State.regs[30] + (OP[3] & 0x7f), 1, State.regs[ OP[1] ]);
465
466 trace_output (OP_STORE16);
467
468 return 2;
469 }
470
471 /* sst.h */
472 int
473 OP_480 ()
474 {
475 trace_input ("sst.h", OP_STORE16, 2);
476
477 store_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2, State.regs[ OP[1] ]);
478
479 trace_output (OP_STORE16);
480
481 return 2;
482 }
483
484 /* sst.w */
485 int
486 OP_501 ()
487 {
488 trace_input ("sst.w", OP_STORE16, 4);
489
490 store_mem (State.regs[30] + ((OP[3] & 0x7e) << 1), 4, State.regs[ OP[1] ]);
491
492 trace_output (OP_STORE16);
493
494 return 2;
495 }
496
497 /* ld.b */
498 int
499 OP_700 ()
500 {
501 int adr;
502
503 trace_input ("ld.b", OP_LOAD32, 1);
504
505 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
506
507 State.regs[ OP[1] ] = EXTEND8 (load_mem (adr, 1));
508
509 trace_output (OP_LOAD32);
510
511 return 4;
512 }
513
514 /* ld.h */
515 int
516 OP_720 ()
517 {
518 int adr;
519
520 trace_input ("ld.h", OP_LOAD32, 2);
521
522 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
523 adr &= ~0x1;
524
525 State.regs[ OP[1] ] = EXTEND16 (load_mem (adr, 2));
526
527 trace_output (OP_LOAD32);
528
529 return 4;
530 }
531
532 /* ld.w */
533 int
534 OP_10720 ()
535 {
536 int adr;
537
538 trace_input ("ld.w", OP_LOAD32, 4);
539
540 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
541 adr &= ~0x3;
542
543 State.regs[ OP[1] ] = load_mem (adr, 4);
544
545 trace_output (OP_LOAD32);
546
547 return 4;
548 }
549
550 /* st.b */
551 int
552 OP_740 ()
553 {
554 trace_input ("st.b", OP_STORE32, 1);
555
556 store_mem (State.regs[ OP[0] ] + EXTEND16 (OP[2]), 1, State.regs[ OP[1] ]);
557
558 trace_output (OP_STORE32);
559
560 return 4;
561 }
562
563 /* st.h */
564 int
565 OP_760 ()
566 {
567 int adr;
568
569 trace_input ("st.h", OP_STORE32, 2);
570
571 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
572 adr &= ~1;
573
574 store_mem (adr, 2, State.regs[ OP[1] ]);
575
576 trace_output (OP_STORE32);
577
578 return 4;
579 }
580
581 /* st.w */
582 int
583 OP_10760 ()
584 {
585 int adr;
586
587 trace_input ("st.w", OP_STORE32, 4);
588
589 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
590 adr &= ~3;
591
592 store_mem (adr, 4, State.regs[ OP[1] ]);
593
594 trace_output (OP_STORE32);
595
596 return 4;
597 }
598
599 /* add reg, reg */
600 int
601 OP_1C0 ()
602 {
603 unsigned int op0, op1, result, z, s, cy, ov;
604
605 trace_input ("add", OP_REG_REG, 0);
606
607 /* Compute the result. */
608
609 op0 = State.regs[ OP[0] ];
610 op1 = State.regs[ OP[1] ];
611
612 result = op0 + op1;
613
614 /* Compute the condition codes. */
615 z = (result == 0);
616 s = (result & 0x80000000);
617 cy = (result < op0 || result < op1);
618 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
619 && (op0 & 0x80000000) != (result & 0x80000000));
620
621 /* Store the result and condition codes. */
622 State.regs[OP[1]] = result;
623 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
624 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
625 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
626 trace_output (OP_REG_REG);
627
628 return 2;
629 }
630
631 /* add sign_extend(imm5), reg */
632 int
633 OP_240 ()
634 {
635 unsigned int op0, op1, result, z, s, cy, ov;
636 int temp;
637
638 trace_input ("add", OP_IMM_REG, 0);
639
640 /* Compute the result. */
641 temp = SEXT5 (OP[0]);
642 op0 = temp;
643 op1 = State.regs[OP[1]];
644 result = op0 + op1;
645
646 /* Compute the condition codes. */
647 z = (result == 0);
648 s = (result & 0x80000000);
649 cy = (result < op0 || result < op1);
650 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
651 && (op0 & 0x80000000) != (result & 0x80000000));
652
653 /* Store the result and condition codes. */
654 State.regs[OP[1]] = result;
655 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
656 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
657 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
658 trace_output (OP_IMM_REG);
659
660 return 2;
661 }
662
663 /* addi sign_extend(imm16), reg, reg */
664 int
665 OP_600 ()
666 {
667 unsigned int op0, op1, result, z, s, cy, ov;
668
669 trace_input ("addi", OP_IMM16_REG_REG, 0);
670
671 /* Compute the result. */
672
673 op0 = EXTEND16 (OP[2]);
674 op1 = State.regs[ OP[0] ];
675 result = op0 + op1;
676
677 /* Compute the condition codes. */
678 z = (result == 0);
679 s = (result & 0x80000000);
680 cy = (result < op0 || result < op1);
681 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
682 && (op0 & 0x80000000) != (result & 0x80000000));
683
684 /* Store the result and condition codes. */
685 State.regs[OP[1]] = result;
686 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
687 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
688 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
689 trace_output (OP_IMM16_REG_REG);
690
691 return 4;
692 }
693
694 /* sub reg1, reg2 */
695 int
696 OP_1A0 ()
697 {
698 unsigned int op0, op1, result, z, s, cy, ov;
699
700 trace_input ("sub", OP_REG_REG, 0);
701 /* Compute the result. */
702 op0 = State.regs[ OP[0] ];
703 op1 = State.regs[ OP[1] ];
704 result = op1 - op0;
705
706 /* Compute the condition codes. */
707 z = (result == 0);
708 s = (result & 0x80000000);
709 cy = (op1 < op0);
710 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
711 && (op1 & 0x80000000) != (result & 0x80000000));
712
713 /* Store the result and condition codes. */
714 State.regs[OP[1]] = result;
715 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
716 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
717 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
718 trace_output (OP_REG_REG);
719
720 return 2;
721 }
722
723 /* subr reg1, reg2 */
724 int
725 OP_180 ()
726 {
727 unsigned int op0, op1, result, z, s, cy, ov;
728
729 trace_input ("subr", OP_REG_REG, 0);
730 /* Compute the result. */
731 op0 = State.regs[ OP[0] ];
732 op1 = State.regs[ OP[1] ];
733 result = op0 - op1;
734
735 /* Compute the condition codes. */
736 z = (result == 0);
737 s = (result & 0x80000000);
738 cy = (op0 < op1);
739 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
740 && (op0 & 0x80000000) != (result & 0x80000000));
741
742 /* Store the result and condition codes. */
743 State.regs[OP[1]] = result;
744 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
745 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
746 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
747 trace_output (OP_REG_REG);
748
749 return 2;
750 }
751
752 /* sxh reg1 */
753 int
754 OP_E0 ()
755 {
756 trace_input ("mulh", OP_REG_REG, 0);
757
758 State.regs[ OP[1] ] = (EXTEND16 (State.regs[ OP[1] ]) * EXTEND16 (State.regs[ OP[0] ]));
759
760 trace_output (OP_REG_REG);
761
762 return 2;
763 }
764
765 /* mulh sign_extend(imm5), reg2 */
766 int
767 OP_2E0 ()
768 {
769 trace_input ("mulh", OP_IMM_REG, 0);
770
771 State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[1] ]) * SEXT5 (OP[0]);
772
773 trace_output (OP_IMM_REG);
774
775 return 2;
776 }
777
778 /* mulhi imm16, reg1, reg2 */
779 int
780 OP_6E0 ()
781 {
782 trace_input ("mulhi", OP_IMM16_REG_REG, 0);
783
784 State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[0] ]) * EXTEND16 (OP[2]);
785
786 trace_output (OP_IMM16_REG_REG);
787
788 return 4;
789 }
790
791 /* divh reg1, reg2 */
792 int
793 OP_40 ()
794 {
795 unsigned int op0, op1, result, ov, s, z;
796 int temp;
797
798 trace_input ("divh", OP_REG_REG, 0);
799
800 /* Compute the result. */
801 temp = EXTEND16 (State.regs[ OP[0] ]);
802 op0 = temp;
803 op1 = State.regs[OP[1]];
804
805 if (op0 == 0xffffffff && op1 == 0x80000000)
806 {
807 result = 0x80000000;
808 ov = 1;
809 }
810 else if (op0 != 0)
811 {
812 result = op1 / op0;
813 ov = 0;
814 }
815 else
816 {
817 result = 0x0;
818 ov = 1;
819 }
820
821 /* Compute the condition codes. */
822 z = (result == 0);
823 s = (result & 0x80000000);
824
825 /* Store the result and condition codes. */
826 State.regs[OP[1]] = result;
827 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
828 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
829 | (ov ? PSW_OV : 0));
830 trace_output (OP_REG_REG);
831
832 return 2;
833 }
834
835 /* cmp reg, reg */
836 int
837 OP_1E0 ()
838 {
839 unsigned int op0, op1, result, z, s, cy, ov;
840
841 trace_input ("cmp", OP_REG_REG_CMP, 0);
842 /* Compute the result. */
843 op0 = State.regs[ OP[0] ];
844 op1 = State.regs[ OP[1] ];
845 result = op1 - op0;
846
847 /* Compute the condition codes. */
848 z = (result == 0);
849 s = (result & 0x80000000);
850 cy = (op1 < op0);
851 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
852 && (op1 & 0x80000000) != (result & 0x80000000));
853
854 /* Set condition codes. */
855 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
856 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
857 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
858 trace_output (OP_REG_REG_CMP);
859
860 return 2;
861 }
862
863 /* cmp sign_extend(imm5), reg */
864 int
865 OP_260 ()
866 {
867 unsigned int op0, op1, result, z, s, cy, ov;
868 int temp;
869
870 /* Compute the result. */
871 trace_input ("cmp", OP_IMM_REG_CMP, 0);
872 temp = SEXT5 (OP[0]);
873 op0 = temp;
874 op1 = State.regs[OP[1]];
875 result = op1 - op0;
876
877 /* Compute the condition codes. */
878 z = (result == 0);
879 s = (result & 0x80000000);
880 cy = (op1 < op0);
881 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
882 && (op1 & 0x80000000) != (result & 0x80000000));
883
884 /* Set condition codes. */
885 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
886 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
887 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
888 trace_output (OP_IMM_REG_CMP);
889
890 return 2;
891 }
892
893 /* setf cccc,reg2 */
894 int
895 OP_7E0 ()
896 {
897 trace_input ("setf", OP_EX1, 0);
898
899 State.regs[ OP[1] ] = condition_met (OP[0]);
900
901 trace_output (OP_EX1);
902
903 return 4;
904 }
905
906 /* satadd reg,reg */
907 int
908 OP_C0 ()
909 {
910 unsigned int op0, op1, result, z, s, cy, ov, sat;
911
912 trace_input ("satadd", OP_REG_REG, 0);
913 /* Compute the result. */
914 op0 = State.regs[ OP[0] ];
915 op1 = State.regs[ OP[1] ];
916 result = op0 + op1;
917
918 /* Compute the condition codes. */
919 z = (result == 0);
920 s = (result & 0x80000000);
921 cy = (result < op0 || result < op1);
922 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
923 && (op0 & 0x80000000) != (result & 0x80000000));
924 sat = ov;
925
926 /* Store the result and condition codes. */
927 State.regs[OP[1]] = result;
928 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
929 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
930 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
931 | (sat ? PSW_SAT : 0));
932
933 /* Handle saturated results. */
934 if (sat && s)
935 State.regs[OP[1]] = 0x80000000;
936 else if (sat)
937 State.regs[OP[1]] = 0x7fffffff;
938 trace_output (OP_REG_REG);
939
940 return 2;
941 }
942
943 /* satadd sign_extend(imm5), reg */
944 int
945 OP_220 ()
946 {
947 unsigned int op0, op1, result, z, s, cy, ov, sat;
948
949 int temp;
950
951 trace_input ("satadd", OP_IMM_REG, 0);
952
953 /* Compute the result. */
954 temp = SEXT5 (OP[0]);
955 op0 = temp;
956 op1 = State.regs[OP[1]];
957 result = op0 + op1;
958
959 /* Compute the condition codes. */
960 z = (result == 0);
961 s = (result & 0x80000000);
962 cy = (result < op0 || result < op1);
963 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
964 && (op0 & 0x80000000) != (result & 0x80000000));
965 sat = ov;
966
967 /* Store the result and condition codes. */
968 State.regs[OP[1]] = result;
969 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
970 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
971 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
972 | (sat ? PSW_SAT : 0));
973
974 /* Handle saturated results. */
975 if (sat && s)
976 State.regs[OP[1]] = 0x80000000;
977 else if (sat)
978 State.regs[OP[1]] = 0x7fffffff;
979 trace_output (OP_IMM_REG);
980
981 return 2;
982 }
983
984 /* satsub reg1, reg2 */
985 int
986 OP_A0 ()
987 {
988 unsigned int op0, op1, result, z, s, cy, ov, sat;
989
990 trace_input ("satsub", OP_REG_REG, 0);
991
992 /* Compute the result. */
993 op0 = State.regs[ OP[0] ];
994 op1 = State.regs[ OP[1] ];
995 result = op1 - op0;
996
997 /* Compute the condition codes. */
998 z = (result == 0);
999 s = (result & 0x80000000);
1000 cy = (op1 < op0);
1001 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1002 && (op1 & 0x80000000) != (result & 0x80000000));
1003 sat = ov;
1004
1005 /* Store the result and condition codes. */
1006 State.regs[OP[1]] = result;
1007 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1008 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1009 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1010 | (sat ? PSW_SAT : 0));
1011
1012 /* Handle saturated results. */
1013 if (sat && s)
1014 State.regs[OP[1]] = 0x80000000;
1015 else if (sat)
1016 State.regs[OP[1]] = 0x7fffffff;
1017 trace_output (OP_REG_REG);
1018 return 2;
1019 }
1020
1021 /* satsubi sign_extend(imm16), reg */
1022 int
1023 OP_660 ()
1024 {
1025 unsigned int op0, op1, result, z, s, cy, ov, sat;
1026 int temp;
1027
1028 trace_input ("satsubi", OP_IMM_REG, 0);
1029
1030 /* Compute the result. */
1031 temp = EXTEND16 (OP[2]);
1032 op0 = temp;
1033 op1 = State.regs[ OP[0] ];
1034 result = op1 - op0;
1035
1036 /* Compute the condition codes. */
1037 z = (result == 0);
1038 s = (result & 0x80000000);
1039 cy = (op1 < op0);
1040 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1041 && (op1 & 0x80000000) != (result & 0x80000000));
1042 sat = ov;
1043
1044 /* Store the result and condition codes. */
1045 State.regs[OP[1]] = result;
1046 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1047 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1048 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1049 | (sat ? PSW_SAT : 0));
1050
1051 /* Handle saturated results. */
1052 if (sat && s)
1053 State.regs[OP[1]] = 0x80000000;
1054 else if (sat)
1055 State.regs[OP[1]] = 0x7fffffff;
1056 trace_output (OP_IMM_REG);
1057
1058 return 4;
1059 }
1060
1061 /* satsubr reg,reg */
1062 int
1063 OP_80 ()
1064 {
1065 unsigned int op0, op1, result, z, s, cy, ov, sat;
1066
1067 trace_input ("satsubr", OP_REG_REG, 0);
1068
1069 /* Compute the result. */
1070 op0 = State.regs[ OP[0] ];
1071 op1 = State.regs[ OP[1] ];
1072 result = op0 - op1;
1073
1074 /* Compute the condition codes. */
1075 z = (result == 0);
1076 s = (result & 0x80000000);
1077 cy = (result < op0);
1078 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1079 && (op1 & 0x80000000) != (result & 0x80000000));
1080 sat = ov;
1081
1082 /* Store the result and condition codes. */
1083 State.regs[OP[1]] = result;
1084 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1085 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1086 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1087 | (sat ? PSW_SAT : 0));
1088
1089 /* Handle saturated results. */
1090 if (sat && s)
1091 State.regs[OP[1]] = 0x80000000;
1092 else if (sat)
1093 State.regs[OP[1]] = 0x7fffffff;
1094 trace_output (OP_REG_REG);
1095
1096 return 2;
1097 }
1098
1099 /* tst reg,reg */
1100 int
1101 OP_160 ()
1102 {
1103 unsigned int op0, op1, result, z, s;
1104
1105 trace_input ("tst", OP_REG_REG_CMP, 0);
1106
1107 /* Compute the result. */
1108 op0 = State.regs[ OP[0] ];
1109 op1 = State.regs[ OP[1] ];
1110 result = op0 & op1;
1111
1112 /* Compute the condition codes. */
1113 z = (result == 0);
1114 s = (result & 0x80000000);
1115
1116 /* Store the condition codes. */
1117 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1118 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1119 trace_output (OP_REG_REG_CMP);
1120
1121 return 2;
1122 }
1123
1124 /* mov sign_extend(imm5), reg */
1125 int
1126 OP_200 ()
1127 {
1128 int value = SEXT5 (OP[0]);
1129
1130 trace_input ("mov", OP_IMM_REG_MOVE, 0);
1131
1132 State.regs[ OP[1] ] = value;
1133
1134 trace_output (OP_IMM_REG_MOVE);
1135
1136 return 2;
1137 }
1138
1139 /* movhi imm16, reg, reg */
1140 int
1141 OP_640 ()
1142 {
1143 trace_input ("movhi", OP_UIMM16_REG_REG, 16);
1144
1145 State.regs[ OP[1] ] = State.regs[ OP[0] ] + (OP[2] << 16);
1146
1147 trace_output (OP_UIMM16_REG_REG);
1148
1149 return 4;
1150 }
1151
1152 /* sar zero_extend(imm5),reg1 */
1153 int
1154 OP_2A0 ()
1155 {
1156 unsigned int op0, op1, result, z, s, cy;
1157
1158 trace_input ("sar", OP_IMM_REG, 0);
1159 op0 = OP[0];
1160 op1 = State.regs[ OP[1] ];
1161 result = (signed)op1 >> op0;
1162
1163 /* Compute the condition codes. */
1164 z = (result == 0);
1165 s = (result & 0x80000000);
1166 cy = (op1 & (1 << (op0 - 1)));
1167
1168 /* Store the result and condition codes. */
1169 State.regs[ OP[1] ] = result;
1170 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1171 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1172 | (cy ? PSW_CY : 0));
1173 trace_output (OP_IMM_REG);
1174
1175 return 2;
1176 }
1177
1178 /* sar reg1, reg2 */
1179 int
1180 OP_A007E0 ()
1181 {
1182 unsigned int op0, op1, result, z, s, cy;
1183
1184 trace_input ("sar", OP_REG_REG, 0);
1185
1186 op0 = State.regs[ OP[0] ] & 0x1f;
1187 op1 = State.regs[ OP[1] ];
1188 result = (signed)op1 >> op0;
1189
1190 /* Compute the condition codes. */
1191 z = (result == 0);
1192 s = (result & 0x80000000);
1193 cy = (op1 & (1 << (op0 - 1)));
1194
1195 /* Store the result and condition codes. */
1196 State.regs[OP[1]] = result;
1197 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1198 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1199 | (cy ? PSW_CY : 0));
1200 trace_output (OP_REG_REG);
1201
1202 return 4;
1203 }
1204
1205 /* shl zero_extend(imm5),reg1 */
1206 int
1207 OP_2C0 ()
1208 {
1209 unsigned int op0, op1, result, z, s, cy;
1210
1211 trace_input ("shl", OP_IMM_REG, 0);
1212 op0 = OP[0];
1213 op1 = State.regs[ OP[1] ];
1214 result = op1 << op0;
1215
1216 /* Compute the condition codes. */
1217 z = (result == 0);
1218 s = (result & 0x80000000);
1219 cy = (op1 & (1 << (32 - op0)));
1220
1221 /* Store the result and condition codes. */
1222 State.regs[OP[1]] = result;
1223 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1224 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1225 | (cy ? PSW_CY : 0));
1226 trace_output (OP_IMM_REG);
1227
1228 return 2;
1229 }
1230
1231 /* shl reg1, reg2 */
1232 int
1233 OP_C007E0 ()
1234 {
1235 unsigned int op0, op1, result, z, s, cy;
1236
1237 trace_input ("shl", OP_REG_REG, 0);
1238 op0 = State.regs[ OP[0] ] & 0x1f;
1239 op1 = State.regs[ OP[1] ];
1240 result = op1 << op0;
1241
1242 /* Compute the condition codes. */
1243 z = (result == 0);
1244 s = (result & 0x80000000);
1245 cy = (op1 & (1 << (32 - op0)));
1246
1247 /* Store the result and condition codes. */
1248 State.regs[OP[1]] = result;
1249 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1250 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1251 | (cy ? PSW_CY : 0));
1252 trace_output (OP_REG_REG);
1253
1254 return 4;
1255 }
1256
1257 /* shr zero_extend(imm5),reg1 */
1258 int
1259 OP_280 ()
1260 {
1261 unsigned int op0, op1, result, z, s, cy;
1262
1263 trace_input ("shr", OP_IMM_REG, 0);
1264 op0 = OP[0];
1265 op1 = State.regs[ OP[1] ];
1266 result = op1 >> op0;
1267
1268 /* Compute the condition codes. */
1269 z = (result == 0);
1270 s = (result & 0x80000000);
1271 cy = (op1 & (1 << (op0 - 1)));
1272
1273 /* Store the result and condition codes. */
1274 State.regs[OP[1]] = result;
1275 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1276 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1277 | (cy ? PSW_CY : 0));
1278 trace_output (OP_IMM_REG);
1279
1280 return 2;
1281 }
1282
1283 /* shr reg1, reg2 */
1284 int
1285 OP_8007E0 ()
1286 {
1287 unsigned int op0, op1, result, z, s, cy;
1288
1289 trace_input ("shr", OP_REG_REG, 0);
1290 op0 = State.regs[ OP[0] ] & 0x1f;
1291 op1 = State.regs[ OP[1] ];
1292 result = op1 >> op0;
1293
1294 /* Compute the condition codes. */
1295 z = (result == 0);
1296 s = (result & 0x80000000);
1297 cy = (op1 & (1 << (op0 - 1)));
1298
1299 /* Store the result and condition codes. */
1300 State.regs[OP[1]] = result;
1301 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1302 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1303 | (cy ? PSW_CY : 0));
1304 trace_output (OP_REG_REG);
1305
1306 return 4;
1307 }
1308
1309 /* or reg, reg */
1310 int
1311 OP_100 ()
1312 {
1313 unsigned int op0, op1, result, z, s;
1314
1315 trace_input ("or", OP_REG_REG, 0);
1316
1317 /* Compute the result. */
1318 op0 = State.regs[ OP[0] ];
1319 op1 = State.regs[ OP[1] ];
1320 result = op0 | op1;
1321
1322 /* Compute the condition codes. */
1323 z = (result == 0);
1324 s = (result & 0x80000000);
1325
1326 /* Store the result and condition codes. */
1327 State.regs[OP[1]] = result;
1328 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1329 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1330 trace_output (OP_REG_REG);
1331
1332 return 2;
1333 }
1334
1335 /* ori zero_extend(imm16), reg, reg */
1336 int
1337 OP_680 ()
1338 {
1339 unsigned int op0, op1, result, z, s;
1340
1341 trace_input ("ori", OP_UIMM16_REG_REG, 0);
1342 op0 = OP[2];
1343 op1 = State.regs[ OP[0] ];
1344 result = op0 | op1;
1345
1346 /* Compute the condition codes. */
1347 z = (result == 0);
1348 s = (result & 0x80000000);
1349
1350 /* Store the result and condition codes. */
1351 State.regs[OP[1]] = result;
1352 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1353 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1354 trace_output (OP_UIMM16_REG_REG);
1355
1356 return 4;
1357 }
1358
1359 /* and reg, reg */
1360 int
1361 OP_140 ()
1362 {
1363 unsigned int op0, op1, result, z, s;
1364
1365 trace_input ("and", OP_REG_REG, 0);
1366
1367 /* Compute the result. */
1368 op0 = State.regs[ OP[0] ];
1369 op1 = State.regs[ OP[1] ];
1370 result = op0 & op1;
1371
1372 /* Compute the condition codes. */
1373 z = (result == 0);
1374 s = (result & 0x80000000);
1375
1376 /* Store the result and condition codes. */
1377 State.regs[OP[1]] = result;
1378 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1379 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1380 trace_output (OP_REG_REG);
1381
1382 return 2;
1383 }
1384
1385 /* andi zero_extend(imm16), reg, reg */
1386 int
1387 OP_6C0 ()
1388 {
1389 unsigned int result, z;
1390
1391 trace_input ("andi", OP_UIMM16_REG_REG, 0);
1392
1393 result = OP[2] & State.regs[ OP[0] ];
1394
1395 /* Compute the condition codes. */
1396 z = (result == 0);
1397
1398 /* Store the result and condition codes. */
1399 State.regs[ OP[1] ] = result;
1400
1401 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1402 PSW |= (z ? PSW_Z : 0);
1403
1404 trace_output (OP_UIMM16_REG_REG);
1405
1406 return 4;
1407 }
1408
1409 /* xor reg, reg */
1410 int
1411 OP_120 ()
1412 {
1413 unsigned int op0, op1, result, z, s;
1414
1415 trace_input ("xor", OP_REG_REG, 0);
1416
1417 /* Compute the result. */
1418 op0 = State.regs[ OP[0] ];
1419 op1 = State.regs[ OP[1] ];
1420 result = op0 ^ op1;
1421
1422 /* Compute the condition codes. */
1423 z = (result == 0);
1424 s = (result & 0x80000000);
1425
1426 /* Store the result and condition codes. */
1427 State.regs[OP[1]] = result;
1428 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1429 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1430 trace_output (OP_REG_REG);
1431
1432 return 2;
1433 }
1434
1435 /* xori zero_extend(imm16), reg, reg */
1436 int
1437 OP_6A0 ()
1438 {
1439 unsigned int op0, op1, result, z, s;
1440
1441 trace_input ("xori", OP_UIMM16_REG_REG, 0);
1442 op0 = OP[2];
1443 op1 = State.regs[ OP[0] ];
1444 result = op0 ^ op1;
1445
1446 /* Compute the condition codes. */
1447 z = (result == 0);
1448 s = (result & 0x80000000);
1449
1450 /* Store the result and condition codes. */
1451 State.regs[OP[1]] = result;
1452 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1453 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1454 trace_output (OP_UIMM16_REG_REG);
1455
1456 return 4;
1457 }
1458
1459 /* not reg1, reg2 */
1460 int
1461 OP_20 ()
1462 {
1463 unsigned int op0, result, z, s;
1464
1465 trace_input ("not", OP_REG_REG_MOVE, 0);
1466 /* Compute the result. */
1467 op0 = State.regs[ OP[0] ];
1468 result = ~op0;
1469
1470 /* Compute the condition codes. */
1471 z = (result == 0);
1472 s = (result & 0x80000000);
1473
1474 /* Store the result and condition codes. */
1475 State.regs[OP[1]] = result;
1476 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1477 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1478 trace_output (OP_REG_REG_MOVE);
1479
1480 return 2;
1481 }
1482
1483 /* set1 */
1484 int
1485 OP_7C0 ()
1486 {
1487 unsigned int op0, op1, op2;
1488 int temp;
1489
1490 trace_input ("set1", OP_BIT, 0);
1491 op0 = State.regs[ OP[0] ];
1492 op1 = OP[1] & 0x7;
1493 temp = EXTEND16 (OP[2]);
1494 op2 = temp;
1495 temp = load_mem (op0 + op2, 1);
1496 PSW &= ~PSW_Z;
1497 if ((temp & (1 << op1)) == 0)
1498 PSW |= PSW_Z;
1499 temp |= (1 << op1);
1500 store_mem (op0 + op2, 1, temp);
1501 trace_output (OP_BIT);
1502
1503 return 4;
1504 }
1505
1506 /* not1 */
1507 int
1508 OP_47C0 ()
1509 {
1510 unsigned int op0, op1, op2;
1511 int temp;
1512
1513 trace_input ("not1", OP_BIT, 0);
1514 op0 = State.regs[ OP[0] ];
1515 op1 = OP[1] & 0x7;
1516 temp = EXTEND16 (OP[2]);
1517 op2 = temp;
1518 temp = load_mem (op0 + op2, 1);
1519 PSW &= ~PSW_Z;
1520 if ((temp & (1 << op1)) == 0)
1521 PSW |= PSW_Z;
1522 temp ^= (1 << op1);
1523 store_mem (op0 + op2, 1, temp);
1524 trace_output (OP_BIT);
1525
1526 return 4;
1527 }
1528
1529 /* clr1 */
1530 int
1531 OP_87C0 ()
1532 {
1533 unsigned int op0, op1, op2;
1534 int temp;
1535
1536 trace_input ("clr1", OP_BIT, 0);
1537 op0 = State.regs[ OP[0] ];
1538 op1 = OP[1] & 0x7;
1539 temp = EXTEND16 (OP[2]);
1540 op2 = temp;
1541 temp = load_mem (op0 + op2, 1);
1542 PSW &= ~PSW_Z;
1543 if ((temp & (1 << op1)) == 0)
1544 PSW |= PSW_Z;
1545 temp &= ~(1 << op1);
1546 store_mem (op0 + op2, 1, temp);
1547 trace_output (OP_BIT);
1548
1549 return 4;
1550 }
1551
1552 /* tst1 */
1553 int
1554 OP_C7C0 ()
1555 {
1556 unsigned int op0, op1, op2;
1557 int temp;
1558
1559 trace_input ("tst1", OP_BIT, 0);
1560 op0 = State.regs[ OP[0] ];
1561 op1 = OP[1] & 0x7;
1562 temp = EXTEND16 (OP[2]);
1563 op2 = temp;
1564 temp = load_mem (op0 + op2, 1);
1565 PSW &= ~PSW_Z;
1566 if ((temp & (1 << op1)) == 0)
1567 PSW |= PSW_Z;
1568 trace_output (OP_BIT);
1569
1570 return 4;
1571 }
1572
1573 /* di */
1574 int
1575 OP_16007E0 ()
1576 {
1577 trace_input ("di", OP_NONE, 0);
1578 PSW |= PSW_ID;
1579 trace_output (OP_NONE);
1580
1581 return 4;
1582 }
1583
1584 /* ei */
1585 int
1586 OP_16087E0 ()
1587 {
1588 trace_input ("ei", OP_NONE, 0);
1589 PSW &= ~PSW_ID;
1590 trace_output (OP_NONE);
1591
1592 return 4;
1593 }
1594
1595 /* halt */
1596 int
1597 OP_12007E0 ()
1598 {
1599 trace_input ("halt", OP_NONE, 0);
1600 /* FIXME this should put processor into a mode where NMI still handled */
1601 trace_output (OP_NONE);
1602 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1603 sim_stopped, SIGTRAP);
1604 return 0;
1605 }
1606
1607 /* trap */
1608 int
1609 OP_10007E0 ()
1610 {
1611 trace_input ("trap", OP_TRAP, 0);
1612 trace_output (OP_TRAP);
1613
1614 /* Trap 31 is used for simulating OS I/O functions */
1615
1616 if (OP[0] == 31)
1617 {
1618 int save_errno = errno;
1619 errno = 0;
1620
1621 /* Registers passed to trap 0 */
1622
1623 #define FUNC State.regs[6] /* function number, return value */
1624 #define PARM1 State.regs[7] /* optional parm 1 */
1625 #define PARM2 State.regs[8] /* optional parm 2 */
1626 #define PARM3 State.regs[9] /* optional parm 3 */
1627
1628 /* Registers set by trap 0 */
1629
1630 #define RETVAL State.regs[10] /* return value */
1631 #define RETERR State.regs[11] /* return error code */
1632
1633 /* Turn a pointer in a register into a pointer into real memory. */
1634
1635 #define MEMPTR(x) (map (x))
1636
1637 switch (FUNC)
1638 {
1639
1640 #ifdef HAVE_FORK
1641 #ifdef SYS_fork
1642 case SYS_fork:
1643 RETVAL = fork ();
1644 break;
1645 #endif
1646 #endif
1647
1648 #ifdef HAVE_EXECVE
1649 #ifdef SYS_execv
1650 case SYS_execve:
1651 {
1652 char *path = fetch_str (simulator, PARM1);
1653 char **argv = fetch_argv (simulator, PARM2);
1654 char **envp = fetch_argv (simulator, PARM3);
1655 RETVAL = execve (path, argv, envp);
1656 zfree (path);
1657 freeargv (argv);
1658 freeargv (envp);
1659 break;
1660 }
1661 #endif
1662 #endif
1663
1664 #if HAVE_EXECV
1665 #ifdef SYS_execv
1666 case SYS_execv:
1667 {
1668 char *path = fetch_str (simulator, PARM1);
1669 char **argv = fetch_argv (simulator, PARM2);
1670 RETVAL = execv (path, argv);
1671 zfree (path);
1672 freeargv (argv);
1673 break;
1674 }
1675 #endif
1676 #endif
1677
1678 #if 0
1679 #ifdef SYS_pipe
1680 case SYS_pipe:
1681 {
1682 reg_t buf;
1683 int host_fd[2];
1684
1685 buf = PARM1;
1686 RETVAL = pipe (host_fd);
1687 SW (buf, host_fd[0]);
1688 buf += sizeof(uint16);
1689 SW (buf, host_fd[1]);
1690 }
1691 break;
1692 #endif
1693 #endif
1694
1695 #if 0
1696 #ifdef SYS_wait
1697 case SYS_wait:
1698 {
1699 int status;
1700
1701 RETVAL = wait (&status);
1702 SW (PARM1, status);
1703 }
1704 break;
1705 #endif
1706 #endif
1707
1708 #ifdef SYS_read
1709 case SYS_read:
1710 {
1711 char *buf = zalloc (PARM3);
1712 RETVAL = sim_io_read (simulator, PARM1, buf, PARM3);
1713 sim_write (simulator, PARM2, buf, PARM3);
1714 zfree (buf);
1715 break;
1716 }
1717 #endif
1718
1719 #ifdef SYS_write
1720 case SYS_write:
1721 {
1722 char *buf = zalloc (PARM3);
1723 sim_read (simulator, PARM2, buf, PARM3);
1724 if (PARM1 == 1)
1725 RETVAL = sim_io_write_stdout (simulator, buf, PARM3);
1726 else
1727 RETVAL = sim_io_write (simulator, PARM1, buf, PARM3);
1728 zfree (buf);
1729 break;
1730 }
1731 #endif
1732
1733 #ifdef SYS_lseek
1734 case SYS_lseek:
1735 RETVAL = sim_io_lseek (simulator, PARM1, PARM2, PARM3);
1736 break;
1737 #endif
1738
1739 #ifdef SYS_close
1740 case SYS_close:
1741 RETVAL = sim_io_close (simulator, PARM1);
1742 break;
1743 #endif
1744
1745 #ifdef SYS_open
1746 case SYS_open:
1747 {
1748 char *buf = fetch_str (simulator, PARM1);
1749 RETVAL = sim_io_open (simulator, buf, PARM2);
1750 zfree (buf);
1751 break;
1752 }
1753 #endif
1754
1755 #ifdef SYS_exit
1756 case SYS_exit:
1757 if ((PARM1 & 0xffff0000) == 0xdead0000 && (PARM1 & 0xffff) != 0)
1758 /* get signal encoded by kill */
1759 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1760 sim_signalled, PARM1 & 0xffff);
1761 else if (PARM1 == 0xdead)
1762 /* old libraries */
1763 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1764 sim_exited, SIGABRT);
1765 else
1766 /* PARM1 has exit status */
1767 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1768 sim_exited, PARM1);
1769 break;
1770 #endif
1771
1772 #if !defined(__GO32__) && !defined(_WIN32)
1773 #ifdef SYS_stat
1774 case SYS_stat: /* added at hmsi */
1775 /* stat system call */
1776 {
1777 struct stat host_stat;
1778 reg_t buf;
1779 char *path = fetch_str (simulator, PARM1);
1780
1781 RETVAL = stat (path, &host_stat);
1782
1783 zfree (path);
1784 buf = PARM2;
1785
1786 /* Just wild-assed guesses. */
1787 store_mem (buf, 2, host_stat.st_dev);
1788 store_mem (buf + 2, 2, host_stat.st_ino);
1789 store_mem (buf + 4, 4, host_stat.st_mode);
1790 store_mem (buf + 8, 2, host_stat.st_nlink);
1791 store_mem (buf + 10, 2, host_stat.st_uid);
1792 store_mem (buf + 12, 2, host_stat.st_gid);
1793 store_mem (buf + 14, 2, host_stat.st_rdev);
1794 store_mem (buf + 16, 4, host_stat.st_size);
1795 store_mem (buf + 20, 4, host_stat.st_atime);
1796 store_mem (buf + 28, 4, host_stat.st_mtime);
1797 store_mem (buf + 36, 4, host_stat.st_ctime);
1798 }
1799 break;
1800 #endif
1801 #endif
1802
1803 #ifdef HAVE_CHOWN
1804 #ifdef SYS_chown
1805 case SYS_chown:
1806 {
1807 char *path = fetch_str (simulator, PARM1);
1808 RETVAL = chown (path, PARM2, PARM3);
1809 zfree (path);
1810 }
1811 break;
1812 #endif
1813 #endif
1814
1815 #if HAVE_CHMOD
1816 #ifdef SYS_chmod
1817 case SYS_chmod:
1818 {
1819 char *path = fetch_str (simulator, PARM1);
1820 RETVAL = chmod (path, PARM2);
1821 zfree (path);
1822 }
1823 break;
1824 #endif
1825 #endif
1826
1827 #ifdef SYS_time
1828 #if HAVE_TIME
1829 case SYS_time:
1830 {
1831 time_t now;
1832 RETVAL = time (&now);
1833 store_mem (PARM1, 4, now);
1834 }
1835 break;
1836 #endif
1837 #endif
1838
1839 #if !defined(__GO32__) && !defined(_WIN32)
1840 #ifdef SYS_times
1841 case SYS_times:
1842 {
1843 struct tms tms;
1844 RETVAL = times (&tms);
1845 store_mem (PARM1, 4, tms.tms_utime);
1846 store_mem (PARM1 + 4, 4, tms.tms_stime);
1847 store_mem (PARM1 + 8, 4, tms.tms_cutime);
1848 store_mem (PARM1 + 12, 4, tms.tms_cstime);
1849 break;
1850 }
1851 #endif
1852 #endif
1853
1854 #ifdef SYS_gettimeofday
1855 #if !defined(__GO32__) && !defined(_WIN32)
1856 case SYS_gettimeofday:
1857 {
1858 struct timeval t;
1859 struct timezone tz;
1860 RETVAL = gettimeofday (&t, &tz);
1861 store_mem (PARM1, 4, t.tv_sec);
1862 store_mem (PARM1 + 4, 4, t.tv_usec);
1863 store_mem (PARM2, 4, tz.tz_minuteswest);
1864 store_mem (PARM2 + 4, 4, tz.tz_dsttime);
1865 break;
1866 }
1867 #endif
1868 #endif
1869
1870 #ifdef SYS_utime
1871 #if HAVE_UTIME
1872 case SYS_utime:
1873 {
1874 /* Cast the second argument to void *, to avoid type mismatch
1875 if a prototype is present. */
1876 sim_io_error (simulator, "Utime not supported");
1877 /* RETVAL = utime (path, (void *) MEMPTR (PARM2)); */
1878 }
1879 break;
1880 #endif
1881 #endif
1882
1883 default:
1884 abort ();
1885 }
1886 RETERR = errno;
1887 errno = save_errno;
1888
1889 return 4;
1890 }
1891 else
1892 { /* Trap 0 -> 30 */
1893 EIPC = PC + 4;
1894 EIPSW = PSW;
1895 /* Mask out EICC */
1896 ECR &= 0xffff0000;
1897 ECR |= 0x40 + OP[0];
1898 /* Flag that we are now doing exception processing. */
1899 PSW |= PSW_EP | PSW_ID;
1900 PC = ((OP[0] < 0x10) ? 0x40 : 0x50) - 4;
1901
1902 return 0;
1903 }
1904 }
1905
1906 /* start-sanitize-v850e */
1907 /* tst1 reg2, [reg1] */
1908 int
1909 OP_E607E0 (void)
1910 {
1911 int temp;
1912
1913 trace_input ("tst1", OP_BIT, 1);
1914
1915 temp = load_mem (State.regs[ OP[0] ], 1);
1916
1917 PSW &= ~PSW_Z;
1918 if ((temp & (1 << State.regs[ OP[1] & 0x7 ])) == 0)
1919 PSW |= PSW_Z;
1920
1921 trace_output (OP_BIT);
1922
1923 return 4;
1924 }
1925
1926 /* end-sanitize-v850e */
1927 /* start-sanitize-v850e */
1928 /* mulu reg1, reg2, reg3 */
1929 int
1930 OP_22207E0 (void)
1931 {
1932 trace_input ("mulu", OP_REG_REG_REG, 0);
1933
1934 Multiply64 (false, State.regs[ OP[0] ]);
1935
1936 trace_output (OP_REG_REG_REG);
1937
1938 return 4;
1939 }
1940
1941 /* end-sanitize-v850e */
1942 /* start-sanitize-v850e */
1943
1944 #define BIT_CHANGE_OP( name, binop ) \
1945 unsigned int bit; \
1946 unsigned int temp; \
1947 \
1948 trace_input (name, OP_BIT_CHANGE, 0); \
1949 \
1950 bit = 1 << State.regs[ OP[1] & 0x7 ]; \
1951 temp = load_mem (State.regs[ OP[0] ], 1); \
1952 \
1953 PSW &= ~PSW_Z; \
1954 if ((temp & bit) == 0) \
1955 PSW |= PSW_Z; \
1956 temp binop bit; \
1957 \
1958 store_mem (State.regs[ OP[0] ], 1, temp); \
1959 \
1960 trace_output (OP_BIT_CHANGE); \
1961 \
1962 return 4;
1963
1964 /* clr1 reg2, [reg1] */
1965 int
1966 OP_E407E0 (void)
1967 {
1968 BIT_CHANGE_OP ("clr1", &= ~ );
1969 }
1970
1971 /* not1 reg2, [reg1] */
1972 int
1973 OP_E207E0 (void)
1974 {
1975 BIT_CHANGE_OP ("not1", ^= );
1976 }
1977
1978 /* set1 */
1979 int
1980 OP_E007E0 (void)
1981 {
1982 BIT_CHANGE_OP ("set1", |= );
1983 }
1984
1985 /* sasf */
1986 int
1987 OP_20007E0 (void)
1988 {
1989 trace_input ("sasf", OP_EX1, 0);
1990
1991 State.regs[ OP[1] ] = (State.regs[ OP[1] ] << 1) | condition_met (OP[0]);
1992
1993 trace_output (OP_EX1);
1994
1995 return 4;
1996 }
1997 /* end-sanitize-v850e */
1998 /* start-sanitize-v850eq */
1999 /* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
2000 void
2001 divun
2002 (
2003 unsigned int N,
2004 unsigned long int als,
2005 unsigned long int sfi,
2006 unsigned long int * quotient_ptr,
2007 unsigned long int * remainder_ptr,
2008 boolean * overflow_ptr
2009 )
2010 {
2011 unsigned long ald = sfi >> (N - 1);
2012 unsigned long alo = als;
2013 unsigned int Q = 1;
2014 unsigned int C;
2015 unsigned int S = 0;
2016 unsigned int i;
2017 unsigned int R1 = 1;
2018 unsigned int DBZ = (als == 0) ? 1 : 0;
2019 unsigned long alt = Q ? ~als : als;
2020
2021 /* 1st Loop */
2022 alo = ald + alt + Q;
2023 C = (((alt >> 31) & (ald >> 31))
2024 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2025 C = C ^ Q;
2026 Q = ~(C ^ S) & 1;
2027 R1 = (alo == 0) ? 0 : (R1 & Q);
2028 if ((S ^ (alo>>31)) && !C)
2029 {
2030 DBZ = 1;
2031 }
2032 S = alo >> 31;
2033 sfi = (sfi << (32-N+1)) | Q;
2034 ald = (alo << 1) | (sfi >> 31);
2035
2036 /* 2nd - N-1th Loop */
2037 for (i = 2; i < N; i++)
2038 {
2039 alt = Q ? ~als : als;
2040 alo = ald + alt + Q;
2041 C = (((alt >> 31) & (ald >> 31))
2042 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2043 C = C ^ Q;
2044 Q = ~(C ^ S) & 1;
2045 R1 = (alo == 0) ? 0 : (R1 & Q);
2046 if ((S ^ (alo>>31)) && !C && !DBZ)
2047 {
2048 DBZ = 1;
2049 }
2050 S = alo >> 31;
2051 sfi = (sfi << 1) | Q;
2052 ald = (alo << 1) | (sfi >> 31);
2053 }
2054
2055 /* Nth Loop */
2056 alt = Q ? ~als : als;
2057 alo = ald + alt + Q;
2058 C = (((alt >> 31) & (ald >> 31))
2059 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2060 C = C ^ Q;
2061 Q = ~(C ^ S) & 1;
2062 R1 = (alo == 0) ? 0 : (R1 & Q);
2063 if ((S ^ (alo>>31)) && !C)
2064 {
2065 DBZ = 1;
2066 }
2067
2068 * quotient_ptr = (sfi << 1) | Q;
2069 * remainder_ptr = Q ? alo : (alo + als);
2070 * overflow_ptr = DBZ | R1;
2071 }
2072
2073 /* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
2074 void
2075 divn
2076 (
2077 unsigned int N,
2078 unsigned long int als,
2079 unsigned long int sfi,
2080 signed long int * quotient_ptr,
2081 signed long int * remainder_ptr,
2082 boolean * overflow_ptr
2083 )
2084 {
2085 unsigned long ald = (signed long) sfi >> (N - 1);
2086 unsigned long alo = als;
2087 unsigned int SS = als >> 31;
2088 unsigned int SD = sfi >> 31;
2089 unsigned int R1 = 1;
2090 unsigned int OV;
2091 unsigned int DBZ = als == 0 ? 1 : 0;
2092 unsigned int Q = ~(SS ^ SD) & 1;
2093 unsigned int C;
2094 unsigned int S;
2095 unsigned int i;
2096 unsigned long alt = Q ? ~als : als;
2097
2098
2099 /* 1st Loop */
2100
2101 alo = ald + alt + Q;
2102 C = (((alt >> 31) & (ald >> 31))
2103 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2104 Q = C ^ SS;
2105 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2106 S = alo >> 31;
2107 sfi = (sfi << (32-N+1)) | Q;
2108 ald = (alo << 1) | (sfi >> 31);
2109 if ((alo >> 31) ^ (ald >> 31))
2110 {
2111 DBZ = 1;
2112 }
2113
2114 /* 2nd - N-1th Loop */
2115
2116 for (i = 2; i < N; i++)
2117 {
2118 alt = Q ? ~als : als;
2119 alo = ald + alt + Q;
2120 C = (((alt >> 31) & (ald >> 31))
2121 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2122 Q = C ^ SS;
2123 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2124 S = alo >> 31;
2125 sfi = (sfi << 1) | Q;
2126 ald = (alo << 1) | (sfi >> 31);
2127 if ((alo >> 31) ^ (ald >> 31))
2128 {
2129 DBZ = 1;
2130 }
2131 }
2132
2133 /* Nth Loop */
2134 alt = Q ? ~als : als;
2135 alo = ald + alt + Q;
2136 C = (((alt >> 31) & (ald >> 31))
2137 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2138 Q = C ^ SS;
2139 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2140 sfi = (sfi << (32-N+1));
2141 ald = alo;
2142
2143 /* End */
2144 if (alo != 0)
2145 {
2146 alt = Q ? ~als : als;
2147 alo = ald + alt + Q;
2148 }
2149 R1 = R1 & ((~alo >> 31) ^ SD);
2150 if ((alo != 0) && ((Q ^ (SS ^ SD)) ^ R1)) alo = ald;
2151 if (N != 32)
2152 ald = sfi = (long) ((sfi >> 1) | (SS ^ SD) << 31) >> (32-N-1) | Q;
2153 else
2154 ald = sfi = sfi | Q;
2155
2156 OV = DBZ | ((alo == 0) ? 0 : R1);
2157
2158 * remainder_ptr = alo;
2159
2160 /* Adj */
2161 if (((alo != 0) && ((SS ^ SD) ^ R1))
2162 || ((alo == 0) && (SS ^ R1)))
2163 alo = ald + 1;
2164 else
2165 alo = ald;
2166
2167 OV = (DBZ | R1) ? OV : ((alo >> 31) & (~ald >> 31));
2168
2169 * quotient_ptr = alo;
2170 * overflow_ptr = OV;
2171 }
2172
2173 /* sdivun imm5, reg1, reg2, reg3 */
2174 int
2175 OP_1C207E0 (void)
2176 {
2177 unsigned long int quotient;
2178 unsigned long int remainder;
2179 unsigned long int divide_by;
2180 unsigned long int divide_this;
2181 boolean overflow = false;
2182 unsigned int imm5;
2183
2184 trace_input ("sdivun", OP_IMM_REG_REG_REG, 0);
2185
2186 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2187
2188 divide_by = State.regs[ OP[0] ];
2189 divide_this = State.regs[ OP[1] ] << imm5;
2190
2191 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2192
2193 State.regs[ OP[1] ] = quotient;
2194 State.regs[ OP[2] >> 11 ] = remainder;
2195
2196 /* Set condition codes. */
2197 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2198
2199 if (overflow) PSW |= PSW_OV;
2200 if (quotient == 0) PSW |= PSW_Z;
2201 if (quotient & 0x80000000) PSW |= PSW_S;
2202
2203 trace_output (OP_IMM_REG_REG_REG);
2204
2205 return 4;
2206 }
2207
2208 /* sdivn imm5, reg1, reg2, reg3 */
2209 int
2210 OP_1C007E0 (void)
2211 {
2212 signed long int quotient;
2213 signed long int remainder;
2214 signed long int divide_by;
2215 signed long int divide_this;
2216 boolean overflow = false;
2217 unsigned int imm5;
2218
2219 trace_input ("sdivn", OP_IMM_REG_REG_REG, 0);
2220
2221 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2222
2223 divide_by = State.regs[ OP[0] ];
2224 divide_this = State.regs[ OP[1] ] << imm5;
2225
2226 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2227
2228 State.regs[ OP[1] ] = quotient;
2229 State.regs[ OP[2] >> 11 ] = remainder;
2230
2231 /* Set condition codes. */
2232 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2233
2234 if (overflow) PSW |= PSW_OV;
2235 if (quotient == 0) PSW |= PSW_Z;
2236 if (quotient < 0) PSW |= PSW_S;
2237
2238 trace_output (OP_IMM_REG_REG_REG);
2239
2240 return 4;
2241 }
2242
2243 /* sdivhun imm5, reg1, reg2, reg3 */
2244 int
2245 OP_18207E0 (void)
2246 {
2247 unsigned long int quotient;
2248 unsigned long int remainder;
2249 unsigned long int divide_by;
2250 unsigned long int divide_this;
2251 boolean overflow = false;
2252 unsigned int imm5;
2253
2254 trace_input ("sdivhun", OP_IMM_REG_REG_REG, 0);
2255
2256 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2257
2258 divide_by = State.regs[ OP[0] ] & 0xffff;
2259 divide_this = State.regs[ OP[1] ] << imm5;
2260
2261 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2262
2263 State.regs[ OP[1] ] = quotient;
2264 State.regs[ OP[2] >> 11 ] = remainder;
2265
2266 /* Set condition codes. */
2267 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2268
2269 if (overflow) PSW |= PSW_OV;
2270 if (quotient == 0) PSW |= PSW_Z;
2271 if (quotient & 0x80000000) PSW |= PSW_S;
2272
2273 trace_output (OP_IMM_REG_REG_REG);
2274
2275 return 4;
2276 }
2277
2278 /* sdivhn imm5, reg1, reg2, reg3 */
2279 int
2280 OP_18007E0 (void)
2281 {
2282 signed long int quotient;
2283 signed long int remainder;
2284 signed long int divide_by;
2285 signed long int divide_this;
2286 boolean overflow = false;
2287 unsigned int imm5;
2288
2289 trace_input ("sdivhn", OP_IMM_REG_REG_REG, 0);
2290
2291 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2292
2293 divide_by = EXTEND16 (State.regs[ OP[0] ]);
2294 divide_this = State.regs[ OP[1] ] << imm5;
2295
2296 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2297
2298 State.regs[ OP[1] ] = quotient;
2299 State.regs[ OP[2] >> 11 ] = remainder;
2300
2301 /* Set condition codes. */
2302 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2303
2304 if (overflow) PSW |= PSW_OV;
2305 if (quotient == 0) PSW |= PSW_Z;
2306 if (quotient < 0) PSW |= PSW_S;
2307
2308 trace_output (OP_IMM_REG_REG_REG);
2309
2310 return 4;
2311 }
2312
2313 /* end-sanitize-v850eq */
2314 /* start-sanitize-v850e */
2315 /* divu reg1, reg2, reg3 */
2316 int
2317 OP_2C207E0 (void)
2318 {
2319 unsigned long int quotient;
2320 unsigned long int remainder;
2321 unsigned long int divide_by;
2322 unsigned long int divide_this;
2323 boolean overflow = false;
2324
2325 trace_input ("divu", OP_REG_REG_REG, 0);
2326
2327 /* Compute the result. */
2328
2329 divide_by = State.regs[ OP[0] ];
2330 divide_this = State.regs[ OP[1] ];
2331
2332 if (divide_by == 0)
2333 {
2334 overflow = true;
2335 divide_by = 1;
2336 }
2337
2338 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2339 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2340
2341 /* Set condition codes. */
2342 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2343
2344 if (overflow) PSW |= PSW_OV;
2345 if (quotient == 0) PSW |= PSW_Z;
2346 if (quotient & 0x80000000) PSW |= PSW_S;
2347
2348 trace_output (OP_REG_REG_REG);
2349
2350 return 4;
2351 }
2352
2353 /* end-sanitize-v850e */
2354 /* start-sanitize-v850e */
2355 /* div reg1, reg2, reg3 */
2356 int
2357 OP_2C007E0 (void)
2358 {
2359 signed long int quotient;
2360 signed long int remainder;
2361 signed long int divide_by;
2362 signed long int divide_this;
2363 boolean overflow = false;
2364
2365 trace_input ("div", OP_REG_REG_REG, 0);
2366
2367 /* Compute the result. */
2368
2369 divide_by = State.regs[ OP[0] ];
2370 divide_this = State.regs[ OP[1] ];
2371
2372 if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
2373 {
2374 overflow = true;
2375 divide_by = 1;
2376 }
2377
2378 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2379 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2380
2381 /* Set condition codes. */
2382 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2383
2384 if (overflow) PSW |= PSW_OV;
2385 if (quotient == 0) PSW |= PSW_Z;
2386 if (quotient < 0) PSW |= PSW_S;
2387
2388 trace_output (OP_REG_REG_REG);
2389
2390 return 4;
2391 }
2392
2393 /* end-sanitize-v850e */
2394 /* start-sanitize-v850e */
2395 /* divhu reg1, reg2, reg3 */
2396 int
2397 OP_28207E0 (void)
2398 {
2399 unsigned long int quotient;
2400 unsigned long int remainder;
2401 unsigned long int divide_by;
2402 unsigned long int divide_this;
2403 boolean overflow = false;
2404
2405 trace_input ("divhu", OP_REG_REG_REG, 0);
2406
2407 /* Compute the result. */
2408
2409 divide_by = State.regs[ OP[0] ] & 0xffff;
2410 divide_this = State.regs[ OP[1] ];
2411
2412 if (divide_by == 0)
2413 {
2414 overflow = true;
2415 divide_by = 1;
2416 }
2417
2418 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2419 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2420
2421 /* Set condition codes. */
2422 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2423
2424 if (overflow) PSW |= PSW_OV;
2425 if (quotient == 0) PSW |= PSW_Z;
2426 if (quotient & 0x80000000) PSW |= PSW_S;
2427
2428 trace_output (OP_REG_REG_REG);
2429
2430 return 4;
2431 }
2432
2433 /* end-sanitize-v850e */
2434 /* start-sanitize-v850e */
2435 /* divh reg1, reg2, reg3 */
2436 int
2437 OP_28007E0 (void)
2438 {
2439 signed long int quotient;
2440 signed long int remainder;
2441 signed long int divide_by;
2442 signed long int divide_this;
2443 boolean overflow = false;
2444
2445 trace_input ("divh", OP_REG_REG_REG, 0);
2446
2447 /* Compute the result. */
2448
2449 divide_by = State.regs[ OP[0] ];
2450 divide_this = EXTEND16 (State.regs[ OP[1] ]);
2451
2452 if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
2453 {
2454 overflow = true;
2455 divide_by = 1;
2456 }
2457
2458 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2459 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2460
2461 /* Set condition codes. */
2462 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2463
2464 if (overflow) PSW |= PSW_OV;
2465 if (quotient == 0) PSW |= PSW_Z;
2466 if (quotient < 0) PSW |= PSW_S;
2467
2468 trace_output (OP_REG_REG_REG);
2469
2470 return 4;
2471 }
2472
2473 /* end-sanitize-v850e */
2474 /* start-sanitize-v850e */
2475 /* mulu imm9, reg2, reg3 */
2476 int
2477 OP_24207E0 (void)
2478 {
2479 trace_input ("mulu", OP_IMM_REG_REG, 0);
2480
2481 Multiply64 (false, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
2482
2483 trace_output (OP_IMM_REG_REG);
2484
2485 return 4;
2486 }
2487
2488 /* end-sanitize-v850e */
2489 /* start-sanitize-v850e */
2490 /* mul imm9, reg2, reg3 */
2491 int
2492 OP_24007E0 (void)
2493 {
2494 trace_input ("mul", OP_IMM_REG_REG, 0);
2495
2496 Multiply64 (true, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
2497
2498 trace_output (OP_IMM_REG_REG);
2499
2500 return 4;
2501 }
2502
2503 /* end-sanitize-v850e */
2504 /* start-sanitize-v850e */
2505 /* ld.hu */
2506 int
2507 OP_107E0 (void)
2508 {
2509 int adr;
2510
2511 trace_input ("ld.hu", OP_LOAD32, 2);
2512
2513 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
2514 adr &= ~0x1;
2515
2516 State.regs[ OP[1] ] = load_mem (adr, 2);
2517
2518 trace_output (OP_LOAD32);
2519
2520 return 4;
2521 }
2522
2523 /* end-sanitize-v850e */
2524 /* start-sanitize-v850e */
2525 /* ld.bu */
2526 int
2527 OP_10780 (void)
2528 {
2529 int adr;
2530
2531 trace_input ("ld.bu", OP_LOAD32, 1);
2532
2533 adr = (State.regs[ OP[0] ]
2534 + (EXTEND16 (OP[2] & ~1) | ((OP[3] >> 5) & 1)));
2535
2536 State.regs[ OP[1] ] = load_mem (adr, 1);
2537
2538 trace_output (OP_LOAD32);
2539
2540 return 4;
2541 }
2542
2543 /* prepare list12, imm5, imm32 */
2544 int
2545 OP_1B0780 (void)
2546 {
2547 int i;
2548
2549 trace_input ("prepare", OP_PUSHPOP1, 0);
2550
2551 /* Store the registers with lower number registers being placed at higher addresses. */
2552 for (i = 0; i < 12; i++)
2553 if ((OP[3] & (1 << type1_regs[ i ])))
2554 {
2555 SP -= 4;
2556 store_mem (SP, 4, State.regs[ 20 + i ]);
2557 }
2558
2559 SP -= (OP[3] & 0x3e) << 1;
2560
2561 EP = load_mem (PC + 4, 4);
2562
2563 trace_output (OP_PUSHPOP1);
2564
2565 return 8;
2566 }
2567
2568 /* prepare list12, imm5, imm16-32 */
2569 int
2570 OP_130780 (void)
2571 {
2572 int i;
2573
2574 trace_input ("prepare", OP_PUSHPOP1, 0);
2575
2576 /* Store the registers with lower number registers being placed at higher addresses. */
2577 for (i = 0; i < 12; i++)
2578 if ((OP[3] & (1 << type1_regs[ i ])))
2579 {
2580 SP -= 4;
2581 store_mem (SP, 4, State.regs[ 20 + i ]);
2582 }
2583
2584 SP -= (OP[3] & 0x3e) << 1;
2585
2586 EP = load_mem (PC + 4, 2) << 16;
2587
2588 trace_output (OP_PUSHPOP1);
2589
2590 return 6;
2591 }
2592
2593 /* prepare list12, imm5, imm16 */
2594 int
2595 OP_B0780 (void)
2596 {
2597 int i;
2598
2599 trace_input ("prepare", OP_PUSHPOP1, 0);
2600
2601 /* Store the registers with lower number registers being placed at higher addresses. */
2602 for (i = 0; i < 12; i++)
2603 if ((OP[3] & (1 << type1_regs[ i ])))
2604 {
2605 SP -= 4;
2606 store_mem (SP, 4, State.regs[ 20 + i ]);
2607 }
2608
2609 SP -= (OP[3] & 0x3e) << 1;
2610
2611 EP = EXTEND16 (load_mem (PC + 4, 2));
2612
2613 trace_output (OP_PUSHPOP1);
2614
2615 return 6;
2616 }
2617
2618 /* prepare list12, imm5, sp */
2619 int
2620 OP_30780 (void)
2621 {
2622 int i;
2623
2624 trace_input ("prepare", OP_PUSHPOP1, 0);
2625
2626 /* Store the registers with lower number registers being placed at higher addresses. */
2627 for (i = 0; i < 12; i++)
2628 if ((OP[3] & (1 << type1_regs[ i ])))
2629 {
2630 SP -= 4;
2631 store_mem (SP, 4, State.regs[ 20 + i ]);
2632 }
2633
2634 SP -= (OP[3] & 0x3e) << 1;
2635
2636 EP = SP;
2637
2638 trace_output (OP_PUSHPOP1);
2639
2640 return 4;
2641 }
2642
2643 /* end-sanitize-v850e */
2644 /* start-sanitize-v850e */
2645 /* mul reg1, reg2, reg3 */
2646 int
2647 OP_22007E0 (void)
2648 {
2649 trace_input ("mul", OP_REG_REG_REG, 0);
2650
2651 Multiply64 (true, State.regs[ OP[0] ]);
2652
2653 trace_output (OP_REG_REG_REG);
2654
2655 return 4;
2656 }
2657
2658 /* end-sanitize-v850e */
2659 /* start-sanitize-v850eq */
2660
2661 /* popmh list18 */
2662 int
2663 OP_307F0 (void)
2664 {
2665 int i;
2666
2667 trace_input ("popmh", OP_PUSHPOP2, 0);
2668
2669 if (OP[3] & (1 << 19))
2670 {
2671 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2672 {
2673 FEPSW = load_mem ( SP & ~ 3, 4);
2674 FEPC = load_mem ((SP + 4) & ~ 3, 4);
2675 }
2676 else
2677 {
2678 EIPSW = load_mem ( SP & ~ 3, 4);
2679 EIPC = load_mem ((SP + 4) & ~ 3, 4);
2680 }
2681
2682 SP += 8;
2683 }
2684
2685 /* Load the registers with lower number registers being retrieved from higher addresses. */
2686 for (i = 16; i--;)
2687 if ((OP[3] & (1 << type2_regs[ i ])))
2688 {
2689 State.regs[ i + 16 ] = load_mem (SP & ~ 3, 4);
2690 SP += 4;
2691 }
2692
2693 trace_output (OP_PUSHPOP2);
2694
2695 return 4;
2696 }
2697
2698 /* popml lsit18 */
2699 int
2700 OP_107F0 (void)
2701 {
2702 int i;
2703
2704 trace_input ("popml", OP_PUSHPOP3, 0);
2705
2706 if (OP[3] & (1 << 19))
2707 {
2708 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2709 {
2710 FEPSW = load_mem ( SP & ~ 3, 4);
2711 FEPC = load_mem ((SP + 4) & ~ 3, 4);
2712 }
2713 else
2714 {
2715 EIPSW = load_mem ( SP & ~ 3, 4);
2716 EIPC = load_mem ((SP + 4) & ~ 3, 4);
2717 }
2718
2719 SP += 8;
2720 }
2721
2722 if (OP[3] & (1 << 3))
2723 {
2724 PSW = load_mem (SP & ~ 3, 4);
2725 SP += 4;
2726 }
2727
2728 /* Load the registers with lower number registers being retrieved from higher addresses. */
2729 for (i = 15; i--;)
2730 if ((OP[3] & (1 << type3_regs[ i ])))
2731 {
2732 State.regs[ i + 1 ] = load_mem (SP & ~ 3, 4);
2733 SP += 4;
2734 }
2735
2736 trace_output (OP_PUSHPOP2);
2737
2738 return 4;
2739 }
2740
2741 /* pushmh list18 */
2742 int
2743 OP_307E0 (void)
2744 {
2745 int i;
2746
2747 trace_input ("pushmh", OP_PUSHPOP2, 0);
2748
2749 /* Store the registers with lower number registers being placed at higher addresses. */
2750 for (i = 0; i < 16; i++)
2751 if ((OP[3] & (1 << type2_regs[ i ])))
2752 {
2753 SP -= 4;
2754 store_mem (SP & ~ 3, 4, State.regs[ i + 16 ]);
2755 }
2756
2757 if (OP[3] & (1 << 19))
2758 {
2759 SP -= 8;
2760
2761 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2762 {
2763 store_mem ((SP + 4) & ~ 3, 4, FEPC);
2764 store_mem ( SP & ~ 3, 4, FEPSW);
2765 }
2766 else
2767 {
2768 store_mem ((SP + 4) & ~ 3, 4, EIPC);
2769 store_mem ( SP & ~ 3, 4, EIPSW);
2770 }
2771 }
2772
2773 trace_output (OP_PUSHPOP2);
2774
2775 return 4;
2776 }
2777
2778 /* end-sanitize-v850eq */
GDB Binutils - Deliverables
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