sim/v850/simops.c

   1 #include <signal.h>
   2 #include "v850_sim.h"
   3 #include "simops.h"
   4
   5 void
   6 OP_10760 ()
   7 {
   8 }
   9
  10 void
  11 OP_C7C0 ()
  12 {
  13 }
  14
  15 void
  16 OP_760 ()
  17 {
  18 }
  19
  20 /* bv disp9 */
  21 void
  22 OP_580 ()
  23 {
  24   unsigned int op0, psw;
  25   int temp;
  26
  27   temp = (State.regs[OP[0]] << 23) >> 23;
  28   op0 = temp;
  29   psw = State.psw;
  30
  31   if ((psw & PSW_OV) != 0)
  32     State.pc += op0;
  33   else
  34     State.pc += 2;
  35 }
  36
  37 /* bl disp9 */
  38 void
  39 OP_581 ()
  40 {
  41   unsigned int op0, psw;
  42   int temp;
  43
  44   temp = (State.regs[OP[0]] << 23) >> 23;
  45   op0 = temp;
  46   psw = State.psw;
  47
  48   if ((psw & PSW_CY) != 0)
  49     State.pc += op0;
  50   else
  51     State.pc += 2;
  52 }
  53
  54 /* be disp9 */
  55 void
  56 OP_582 ()
  57 {
  58   unsigned int op0, psw;
  59   int temp;
  60
  61   temp = (State.regs[OP[0]] << 23) >> 23;
  62   op0 = temp;
  63   psw = State.psw;
  64
  65   if ((psw & PSW_Z) != 0)
  66     State.pc += op0;
  67   else
  68     State.pc += 2;
  69 }
  70
  71 /* bnh disp 9*/
  72 void
  73 OP_583 ()
  74 {
  75   unsigned int op0, psw;
  76   int temp;
  77
  78   temp = (State.regs[OP[0]] << 23) >> 23;
  79   op0 = temp;
  80   psw = State.psw;
  81
  82   if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0)
  83     State.pc += op0;
  84   else
  85     State.pc += 2;
  86 }
  87
  88 /* bn disp9 */
  89 void
  90 OP_584 ()
  91 {
  92   unsigned int op0, psw;
  93   int temp;
  94
  95   temp = (State.regs[OP[0]] << 23) >> 23;
  96   op0 = temp;
  97   psw = State.psw;
  98
  99   if ((psw & PSW_S) != 0)
 100     State.pc += op0;
 101   else
 102     State.pc += 2;
 103 }
 104
 105 /* br disp9 */
 106 void
 107 OP_585 ()
 108 {
 109   unsigned int op0;
 110   int temp;
 111
 112   temp = (State.regs[OP[0]] << 23) >> 23;
 113   op0 = temp;
 114   State.pc += op0;
 115 }
 116
 117 /* blt disp9 */
 118 void
 119 OP_586 ()
 120 {
 121   unsigned int op0, psw;
 122   int temp;
 123
 124   temp = (State.regs[OP[0]] << 23) >> 23;
 125   op0 = temp;
 126   psw = State.psw;
 127
 128   if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0)
 129     State.pc += op0;
 130   else
 131     State.pc += 2;
 132 }
 133
 134 /* ble disp9 */
 135 void
 136 OP_587 ()
 137 {
 138   unsigned int op0, psw;
 139   int temp;
 140
 141   temp = (State.regs[OP[0]] << 23) >> 23;
 142   op0 = temp;
 143   psw = State.psw;
 144
 145   if ((((psw & PSW_Z) != 0)
 146        || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) != 0)
 147     State.pc += op0;
 148   else
 149     State.pc += 2;
 150 }
 151
 152 /* bnv disp9 */
 153 void
 154 OP_588 ()
 155 {
 156   unsigned int op0, psw;
 157   int temp;
 158
 159   temp = (State.regs[OP[0]] << 23) >> 23;
 160   op0 = temp;
 161   psw = State.psw;
 162
 163   if ((psw & PSW_OV) == 0)
 164     State.pc += op0;
 165   else
 166     State.pc += 2;
 167 }
 168
 169 /* bnl disp9 */
 170 void
 171 OP_589 ()
 172 {
 173   unsigned int op0, psw;
 174   int temp;
 175
 176   temp = (State.regs[OP[0]] << 23) >> 23;
 177   op0 = temp;
 178   psw = State.psw;
 179
 180   if ((psw & PSW_CY) == 0)
 181     State.pc += op0;
 182   else
 183     State.pc += 2;
 184 }
 185
 186 /* bne disp9 */
 187 void
 188 OP_58A ()
 189 {
 190   unsigned int op0, psw;
 191   int temp;
 192
 193   temp = (State.regs[OP[0]] << 23) >> 23;
 194   op0 = temp;
 195   psw = State.psw;
 196
 197   if ((psw & PSW_Z) == 0)
 198     State.pc += op0;
 199   else
 200     State.pc += 2;
 201 }
 202
 203 /* bh disp9 */
 204 void
 205 OP_58B ()
 206 {
 207   unsigned int op0, psw;
 208   int temp;
 209
 210   temp = (State.regs[OP[0]] << 23) >> 23;
 211   op0 = temp;
 212   psw = State.psw;
 213
 214   if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0)
 215     State.pc += op0;
 216   else
 217     State.pc += 2;
 218 }
 219
 220 /* bp disp9 */
 221 void
 222 OP_58C ()
 223 {
 224   unsigned int op0, psw;
 225   int temp;
 226
 227   temp = (State.regs[OP[0]] << 23) >> 23;
 228   op0 = temp;
 229   psw = State.psw;
 230
 231   if ((psw & PSW_S) == 0)
 232     State.pc += op0;
 233   else
 234     State.pc += 2;
 235 }
 236
 237 /* bsa disp9 */
 238 void
 239 OP_58D ()
 240 {
 241   unsigned int op0, psw;
 242   int temp;
 243
 244   temp = (State.regs[OP[0]] << 23) >> 23;
 245   op0 = temp;
 246   psw = State.psw;
 247
 248   if ((psw & PSW_SAT) != 0)
 249     State.pc += op0;
 250   else
 251     State.pc += 2;
 252 }
 253
 254 /* bge disp9 */
 255 void
 256 OP_58E ()
 257 {
 258   unsigned int op0, psw;
 259   int temp;
 260
 261   temp = (State.regs[OP[0]] << 23) >> 23;
 262   op0 = temp;
 263   psw = State.psw;
 264
 265   if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0)
 266     State.pc += op0;
 267   else
 268     State.pc += 2;
 269 }
 270
 271 /* bgt disp9 */
 272 void
 273 OP_58F ()
 274 {
 275   unsigned int op0, psw;
 276   int temp;
 277
 278   temp = (State.regs[OP[0]] << 23) >> 23;
 279   op0 = temp;
 280   psw = State.psw;
 281
 282   if ((((psw & PSW_Z) != 0)
 283        || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) == 0)
 284     State.pc += op0;
 285   else
 286     State.pc += 2;
 287 }
 288
 289 /* jmp [reg1] */
 290 void
 291 OP_60 ()
 292 {
 293   /* interp.c will bump this by +2, so correct for it here.  */
 294   State.pc = State.regs[OP[0]] - 2;
 295 }
 296
 297 /* jarl disp22, reg */
 298 void
 299 OP_780 ()
 300 {
 301   unsigned int op0, opc;
 302   int temp;
 303
 304   temp = OP[0];
 305   temp = (temp << 10) >> 10;
 306   op0 = temp;
 307   opc = State.pc;
 308
 309   State.pc += temp;
 310
 311   /* Gross.  jarl X,r0 is really jr and doesn't save its result.  */
 312   if (OP[1] != 0)
 313     State.regs[OP[1]] = opc + 4;
 314 }
 315
 316 /* add reg, reg */
 317 void
 318 OP_1C0 ()
 319 {
 320   unsigned int op0, op1, result, z, s, cy, ov;
 321
 322   /* Compute the result.  */
 323   op0 = State.regs[OP[0]];
 324   op1 = State.regs[OP[1]];
 325   result = op0 + op1;
 326
 327   /* Compute the condition codes.  */
 328   z = (result == 0);
 329   s = (result & 0x80000000);
 330   cy = (result < op0 || result < op1);
 331   ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
 332         && (op0 & 0x80000000) != (result & 0x80000000));
 333
 334   /* Store the result and condition codes.  */
 335   State.regs[OP[1]] = result;
 336   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 337   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 338                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 339 }
 340
 341 /* add sign_extend(imm5), reg */
 342 void
 343 OP_240 ()
 344 {
 345   unsigned int op0, op1, result, z, s, cy, ov;
 346   int temp;
 347
 348   /* Compute the result.  */
 349   temp = (OP[0] & 0x1f);
 350   temp = (temp << 27) >> 27;
 351   op0 = temp;
 352   op1 = State.regs[OP[1]];
 353   result = op0 + op1;
 354
 355   /* Compute the condition codes.  */
 356   z = (result == 0);
 357   s = (result & 0x80000000);
 358   cy = (result < op0 || result < op1);
 359   ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
 360         && (op0 & 0x80000000) != (result & 0x80000000));
 361
 362   /* Store the result and condition codes.  */
 363   State.regs[OP[1]] = result;
 364   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 365   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 366                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 367 }
 368
 369 /* addi sign_extend(imm16), reg, reg */
 370 void
 371 OP_600 ()
 372 {
 373   unsigned int op0, op1, result, z, s, cy, ov;
 374   int temp;
 375
 376   /* Compute the result.  */
 377   temp = (OP[0] & 0xffff);
 378   temp = (temp << 16) >> 16;
 379   op0 = temp;
 380   op1 = State.regs[OP[1]];
 381   result = op0 + op1;
 382
 383   /* Compute the condition codes.  */
 384   z = (result == 0);
 385   s = (result & 0x80000000);
 386   cy = (result < op0 || result < op1);
 387   ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
 388         && (op0 & 0x80000000) != (result & 0x80000000));
 389
 390   /* Store the result and condition codes.  */
 391   State.regs[OP[2]] = result;
 392   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 393   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 394                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 395 }
 396
 397 /* sub reg1, reg2 */
 398 void
 399 OP_1A0 ()
 400 {
 401   unsigned int op0, op1, result, z, s, cy, ov;
 402
 403   /* Compute the result.  */
 404   op0 = State.regs[OP[0]];
 405   op1 = State.regs[OP[1]];
 406   result = op1 - op0;
 407
 408   /* Compute the condition codes.  */
 409   z = (result == 0);
 410   s = (result & 0x80000000);
 411   cy = (result < -op0);
 412   ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
 413         && (op1 & 0x80000000) != (result & 0x80000000));
 414
 415   /* Store the result and condition codes.  */
 416   State.regs[OP[1]] = result;
 417   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 418   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 419                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 420 }
 421
 422 /* subr reg1, reg2 */
 423 void
 424 OP_180 ()
 425 {
 426   unsigned int op0, op1, result, z, s, cy, ov;
 427
 428   /* Compute the result.  */
 429   op0 = State.regs[OP[0]];
 430   op1 = State.regs[OP[1]];
 431   result = op0 - op1;
 432
 433   /* Compute the condition codes.  */
 434   z = (result == 0);
 435   s = (result & 0x80000000);
 436   cy = (result < -op1);
 437   ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
 438         && (op0 & 0x80000000) != (result & 0x80000000));
 439
 440   /* Store the result and condition codes.  */
 441   State.regs[OP[1]] = result;
 442   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 443   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 444                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 445 }
 446
 447 /* mulh reg1, reg2 */
 448 void
 449 OP_E0 ()
 450 {
 451   State.regs[OP[1]] = ((State.regs[OP[1]] & 0xffff)
 452                        * (State.regs[OP[0]] & 0xffff));
 453 }
 454
 455 /* mulh sign_extend(imm5), reg2
 456
 457    Condition codes */
 458 void
 459 OP_2E0 ()
 460 {
 461   int value = OP[0];
 462
 463   value = (value << 27) >> 27;
 464
 465   State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value;
 466 }
 467
 468 /* mulhi imm16, reg1, reg2 */
 469 void
 470 OP_6E0 ()
 471 {
 472   int value = OP[0];
 473
 474   value = value & 0xffff;
 475
 476   State.regs[OP[2]] = (State.regs[OP[1]] & 0xffff) * value;
 477 }
 478
 479 /* divh reg1, reg2 */
 480 void
 481 OP_40 ()
 482 {
 483   unsigned int op0, op1, result, z, s, cy, ov;
 484   int temp;
 485
 486   /* Compute the result.  */
 487   temp = State.regs[OP[0]] & 0xffff;
 488   temp = (temp << 16) >> 16;
 489   op0 = temp;
 490   op1 = State.regs[OP[1]];
 491
 492   if (op0 == 0xffffffff && op1 == 0x80000000)
 493     {
 494       result = 0x80000000;
 495       ov = 1;
 496     }
 497   else if (op0 != 0)
 498     {
 499       result = op1 / op0;
 500       ov = 0;
 501     }
 502   else
 503     ov = 1;
 504
 505   /* Compute the condition codes.  */
 506   z = (result == 0);
 507   s = (result & 0x80000000);
 508
 509   /* Store the result and condition codes.  */
 510   State.regs[OP[1]] = result;
 511   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
 512   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 513                 | (ov ? PSW_OV : 0));
 514 }
 515
 516 /* cmp reg, reg */
 517 void
 518 OP_1E0 ()
 519 {
 520   unsigned int op0, op1, result, z, s, cy, ov;
 521
 522   /* Compute the result.  */
 523   op0 = State.regs[OP[0]];
 524   op1 = State.regs[OP[1]];
 525   result = op1 - op0;
 526
 527   /* Compute the condition codes.  */
 528   z = (result == 0);
 529   s = (result & 0x80000000);
 530   cy = (result < -op0);
 531   ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
 532         && (op1 & 0x80000000) != (result & 0x80000000));
 533
 534   /* Set condition codes.  */
 535   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 536   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 537                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 538 }
 539
 540 /* cmp sign_extend(imm5), reg */
 541 void
 542 OP_260 ()
 543 {
 544   unsigned int op0, op1, result, z, s, cy, ov;
 545   int temp;
 546
 547   /* Compute the result.  */
 548   temp = OP[0];
 549   temp = (temp << 27) >> 27;
 550   op0 = temp;
 551   op1 = State.regs[OP[1]];
 552   result = op1 - op0;
 553
 554   /* Compute the condition codes.  */
 555   z = (result == 0);
 556   s = (result & 0x80000000);
 557   cy = (result < -op0);
 558   ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
 559         && (op1 & 0x80000000) != (result & 0x80000000));
 560
 561   /* Set condition codes.  */
 562   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 563   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 564                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 565 }
 566
 567 /* setf cccc,reg2 */
 568 void
 569 OP_7E0 ()
 570 {
 571   /* Hack alert.  We turn off a bit in op0 since we really only
 572      wanted 4 bits.  */
 573   unsigned int op0, psw, result;
 574
 575   op0 = OP[0] & 0xf;
 576   psw = State.psw;
 577
 578   switch (op0)
 579     {
 580       case 0x0:
 581         result = ((psw & PSW_OV) != 0);
 582         break;
 583       case 0x1:
 584         result = ((psw & PSW_CY) != 0);
 585         break;
 586       case 0x2:
 587         result = ((psw & PSW_Z) != 0);
 588         break;
 589       case 0x3:
 590         result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
 591         break;
 592       case 0x4:
 593         result = ((psw & PSW_S) != 0);
 594         break;
 595       case 0x5:
 596         result = 1;
 597         break;
 598       case 0x6:
 599         result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
 600         break;
 601       case 0x7:
 602         result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
 603                   || ((psw & PSW_Z) != 0)) != 0);
 604         break;
 605       case 0x8:
 606         result = ((psw & PSW_OV) == 0);
 607         break;
 608       case 0x9:
 609         result = ((psw & PSW_CY) == 0);
 610         break;
 611       case 0xa:
 612         result = ((psw & PSW_Z) == 0);
 613         break;
 614       case 0xb:
 615         result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
 616         break;
 617       case 0xc:
 618         result = ((psw & PSW_S) == 0);
 619         break;
 620       case 0xd:
 621         result = ((psw & PSW_SAT) != 0);
 622         break;
 623       case 0xe:
 624         result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
 625         break;
 626       case 0xf:
 627         result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
 628                   || ((psw & PSW_Z) != 0)) == 0);
 629         break;
 630     }
 631
 632   State.regs[OP[1]] = result;
 633 }
 634
 635 /* satadd reg,reg */
 636 void
 637 OP_C0 ()
 638 {
 639   unsigned int op0, op1, result, z, s, cy, ov, sat;
 640
 641   /* Compute the result.  */
 642   op0 = State.regs[OP[0]];
 643   op1 = State.regs[OP[1]];
 644   result = op0 + op1;
 645
 646   /* Compute the condition codes.  */
 647   z = (result == 0);
 648   s = (result & 0x80000000);
 649   cy = (result < op0 || result < op1);
 650   ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
 651         && (op0 & 0x80000000) != (result & 0x80000000));
 652   sat = ov;
 653
 654   /* Store the result and condition codes.  */
 655   State.regs[OP[1]] = result;
 656   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 657   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 658                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
 659                 | (sat ? PSW_SAT : 0));
 660
 661   /* Handle saturated results.  */
 662   if (sat && (op0 & 0x80000000))
 663     State.regs[OP[1]] = 0x80000000;
 664   else if (sat)
 665     State.regs[OP[1]] = 0x7fffffff;
 666 }
 667
 668 /* satadd sign_extend(imm5), reg */
 669 void
 670 OP_220 ()
 671 {
 672   unsigned int op0, op1, result, z, s, cy, ov, sat;
 673
 674   int temp;
 675
 676   /* Compute the result.  */
 677   temp = (OP[0] & 0x1f);
 678   temp = (temp << 27) >> 27;
 679   op0 = temp;
 680   op1 = State.regs[OP[1]];
 681   result = op0 + op1;
 682
 683   /* Compute the condition codes.  */
 684   z = (result == 0);
 685   s = (result & 0x80000000);
 686   cy = (result < op0 || result < op1);
 687   ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
 688         && (op0 & 0x80000000) != (result & 0x80000000));
 689   sat = ov;
 690
 691   /* Store the result and condition codes.  */
 692   State.regs[OP[1]] = result;
 693   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 694   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 695                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
 696                 | (sat ? PSW_SAT : 0));
 697
 698   /* Handle saturated results.  */
 699   if (sat && (op0 & 0x80000000))
 700     State.regs[OP[1]] = 0x80000000;
 701   else if (sat)
 702     State.regs[OP[1]] = 0x7fffffff;
 703 }
 704
 705 /* satsub reg1, reg2 */
 706 void
 707 OP_A0 ()
 708 {
 709   unsigned int op0, op1, result, z, s, cy, ov, sat;
 710
 711   /* Compute the result.  */
 712   op0 = State.regs[OP[0]];
 713   op1 = State.regs[OP[1]];
 714   result = op1 - op0;
 715
 716   /* Compute the condition codes.  */
 717   z = (result == 0);
 718   s = (result & 0x80000000);
 719   cy = (result < -op0);
 720   ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
 721         && (op1 & 0x80000000) != (result & 0x80000000));
 722   sat = ov;
 723
 724   /* Store the result and condition codes.  */
 725   State.regs[OP[1]] = result;
 726   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 727   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 728                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
 729                 | (sat ? PSW_SAT : 0));
 730
 731   /* Handle saturated results.  */
 732   if (sat && (op1 & 0x80000000))
 733     State.regs[OP[1]] = 0x80000000;
 734   else if (sat)
 735     State.regs[OP[1]] = 0x7fffffff;
 736 }
 737
 738 /* satsubi sign_extend(imm16), reg */
 739 void
 740 OP_660 ()
 741 {
 742   unsigned int op0, op1, result, z, s, cy, ov, sat;
 743   int temp;
 744
 745   /* Compute the result.  */
 746   temp = (OP[0] & 0xffff);
 747   temp = (temp << 16) >> 16;
 748   op0 = temp;
 749   op1 = State.regs[OP[1]];
 750   result = op1 - op0;
 751
 752   /* Compute the condition codes.  */
 753   z = (result == 0);
 754   s = (result & 0x80000000);
 755   cy = (result < -op0);
 756   ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
 757         && (op1 & 0x80000000) != (result & 0x80000000));
 758   sat = ov;
 759
 760   /* Store the result and condition codes.  */
 761   State.regs[OP[1]] = result;
 762   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 763   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 764                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
 765                 | (sat ? PSW_SAT : 0));
 766
 767   /* Handle saturated results.  */
 768   if (sat && (op1 & 0x80000000))
 769     State.regs[OP[1]] = 0x80000000;
 770   else if (sat)
 771     State.regs[OP[1]] = 0x7fffffff;
 772 }
 773
 774 void
 775 OP_80 ()
 776 {
 777   unsigned int op0, op1, result, z, s, cy, ov, sat;
 778
 779   /* Compute the result.  */
 780   op0 = State.regs[OP[0]];
 781   op1 = State.regs[OP[1]];
 782   result = op0 - op1;
 783
 784   /* Compute the condition codes.  */
 785   z = (result == 0);
 786   s = (result & 0x80000000);
 787   cy = (result < -op0);
 788   ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
 789         && (op1 & 0x80000000) != (result & 0x80000000));
 790   sat = ov;
 791
 792   /* Store the result and condition codes.  */
 793   State.regs[OP[1]] = result;
 794   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 795   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 796                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
 797                 | (sat ? PSW_SAT : 0));
 798
 799   /* Handle saturated results.  */
 800   if (sat && (op0 & 0x80000000))
 801     State.regs[OP[1]] = 0x80000000;
 802   else if (sat)
 803     State.regs[OP[1]] = 0x7fffffff;
 804 }
 805
 806 /* tst reg,reg */
 807 void
 808 OP_160 ()
 809 {
 810   unsigned int op0, op1, result, z, s, cy, ov;
 811
 812   /* Compute the result.  */
 813   op0 = State.regs[OP[0]];
 814   op1 = State.regs[OP[1]];
 815   result = op0 & op1;
 816
 817   /* Compute the condition codes.  */
 818   z = (result == 0);
 819   s = (result & 0x80000000);
 820
 821   /* Store the condition codes.  */
 822   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
 823   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
 824 }
 825
 826 void
 827 OP_10720 ()
 828 {
 829 }
 830
 831 void
 832 OP_720 ()
 833 {
 834 }
 835
 836 void
 837 OP_87C0 ()
 838 {
 839 }
 840
 841 void
 842 OP_300 ()
 843 {
 844 }
 845
 846 /* mov reg, reg */
 847 void
 848 OP_0 ()
 849 {
 850   State.regs[OP[1]] = State.regs[OP[0]];
 851 }
 852
 853 /* mov sign_extend(imm5), reg */
 854 void
 855 OP_200 ()
 856 {
 857   int value = OP[0];
 858
 859   value = (value << 27) >> 27;
 860   State.regs[OP[1]] = value;
 861 }
 862
 863 /* movea sign_extend(imm16), reg, reg  */
 864
 865 void
 866 OP_620 ()
 867 {
 868   int value = OP[0];
 869
 870   value = (value << 16) >> 16;
 871
 872   State.regs[OP[2]] = State.regs[OP[1]] + value;
 873 }
 874
 875 /* movhi imm16, reg, reg */
 876 void
 877 OP_640 ()
 878 {
 879   int value = OP[0];
 880
 881   value = (value & 0xffff) << 16;
 882
 883   State.regs[OP[2]] = State.regs[OP[1]] + value;
 884 }
 885
 886 void
 887 OP_7C0 ()
 888 {
 889 }
 890
 891 void
 892 OP_1687E0 ()
 893 {
 894 }
 895
 896 void
 897 OP_740 ()
 898 {
 899 }
 900
 901 /* sar zero_extend(imm5),reg1 */
 902 void
 903 OP_2A0 ()
 904 {
 905   unsigned int op0, op1, result, z, s, cy, ov;
 906
 907   op0 = OP[0] & 0x1f;
 908   op1 = State.regs[OP[1]];
 909   result = (signed)op1 >> op0;
 910
 911   /* Compute the condition codes.  */
 912   z = (result == 0);
 913   s = (result & 0x80000000);
 914   cy = (op1 & (1 << (op0 - 1)));
 915
 916   /* Store the result and condition codes.  */
 917   State.regs[OP[1]] = result;
 918   State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
 919   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 920                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 921 }
 922
 923 /* sar reg1, reg2 */
 924 void
 925 OP_A007E0 ()
 926 {
 927   unsigned int op0, op1, result, z, s, cy, ov;
 928
 929   op0 = State.regs[OP[0]] & 0x1f;
 930   op1 = State.regs[OP[1]];
 931   result = (signed)op1 >> op0;
 932
 933   /* Compute the condition codes.  */
 934   z = (result == 0);
 935   s = (result & 0x80000000);
 936   cy = (op1 & (1 << (op0 - 1)));
 937
 938   /* Store the result and condition codes.  */
 939   State.regs[OP[1]] = result;
 940   State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
 941   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 942                 | (cy ? PSW_CY : 0));
 943 }
 944
 945 /* shl zero_extend(imm5),reg1 */
 946 void
 947 OP_2C0 ()
 948 {
 949   unsigned int op0, op1, result, z, s, cy, ov;
 950
 951   op0 = OP[0] & 0x1f;
 952   op1 = State.regs[OP[1]];
 953   result = op1 << op0;
 954
 955   /* Compute the condition codes.  */
 956   z = (result == 0);
 957   s = (result & 0x80000000);
 958   cy = (op1 & (1 << (32 - op0)));
 959
 960   /* Store the result and condition codes.  */
 961   State.regs[OP[1]] = result;
 962   State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
 963   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 964                 | (cy ? PSW_CY : 0));
 965 }
 966
 967 /* shl reg1, reg2 */
 968 void
 969 OP_C007E0 ()
 970 {
 971   unsigned int op0, op1, result, z, s, cy, ov;
 972
 973   op0 = State.regs[OP[0]] & 0x1f;
 974   op1 = State.regs[OP[1]];
 975   result = op1 << op0;
 976
 977   /* Compute the condition codes.  */
 978   z = (result == 0);
 979   s = (result & 0x80000000);
 980   cy = (op1 & (1 << (32 - op0)));
 981
 982   /* Store the result and condition codes.  */
 983   State.regs[OP[1]] = result;
 984   State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
 985   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 986                 | (cy ? PSW_CY : 0));
 987 }
 988
 989 /* shr zero_extend(imm5),reg1 */
 990 void
 991 OP_280 ()
 992 {
 993   unsigned int op0, op1, result, z, s, cy, ov;
 994
 995   op0 = OP[0] & 0x1f;
 996   op1 = State.regs[OP[1]];
 997   result = op1 >> op0;
 998
 999   /* Compute the condition codes.  */
1000   z = (result == 0);
1001   s = (result & 0x80000000);
1002   cy = (op1 & (1 << (op0 - 1)));
1003
1004   /* Store the result and condition codes.  */
1005   State.regs[OP[1]] = result;
1006   State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1007   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1008                 | (cy ? PSW_CY : 0));
1009 }
1010
1011 /* shr reg1, reg2 */
1012 void
1013 OP_8007E0 ()
1014 {
1015   unsigned int op0, op1, result, z, s, cy, ov;
1016
1017   op0 = State.regs[OP[0]] & 0x1f;
1018   op1 = State.regs[OP[1]];
1019   result = op1 >> op0;
1020
1021   /* Compute the condition codes.  */
1022   z = (result == 0);
1023   s = (result & 0x80000000);
1024   cy = (op1 & (1 << (op0 - 1)));
1025
1026   /* Store the result and condition codes.  */
1027   State.regs[OP[1]] = result;
1028   State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1029   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1030                 | (cy ? PSW_CY : 0));
1031 }
1032
1033 void
1034 OP_500 ()
1035 {
1036 }
1037
1038 void
1039 OP_47C0 ()
1040 {
1041 }
1042
1043 /* or reg, reg */
1044 void
1045 OP_100 ()
1046 {
1047   unsigned int op0, op1, result, z, s, cy, ov;
1048
1049   /* Compute the result.  */
1050   op0 = State.regs[OP[0]];
1051   op1 = State.regs[OP[1]];
1052   result = op0 | op1;
1053
1054   /* Compute the condition codes.  */
1055   z = (result == 0);
1056   s = (result & 0x80000000);
1057
1058   /* Store the result and condition codes.  */
1059   State.regs[OP[1]] = result;
1060   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
1061   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1062 }
1063
1064 /* ori zero_extend(imm16), reg, reg */
1065 void
1066 OP_680 ()
1067 {
1068   unsigned int op0, op1, result, z, s, cy, ov;
1069
1070   op0 = OP[0] & 0xffff;
1071   op1 = State.regs[OP[1]];
1072   result = op0 | op1;
1073
1074   /* Compute the condition codes.  */
1075   z = (result == 0);
1076   s = (result & 0x80000000);
1077
1078   /* Store the result and condition codes.  */
1079   State.regs[OP[2]] = result;
1080   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
1081   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1082 }
1083
1084 /* and reg, reg */
1085 void
1086 OP_140 ()
1087 {
1088   unsigned int op0, op1, result, z, s, cy, ov;
1089
1090   /* Compute the result.  */
1091   op0 = State.regs[OP[0]];
1092   op1 = State.regs[OP[1]];
1093   result = op0 & op1;
1094
1095   /* Compute the condition codes.  */
1096   z = (result == 0);
1097   s = (result & 0x80000000);
1098
1099   /* Store the result and condition codes.  */
1100   State.regs[OP[1]] = result;
1101   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
1102   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1103 }
1104
1105 /* andi zero_extend(imm16), reg, reg */
1106 void
1107 OP_6C0 ()
1108 {
1109   unsigned int op0, op1, result, z, s, cy, ov;
1110
1111   op0 = OP[0] & 0xffff;
1112   op1 = State.regs[OP[1]];
1113   result = op0 & op1;
1114
1115   /* Compute the condition codes.  */
1116   z = (result == 0);
1117
1118   /* Store the result and condition codes.  */
1119   State.regs[OP[2]] = result;
1120   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
1121   State.psw |= (z ? PSW_Z : 0);
1122 }
1123
1124 /* xor reg, reg */
1125 void
1126 OP_120 ()
1127 {
1128   unsigned int op0, op1, result, z, s, cy, ov;
1129
1130   /* Compute the result.  */
1131   op0 = State.regs[OP[0]];
1132   op1 = State.regs[OP[1]];
1133   result = op0 ^ op1;
1134
1135   /* Compute the condition codes.  */
1136   z = (result == 0);
1137   s = (result & 0x80000000);
1138
1139   /* Store the result and condition codes.  */
1140   State.regs[OP[1]] = result;
1141   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
1142   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1143 }
1144
1145 /* xori zero_extend(imm16), reg, reg */
1146 void
1147 OP_6A0 ()
1148 {
1149   unsigned int op0, op1, result, z, s, cy, ov;
1150
1151   op0 = OP[0] & 0xffff;
1152   op1 = State.regs[OP[1]];
1153   result = op0 ^ op1;
1154
1155   /* Compute the condition codes.  */
1156   z = (result == 0);
1157   s = (result & 0x80000000);
1158
1159   /* Store the result and condition codes.  */
1160   State.regs[OP[2]] = result;
1161   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
1162   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1163 }
1164
1165 /* not reg1, reg2 */
1166 void
1167 OP_20 ()
1168 {
1169   unsigned int op0, result, z, s, cy, ov;
1170
1171   /* Compute the result.  */
1172   op0 = State.regs[OP[0]];
1173   result = ~op0;
1174
1175   /* Compute the condition codes.  */
1176   z = (result == 0);
1177   s = (result & 0x80000000);
1178
1179   /* Store the result and condition codes.  */
1180   State.regs[OP[1]] = result;
1181   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
1182   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1183 }
1184
1185 void
1186 OP_480 ()
1187 {
1188 }
1189
1190 void
1191 OP_380 ()
1192 {
1193 }
1194
1195 void
1196 OP_501 ()
1197 {
1198 }
1199
1200 /* di */
1201 void
1202 OP_16007E0 ()
1203 {
1204   State.psw |= PSW_ID;
1205 }
1206
1207 /* ei */
1208 void
1209 OP_16087E0 ()
1210 {
1211   State.psw &= ~PSW_ID;
1212 }
1213
1214 /* halt, not supported */
1215 void
1216 OP_12007E0 ()
1217 {
1218   abort ();
1219 }
1220
1221 /* reti, not supported */
1222 void
1223 OP_14007E0 ()
1224 {
1225   abort ();
1226 }
1227
1228 /* trap, not supportd */
1229 void
1230 OP_10007E0 ()
1231 {
1232   abort ();
1233 }
1234
1235 /* ldsr, not supported */
1236 void
1237 OP_2007E0 ()
1238 {
1239   abort ();
1240 }
1241
1242 /* stsr, not supported */
1243 void
1244 OP_4007E0 ()
1245 {
1246   abort ();
1247 }
1248
1249 void
1250 OP_400 ()
1251 {
1252 }
1253
1254 void
1255 OP_700 ()
1256 {
1257 }
1258