sim/v850/simops.c

   1 #include <signal.h>
   2 #include "v850_sim.h"
   3 #include "simops.h"
   4
   5 void
   6 OP_220 ()
   7 {
   8 }
   9
  10 void
  11 OP_10760 ()
  12 {
  13 }
  14
  15 void
  16 OP_C7C0 ()
  17 {
  18 }
  19
  20 void
  21 OP_760 ()
  22 {
  23 }
  24
  25 /* bv disp9 */
  26 void
  27 OP_580 ()
  28 {
  29   unsigned int op0, psw;
  30   int temp;
  31
  32   temp = (State.regs[OP[0]] << 23) >> 23;
  33   op0 = temp;
  34   psw = State.psw;
  35
  36   if ((psw & PSW_OV) != 0)
  37     State.pc += op0;
  38   else
  39     State.pc += 2;
  40 }
  41
  42 /* bl disp9 */
  43 void
  44 OP_581 ()
  45 {
  46   unsigned int op0, psw;
  47   int temp;
  48
  49   temp = (State.regs[OP[0]] << 23) >> 23;
  50   op0 = temp;
  51   psw = State.psw;
  52
  53   if ((psw & PSW_CY) != 0)
  54     State.pc += op0;
  55   else
  56     State.pc += 2;
  57 }
  58
  59 /* be disp9 */
  60 void
  61 OP_582 ()
  62 {
  63   unsigned int op0, psw;
  64   int temp;
  65
  66   temp = (State.regs[OP[0]] << 23) >> 23;
  67   op0 = temp;
  68   psw = State.psw;
  69
  70   if ((psw & PSW_Z) != 0)
  71     State.pc += op0;
  72   else
  73     State.pc += 2;
  74 }
  75
  76 /* bnh disp 9*/
  77 void
  78 OP_583 ()
  79 {
  80   unsigned int op0, psw;
  81   int temp;
  82
  83   temp = (State.regs[OP[0]] << 23) >> 23;
  84   op0 = temp;
  85   psw = State.psw;
  86
  87   if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0)
  88     State.pc += op0;
  89   else
  90     State.pc += 2;
  91 }
  92
  93 /* bn disp9 */
  94 void
  95 OP_584 ()
  96 {
  97   unsigned int op0, psw;
  98   int temp;
  99
 100   temp = (State.regs[OP[0]] << 23) >> 23;
 101   op0 = temp;
 102   psw = State.psw;
 103
 104   if ((psw & PSW_S) != 0)
 105     State.pc += op0;
 106   else
 107     State.pc += 2;
 108 }
 109
 110 /* br disp9 */
 111 void
 112 OP_585 ()
 113 {
 114   unsigned int op0;
 115   int temp;
 116
 117   temp = (State.regs[OP[0]] << 23) >> 23;
 118   op0 = temp;
 119   State.pc += op0;
 120 }
 121
 122 /* blt disp9 */
 123 void
 124 OP_586 ()
 125 {
 126   unsigned int op0, psw;
 127   int temp;
 128
 129   temp = (State.regs[OP[0]] << 23) >> 23;
 130   op0 = temp;
 131   psw = State.psw;
 132
 133   if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0)
 134     State.pc += op0;
 135   else
 136     State.pc += 2;
 137 }
 138
 139 /* ble disp9 */
 140 void
 141 OP_587 ()
 142 {
 143   unsigned int op0, psw;
 144   int temp;
 145
 146   temp = (State.regs[OP[0]] << 23) >> 23;
 147   op0 = temp;
 148   psw = State.psw;
 149
 150   if ((((psw & PSW_Z) != 0)
 151        || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) != 0)
 152     State.pc += op0;
 153   else
 154     State.pc += 2;
 155 }
 156
 157 /* bnv disp9 */
 158 void
 159 OP_588 ()
 160 {
 161   unsigned int op0, psw;
 162   int temp;
 163
 164   temp = (State.regs[OP[0]] << 23) >> 23;
 165   op0 = temp;
 166   psw = State.psw;
 167
 168   if ((psw & PSW_OV) == 0)
 169     State.pc += op0;
 170   else
 171     State.pc += 2;
 172 }
 173
 174 /* bnl disp9 */
 175 void
 176 OP_589 ()
 177 {
 178   unsigned int op0, psw;
 179   int temp;
 180
 181   temp = (State.regs[OP[0]] << 23) >> 23;
 182   op0 = temp;
 183   psw = State.psw;
 184
 185   if ((psw & PSW_CY) == 0)
 186     State.pc += op0;
 187   else
 188     State.pc += 2;
 189 }
 190
 191 /* bne disp9 */
 192 void
 193 OP_58A ()
 194 {
 195   unsigned int op0, psw;
 196   int temp;
 197
 198   temp = (State.regs[OP[0]] << 23) >> 23;
 199   op0 = temp;
 200   psw = State.psw;
 201
 202   if ((psw & PSW_Z) == 0)
 203     State.pc += op0;
 204   else
 205     State.pc += 2;
 206 }
 207
 208 /* bh disp9 */
 209 void
 210 OP_58B ()
 211 {
 212   unsigned int op0, psw;
 213   int temp;
 214
 215   temp = (State.regs[OP[0]] << 23) >> 23;
 216   op0 = temp;
 217   psw = State.psw;
 218
 219   if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0)
 220     State.pc += op0;
 221   else
 222     State.pc += 2;
 223 }
 224
 225 /* bp disp9 */
 226 void
 227 OP_58C ()
 228 {
 229   unsigned int op0, psw;
 230   int temp;
 231
 232   temp = (State.regs[OP[0]] << 23) >> 23;
 233   op0 = temp;
 234   psw = State.psw;
 235
 236   if ((psw & PSW_S) == 0)
 237     State.pc += op0;
 238   else
 239     State.pc += 2;
 240 }
 241
 242 /* bsa disp9 */
 243 void
 244 OP_58D ()
 245 {
 246   unsigned int op0, psw;
 247   int temp;
 248
 249   temp = (State.regs[OP[0]] << 23) >> 23;
 250   op0 = temp;
 251   psw = State.psw;
 252
 253   if ((psw & PSW_SAT) != 0)
 254     State.pc += op0;
 255   else
 256     State.pc += 2;
 257 }
 258
 259 /* bge disp9 */
 260 void
 261 OP_58E ()
 262 {
 263   unsigned int op0, psw;
 264   int temp;
 265
 266   temp = (State.regs[OP[0]] << 23) >> 23;
 267   op0 = temp;
 268   psw = State.psw;
 269
 270   if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0)
 271     State.pc += op0;
 272   else
 273     State.pc += 2;
 274 }
 275
 276 /* bgt disp9 */
 277 void
 278 OP_58F ()
 279 {
 280   unsigned int op0, psw;
 281   int temp;
 282
 283   temp = (State.regs[OP[0]] << 23) >> 23;
 284   op0 = temp;
 285   psw = State.psw;
 286
 287   if ((((psw & PSW_Z) != 0)
 288        || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) == 0)
 289     State.pc += op0;
 290   else
 291     State.pc += 2;
 292 }
 293
 294 void
 295 OP_660 ()
 296 {
 297 }
 298
 299
 300 /* add reg, reg */
 301 void
 302 OP_1C0 ()
 303 {
 304   unsigned int op0, op1, result, z, s, cy, ov;
 305
 306   /* Compute the result.  */
 307   op0 = State.regs[OP[0]];
 308   op1 = State.regs[OP[1]];
 309   result = op0 + op1;
 310
 311   /* Compute the condition codes.  */
 312   z = (result == 0);
 313   s = (result & 0x80000000);
 314   cy = (result < op0 || result < op1);
 315   ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
 316         && (op0 & 0x80000000) != (result & 0x80000000));
 317
 318   /* Store the result and condition codes.  */
 319   State.regs[OP[1]] = result;
 320   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 321   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 322                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 323 }
 324
 325 /* add sign_extend(imm5), reg */
 326 void
 327 OP_240 ()
 328 {
 329   unsigned int op0, op1, result, z, s, cy, ov;
 330   int temp;
 331
 332   /* Compute the result.  */
 333   temp = (OP[0] & 0x1f);
 334   temp = (temp << 27) >> 27;
 335   op0 = temp;
 336   op1 = State.regs[OP[1]];
 337   result = op0 + op1;
 338
 339   /* Compute the condition codes.  */
 340   z = (result == 0);
 341   s = (result & 0x80000000);
 342   cy = (result < op0 || result < op1);
 343   ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
 344         && (op0 & 0x80000000) != (result & 0x80000000));
 345
 346   /* Store the result and condition codes.  */
 347   State.regs[OP[1]] = result;
 348   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 349   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 350                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 351 }
 352
 353 /* addi sign_extend(imm16), reg, reg */
 354 void
 355 OP_600 ()
 356 {
 357   unsigned int op0, op1, result, z, s, cy, ov;
 358   int temp;
 359
 360   /* Compute the result.  */
 361   temp = (OP[0] & 0xffff);
 362   temp = (temp << 16) >> 16;
 363   op0 = temp;
 364   op1 = State.regs[OP[1]];
 365   result = op0 + op1;
 366
 367   /* Compute the condition codes.  */
 368   z = (result == 0);
 369   s = (result & 0x80000000);
 370   cy = (result < op0 || result < op1);
 371   ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
 372         && (op0 & 0x80000000) != (result & 0x80000000));
 373
 374   /* Store the result and condition codes.  */
 375   State.regs[OP[2]] = result;
 376   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 377   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 378                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 379 }
 380
 381 /* sub reg1, reg2 */
 382 void
 383 OP_1A0 ()
 384 {
 385   unsigned int op0, op1, result, z, s, cy, ov;
 386
 387   /* Compute the result.  */
 388   op0 = State.regs[OP[0]];
 389   op1 = State.regs[OP[1]];
 390   result = op1 - op0;
 391
 392   /* Compute the condition codes.  */
 393   z = (result == 0);
 394   s = (result & 0x80000000);
 395   cy = (result < -op0);
 396   ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
 397         && (op1 & 0x80000000) != (result & 0x80000000));
 398
 399   /* Store the result and condition codes.  */
 400   State.regs[OP[1]] = result;
 401   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 402   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 403                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 404   State.regs[OP[1]] = State.regs[OP[0]];
 405 }
 406
 407 /* subr reg1, reg2 */
 408 void
 409 OP_180 ()
 410 {
 411   unsigned int op0, op1, result, z, s, cy, ov;
 412
 413   /* Compute the result.  */
 414   op0 = State.regs[OP[0]];
 415   op1 = State.regs[OP[1]];
 416   result = op0 - op1;
 417
 418   /* Compute the condition codes.  */
 419   z = (result == 0);
 420   s = (result & 0x80000000);
 421   cy = (result < -op1);
 422   ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
 423         && (op0 & 0x80000000) != (result & 0x80000000));
 424
 425   /* Store the result and condition codes.  */
 426   State.regs[OP[1]] = result;
 427   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 428   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 429                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 430 }
 431
 432 /* mulh reg1, reg2 */
 433 void
 434 OP_E0 ()
 435 {
 436   State.regs[OP[1]] = ((State.regs[OP[1]] & 0xffff)
 437                        * (State.regs[OP[0]] & 0xffff));
 438 }
 439
 440 /* mulh sign_extend(imm5), reg2
 441
 442    Condition codes */
 443 void
 444 OP_2E0 ()
 445 {
 446   int value = OP[0];
 447
 448   value = (value << 27) >> 27;
 449
 450   State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value;
 451 }
 452
 453 /* mulhi imm16, reg1, reg2 */
 454 void
 455 OP_6E0 ()
 456 {
 457   int value = OP[0];
 458
 459   value = value & 0xffff;
 460
 461   State.regs[OP[2]] = (State.regs[OP[1]] & 0xffff) * value;
 462 }
 463
 464 /* divh reg1, reg2 */
 465 void
 466 OP_40 ()
 467 {
 468   unsigned int op0, op1, result, z, s, cy, ov;
 469   int temp;
 470
 471   /* Compute the result.  */
 472   temp = State.regs[OP[0]] & 0xffff;
 473   temp = (temp << 16) >> 16;
 474   op0 = temp;
 475   op1 = State.regs[OP[1]];
 476
 477   if (op0 == 0xffffffff && op1 == 0x80000000)
 478     {
 479       result = 0x80000000;
 480       ov = 1;
 481     }
 482   else if (op0 != 0)
 483     {
 484       result = op1 / op0;
 485       ov = 0;
 486     }
 487   else
 488     ov = 1;
 489
 490   /* Compute the condition codes.  */
 491   z = (result == 0);
 492   s = (result & 0x80000000);
 493
 494   /* Store the result and condition codes.  */
 495   State.regs[OP[1]] = result;
 496   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
 497   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 498                 | (ov ? PSW_OV : 0));
 499 }
 500
 501 void
 502 OP_10720 ()
 503 {
 504 }
 505
 506 void
 507 OP_780 ()
 508 {
 509 }
 510
 511 void
 512 OP_720 ()
 513 {
 514 }
 515
 516 void
 517 OP_60 ()
 518 {
 519 }
 520
 521 void
 522 OP_87C0 ()
 523 {
 524 }
 525
 526 void
 527 OP_300 ()
 528 {
 529 }
 530
 531 /* mov reg, reg */
 532 void
 533 OP_0 ()
 534 {
 535   State.regs[OP[1]] = State.regs[OP[0]];
 536 }
 537
 538 /* mov sign_extend(imm5), reg */
 539 void
 540 OP_200 ()
 541 {
 542   int value = OP[0];
 543
 544   value = (value << 27) >> 27;
 545   State.regs[OP[1]] = value;
 546 }
 547
 548 /* movea sign_extend(imm16), reg, reg  */
 549
 550 void
 551 OP_620 ()
 552 {
 553   int value = OP[0];
 554
 555   value = (value << 16) >> 16;
 556
 557   State.regs[OP[2]] = State.regs[OP[1]] + value;
 558 }
 559
 560 /* movhi imm16, reg, reg */
 561 void
 562 OP_640 ()
 563 {
 564   int value = OP[0];
 565
 566   value = (value & 0xffff) << 16;
 567
 568   State.regs[OP[2]] = State.regs[OP[1]] + value;
 569 }
 570
 571 void
 572 OP_7C0 ()
 573 {
 574 }
 575
 576 void
 577 OP_1687E0 ()
 578 {
 579 }
 580
 581 void
 582 OP_1E0 ()
 583 {
 584 }
 585
 586 void
 587 OP_A0 ()
 588 {
 589 }
 590
 591 void
 592 OP_260 ()
 593 {
 594 }
 595
 596 void
 597 OP_740 ()
 598 {
 599 }
 600
 601 void
 602 OP_80 ()
 603 {
 604 }
 605
 606 /* sar zero_extend(imm5),reg1 */
 607 void
 608 OP_2A0 ()
 609 {
 610   unsigned int op0, op1, result, z, s, cy, ov;
 611
 612   op0 = OP[0] & 0x1f;
 613   op1 = State.regs[OP[1]];
 614   result = (signed)op1 >> op0;
 615
 616   /* Compute the condition codes.  */
 617   z = (result == 0);
 618   s = (result & 0x80000000);
 619   cy = (op1 & (1 << (op0 - 1)));
 620
 621   /* Store the result and condition codes.  */
 622   State.regs[OP[1]] = result;
 623   State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
 624   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 625                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 626 }
 627
 628 /* sar reg1, reg2 */
 629 void
 630 OP_A007E0 ()
 631 {
 632   unsigned int op0, op1, result, z, s, cy, ov;
 633
 634   op0 = State.regs[OP[0]] & 0x1f;
 635   op1 = State.regs[OP[1]];
 636   result = (signed)op1 >> op0;
 637
 638   /* Compute the condition codes.  */
 639   z = (result == 0);
 640   s = (result & 0x80000000);
 641   cy = (op1 & (1 << (op0 - 1)));
 642
 643   /* Store the result and condition codes.  */
 644   State.regs[OP[1]] = result;
 645   State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
 646   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 647                 | (cy ? PSW_CY : 0));
 648 }
 649
 650 /* shl zero_extend(imm5),reg1 */
 651 void
 652 OP_2C0 ()
 653 {
 654   unsigned int op0, op1, result, z, s, cy, ov;
 655
 656   op0 = OP[0] & 0x1f;
 657   op1 = State.regs[OP[1]];
 658   result = op1 << op0;
 659
 660   /* Compute the condition codes.  */
 661   z = (result == 0);
 662   s = (result & 0x80000000);
 663   cy = (op1 & (1 << (32 - op0)));
 664
 665   /* Store the result and condition codes.  */
 666   State.regs[OP[1]] = result;
 667   State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
 668   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 669                 | (cy ? PSW_CY : 0));
 670 }
 671
 672 /* shl reg1, reg2 */
 673 void
 674 OP_C007E0 ()
 675 {
 676   unsigned int op0, op1, result, z, s, cy, ov;
 677
 678   op0 = State.regs[OP[0]] & 0x1f;
 679   op1 = State.regs[OP[1]];
 680   result = op1 << op0;
 681
 682   /* Compute the condition codes.  */
 683   z = (result == 0);
 684   s = (result & 0x80000000);
 685   cy = (op1 & (1 << (32 - op0)));
 686
 687   /* Store the result and condition codes.  */
 688   State.regs[OP[1]] = result;
 689   State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
 690   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 691                 | (cy ? PSW_CY : 0));
 692 }
 693
 694 /* shr zero_extend(imm5),reg1 */
 695 void
 696 OP_280 ()
 697 {
 698   unsigned int op0, op1, result, z, s, cy, ov;
 699
 700   op0 = OP[0] & 0x1f;
 701   op1 = State.regs[OP[1]];
 702   result = op1 >> op0;
 703
 704   /* Compute the condition codes.  */
 705   z = (result == 0);
 706   s = (result & 0x80000000);
 707   cy = (op1 & (1 << (op0 - 1)));
 708
 709   /* Store the result and condition codes.  */
 710   State.regs[OP[1]] = result;
 711   State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
 712   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 713                 | (cy ? PSW_CY : 0));
 714 }
 715
 716 /* shr reg1, reg2 */
 717 void
 718 OP_8007E0 ()
 719 {
 720   unsigned int op0, op1, result, z, s, cy, ov;
 721
 722   op0 = State.regs[OP[0]] & 0x1f;
 723   op1 = State.regs[OP[1]];
 724   result = op1 >> op0;
 725
 726   /* Compute the condition codes.  */
 727   z = (result == 0);
 728   s = (result & 0x80000000);
 729   cy = (op1 & (1 << (op0 - 1)));
 730
 731   /* Store the result and condition codes.  */
 732   State.regs[OP[1]] = result;
 733   State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
 734   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 735                 | (cy ? PSW_CY : 0));
 736 }
 737
 738 void
 739 OP_500 ()
 740 {
 741 }
 742
 743 void
 744 OP_47C0 ()
 745 {
 746 }
 747
 748 void
 749 OP_7E0 ()
 750 {
 751 }
 752
 753 /* or reg, reg */
 754 void
 755 OP_100 ()
 756 {
 757   unsigned int op0, op1, result, z, s, cy, ov;
 758
 759   /* Compute the result.  */
 760   op0 = State.regs[OP[0]];
 761   op1 = State.regs[OP[1]];
 762   result = op0 | op1;
 763
 764   /* Compute the condition codes.  */
 765   z = (result == 0);
 766   s = (result & 0x80000000);
 767
 768   /* Store the result and condition codes.  */
 769   State.regs[OP[1]] = result;
 770   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
 771   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
 772 }
 773
 774 /* ori zero_extend(imm16), reg, reg */
 775 void
 776 OP_680 ()
 777 {
 778   unsigned int op0, op1, result, z, s, cy, ov;
 779
 780   op0 = OP[0] & 0xffff;
 781   op1 = State.regs[OP[1]];
 782   result = op0 | op1;
 783
 784   /* Compute the condition codes.  */
 785   z = (result == 0);
 786   s = (result & 0x80000000);
 787
 788   /* Store the result and condition codes.  */
 789   State.regs[OP[2]] = result;
 790   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
 791   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
 792 }
 793
 794 /* and reg, reg */
 795 void
 796 OP_140 ()
 797 {
 798   unsigned int op0, op1, result, z, s, cy, ov;
 799
 800   /* Compute the result.  */
 801   op0 = State.regs[OP[0]];
 802   op1 = State.regs[OP[1]];
 803   result = op0 & op1;
 804
 805   /* Compute the condition codes.  */
 806   z = (result == 0);
 807   s = (result & 0x80000000);
 808
 809   /* Store the result and condition codes.  */
 810   State.regs[OP[1]] = result;
 811   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
 812   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
 813 }
 814
 815 /* andi zero_extend(imm16), reg, reg */
 816 void
 817 OP_6C0 ()
 818 {
 819   unsigned int op0, op1, result, z, s, cy, ov;
 820
 821   op0 = OP[0] & 0xffff;
 822   op1 = State.regs[OP[1]];
 823   result = op0 & op1;
 824
 825   /* Compute the condition codes.  */
 826   z = (result == 0);
 827
 828   /* Store the result and condition codes.  */
 829   State.regs[OP[2]] = result;
 830   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
 831   State.psw |= (z ? PSW_Z : 0);
 832 }
 833
 834 /* xor reg, reg */
 835 void
 836 OP_120 ()
 837 {
 838   unsigned int op0, op1, result, z, s, cy, ov;
 839
 840   /* Compute the result.  */
 841   op0 = State.regs[OP[0]];
 842   op1 = State.regs[OP[1]];
 843   result = op0 ^ op1;
 844
 845   /* Compute the condition codes.  */
 846   z = (result == 0);
 847   s = (result & 0x80000000);
 848
 849   /* Store the result and condition codes.  */
 850   State.regs[OP[1]] = result;
 851   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
 852   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
 853 }
 854
 855 /* xori zero_extend(imm16), reg, reg */
 856 void
 857 OP_6A0 ()
 858 {
 859   unsigned int op0, op1, result, z, s, cy, ov;
 860
 861   op0 = OP[0] & 0xffff;
 862   op1 = State.regs[OP[1]];
 863   result = op0 ^ op1;
 864
 865   /* Compute the condition codes.  */
 866   z = (result == 0);
 867   s = (result & 0x80000000);
 868
 869   /* Store the result and condition codes.  */
 870   State.regs[OP[2]] = result;
 871   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
 872   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
 873 }
 874
 875 /* not reg1, reg2 */
 876 void
 877 OP_20 ()
 878 {
 879   unsigned int op0, result, z, s, cy, ov;
 880
 881   /* Compute the result.  */
 882   op0 = State.regs[OP[0]];
 883   result = ~op0;
 884
 885   /* Compute the condition codes.  */
 886   z = (result == 0);
 887   s = (result & 0x80000000);
 888
 889   /* Store the result and condition codes.  */
 890   State.regs[OP[1]] = result;
 891   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
 892   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
 893 }
 894
 895 void
 896 OP_C0 ()
 897 {
 898 }
 899
 900 void
 901 OP_480 ()
 902 {
 903 }
 904
 905 void
 906 OP_380 ()
 907 {
 908 }
 909
 910 void
 911 OP_501 ()
 912 {
 913 }
 914
 915 /* di, not supported */
 916 void
 917 OP_16007E0 ()
 918 {
 919   abort ();
 920 }
 921
 922 /* ei, not supported */
 923 void
 924 OP_16087E0 ()
 925 {
 926   abort ();
 927 }
 928
 929 /* halt, not supported */
 930 void
 931 OP_12007E0 ()
 932 {
 933   abort ();
 934 }
 935
 936 /* reti, not supported */
 937 void
 938 OP_14007E0 ()
 939 {
 940   abort ();
 941 }
 942
 943 /* trap, not supportd */
 944 void
 945 OP_10007E0 ()
 946 {
 947   abort ();
 948 }
 949
 950 /* ldsr, not supported */
 951 void
 952 OP_2007E0 ()
 953 {
 954   abort ();
 955 }
 956
 957 /* stsr, not supported */
 958 void
 959 OP_4007E0 ()
 960 {
 961   abort ();
 962 }
 963
 964 void
 965 OP_400 ()
 966 {
 967 }
 968
 969 void
 970 OP_160 ()
 971 {
 972 }
 973
 974 void
 975 OP_700 ()
 976 {
 977 }
 978