9 #include "sys/syscall.h"
13 #include <sys/times.h>
43 static void trace_input
PARAMS ((char *name
, enum op_types type
, int size
));
44 static void trace_output
PARAMS ((enum op_types result
));
45 static int init_text_p
= 0;
46 static asection
*text
;
47 static bfd_vma text_start
;
48 static bfd_vma text_end
;
51 #ifndef SIZE_INSTRUCTION
52 #define SIZE_INSTRUCTION 6
56 #define SIZE_OPERANDS 16
60 #define SIZE_VALUES 11
64 #define SIZE_LOCATION 40
68 trace_input (name
, type
, size
)
80 const char *functionname
;
81 unsigned int linenumber
;
83 if ((v850_debug
& DEBUG_TRACE
) == 0)
90 for (s
= exec_bfd
->sections
; s
; s
= s
->next
)
91 if (strcmp (bfd_get_section_name (exec_bfd
, s
), ".text") == 0)
94 text_start
= bfd_get_section_vma (exec_bfd
, s
);
95 text_end
= text_start
+ bfd_section_size (exec_bfd
, s
);
100 if (text
&& PC
>= text_start
&& PC
< text_end
)
102 filename
= (const char *)0;
103 functionname
= (const char *)0;
105 if (bfd_find_nearest_line (exec_bfd
, text
, (struct symbol_cache_entry
**)0, PC
- text_start
,
106 &filename
, &functionname
, &linenumber
))
111 sprintf (p
, "Line %5d ", linenumber
);
117 sprintf (p
, "Func %s ", functionname
);
122 char *q
= (char *) strrchr (filename
, '/');
123 sprintf (p
, "File %s ", (q
) ? q
+1 : filename
);
132 (*v850_callback
->printf_filtered
) (v850_callback
, "0x%.8x: %-*.*s %-*s",
134 SIZE_LOCATION
, SIZE_LOCATION
, buf
,
135 SIZE_INSTRUCTION
, name
);
142 strcpy (buf
, "unknown");
146 sprintf (buf
, "%d", OP
[0]);
150 sprintf (buf
, "r%d", OP
[0]);
155 case OP_REG_REG_MOVE
:
156 sprintf (buf
, "r%d,r%d", OP
[0], OP
[1]);
161 case OP_IMM_REG_MOVE
:
162 sprintf (buf
, "%d,r%d", OP
[0], OP
[1]);
166 sprintf (buf
, "%d", SEXT9 (OP
[0]));
170 sprintf (buf
, "%d[r30],r%d", OP
[1] * size
, OP
[0]);
174 sprintf (buf
, "r%d,%d[r30]", OP
[0], OP
[1] * size
);
178 sprintf (buf
, "%d[r%d],r%d", SEXT16 (OP
[2]) & ~0x1, OP
[0], OP
[1]);
182 sprintf (buf
, "r%d,%d[r%d]", OP
[1], SEXT16 (OP
[2] & ~0x1), OP
[0]);
186 sprintf (buf
, "%d,r%d", SEXT22 (OP
[0]), OP
[1]);
190 sprintf (buf
, "%d,r%d,r%d", SEXT16 (OP
[0]), OP
[1], OP
[2]);
193 case OP_UIMM_REG_REG
:
194 sprintf (buf
, "%d,r%d,r%d", OP
[0] & 0xffff, OP
[1], OP
[2]);
198 sprintf (buf
, "%d,%d[r%d]", OP
[1] & 0x7, SEXT16 (OP
[2]), OP
[0]);
204 default: cond
= "?"; break;
205 case 0x0: cond
= "v"; break;
206 case 0x1: cond
= "c"; break;
207 case 0x2: cond
= "z"; break;
208 case 0x3: cond
= "nh"; break;
209 case 0x4: cond
= "s"; break;
210 case 0x5: cond
= "t"; break;
211 case 0x6: cond
= "lt"; break;
212 case 0x7: cond
= "le"; break;
213 case 0x8: cond
= "nv"; break;
214 case 0x9: cond
= "nc"; break;
215 case 0xa: cond
= "nz"; break;
216 case 0xb: cond
= "h"; break;
217 case 0xc: cond
= "ns"; break;
218 case 0xd: cond
= "sa"; break;
219 case 0xe: cond
= "ge"; break;
220 case 0xf: cond
= "gt"; break;
223 sprintf (buf
, "%s,r%d", cond
, OP
[1]);
232 sprintf (buf
, "r%d,s%d", OP
[0], OP
[1]);
236 if ((v850_debug
& DEBUG_VALUES
) == 0)
238 (*v850_callback
->printf_filtered
) (v850_callback
, "%s\n", buf
);
242 (*v850_callback
->printf_filtered
) (v850_callback
, "%-*s", SIZE_OPERANDS
, buf
);
253 case OP_REG_REG_MOVE
:
254 values
[0] = State
.regs
[OP
[0]];
260 values
[0] = State
.regs
[OP
[1]];
261 values
[1] = State
.regs
[OP
[0]];
267 values
[0] = SEXT5 (OP
[0]);
272 case OP_IMM_REG_MOVE
:
273 values
[0] = SEXT5 (OP
[0]);
278 values
[0] = State
.pc
;
279 values
[1] = SEXT9 (OP
[0]);
285 values
[0] = OP
[1] * size
;
286 values
[1] = State
.regs
[30];
291 values
[0] = State
.regs
[OP
[0]];
292 values
[1] = OP
[1] * size
;
293 values
[2] = State
.regs
[30];
298 values
[0] = SEXT16 (OP
[2]);
299 values
[1] = State
.regs
[OP
[0]];
304 values
[0] = State
.regs
[OP
[1]];
305 values
[1] = SEXT16 (OP
[2]);
306 values
[2] = State
.regs
[OP
[0]];
311 values
[0] = SEXT22 (OP
[0]);
312 values
[1] = State
.pc
;
317 values
[0] = SEXT16 (OP
[0]) << size
;
318 values
[1] = State
.regs
[OP
[1]];
322 case OP_UIMM_REG_REG
:
323 values
[0] = (OP
[0] & 0xffff) << size
;
324 values
[1] = State
.regs
[OP
[1]];
342 values
[0] = State
.regs
[OP
[0]];
347 values
[0] = State
.sregs
[OP
[1]];
351 for (i
= 0; i
< num_values
; i
++)
352 (*v850_callback
->printf_filtered
) (v850_callback
, "%*s0x%.8lx", SIZE_VALUES
- 10, "", values
[i
]);
355 (*v850_callback
->printf_filtered
) (v850_callback
, "%*s", SIZE_VALUES
, "");
360 trace_output (result
)
361 enum op_types result
;
363 if ((v850_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
383 (*v850_callback
->printf_filtered
) (v850_callback
, " :: 0x%.8lx",
384 (unsigned long)State
.regs
[OP
[0]]);
388 case OP_REG_REG_MOVE
:
390 case OP_IMM_REG_MOVE
:
393 (*v850_callback
->printf_filtered
) (v850_callback
, " :: 0x%.8lx",
394 (unsigned long)State
.regs
[OP
[1]]);
398 case OP_UIMM_REG_REG
:
399 (*v850_callback
->printf_filtered
) (v850_callback
, " :: 0x%.8lx",
400 (unsigned long)State
.regs
[OP
[2]]);
405 (*v850_callback
->printf_filtered
) (v850_callback
, " :: 0x%.8lx",
406 (unsigned long)State
.regs
[OP
[1]]);
410 (*v850_callback
->printf_filtered
) (v850_callback
, " :: 0x%.8lx",
411 (unsigned long)State
.sregs
[OP
[1]]);
415 (*v850_callback
->printf_filtered
) (v850_callback
, "\n");
420 #define trace_input(NAME, IN1, IN2)
421 #define trace_output(RESULT)
432 trace_input ("sld.b", OP_LOAD16
, 1);
436 result
= load_mem (State
.regs
[30] + op2
, 1);
437 State
.regs
[OP
[0]] = SEXT8 (result
);
438 trace_output (OP_LOAD16
);
448 trace_input ("sld.h", OP_LOAD16
, 2);
452 result
= load_mem (State
.regs
[30] + op2
, 2);
453 State
.regs
[OP
[0]] = SEXT16 (result
);
454 trace_output (OP_LOAD16
);
464 trace_input ("sld.w", OP_LOAD16
, 4);
468 result
= load_mem (State
.regs
[30] + op2
, 4);
469 State
.regs
[OP
[0]] = result
;
470 trace_output (OP_LOAD16
);
477 unsigned int op0
, op1
;
480 trace_input ("sst.b", OP_STORE16
, 1);
481 op0
= State
.regs
[OP
[0]];
485 store_mem (State
.regs
[30] + op1
, 1, op0
);
486 trace_output (OP_STORE16
);
493 unsigned int op0
, op1
;
496 trace_input ("sst.h", OP_STORE16
, 2);
497 op0
= State
.regs
[OP
[0]];
501 store_mem (State
.regs
[30] + op1
, 2, op0
);
502 trace_output (OP_STORE16
);
509 unsigned int op0
, op1
;
512 trace_input ("sst.w", OP_STORE16
, 4);
513 op0
= State
.regs
[OP
[0]];
517 store_mem (State
.regs
[30] + op1
, 4, op0
);
518 trace_output (OP_STORE16
);
525 unsigned int op0
, op2
;
528 trace_input ("ld.b", OP_LOAD32
, 1);
529 op0
= State
.regs
[OP
[0]];
530 temp
= SEXT16 (OP
[2]);
532 result
= load_mem (op0
+ op2
, 1);
533 State
.regs
[OP
[1]] = SEXT8 (result
);
534 trace_output (OP_LOAD32
);
541 unsigned int op0
, op2
;
544 trace_input ("ld.h", OP_LOAD32
, 2);
545 op0
= State
.regs
[OP
[0]];
546 temp
= SEXT16 (OP
[2]);
549 result
= load_mem (op0
+ op2
, 2);
550 State
.regs
[OP
[1]] = SEXT16 (result
);
551 trace_output (OP_LOAD32
);
558 unsigned int op0
, op2
;
561 trace_input ("ld.w", OP_LOAD32
, 4);
562 op0
= State
.regs
[OP
[0]];
563 temp
= SEXT16 (OP
[2]);
566 result
= load_mem (op0
+ op2
, 4);
567 State
.regs
[OP
[1]] = result
;
568 trace_output (OP_LOAD32
);
575 unsigned int op0
, op1
, op2
;
578 trace_input ("st.b", OP_STORE32
, 1);
579 op0
= State
.regs
[OP
[0]];
580 op1
= State
.regs
[OP
[1]];
581 temp
= SEXT16 (OP
[2]);
583 store_mem (op0
+ op2
, 1, op1
);
584 trace_output (OP_STORE32
);
591 unsigned int op0
, op1
, op2
;
594 trace_input ("st.h", OP_STORE32
, 2);
595 op0
= State
.regs
[OP
[0]];
596 op1
= State
.regs
[OP
[1]];
597 temp
= SEXT16 (OP
[2] & ~0x1);
599 store_mem (op0
+ op2
, 2, op1
);
600 trace_output (OP_STORE32
);
607 unsigned int op0
, op1
, op2
;
610 trace_input ("st.w", OP_STORE32
, 4);
611 op0
= State
.regs
[OP
[0]];
612 op1
= State
.regs
[OP
[1]];
613 temp
= SEXT16 (OP
[2] & ~0x1);
615 store_mem (op0
+ op2
, 4, op1
);
616 trace_output (OP_STORE32
);
626 trace_input ("bv", OP_COND_BR
, 0);
630 if ((psw
& PSW_OV
) != 0)
634 trace_output (OP_COND_BR
);
644 trace_input ("bl", OP_COND_BR
, 0);
648 if ((psw
& PSW_CY
) != 0)
652 trace_output (OP_COND_BR
);
662 trace_input ("be", OP_COND_BR
, 0);
666 if ((psw
& PSW_Z
) != 0)
670 trace_output (OP_COND_BR
);
680 trace_input ("bnh", OP_COND_BR
, 0);
684 if ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) != 0)
688 trace_output (OP_COND_BR
);
698 trace_input ("bn", OP_COND_BR
, 0);
702 if ((psw
& PSW_S
) != 0)
706 trace_output (OP_COND_BR
);
716 trace_input ("br", OP_COND_BR
, 0);
719 trace_output (OP_COND_BR
);
729 trace_input ("blt", OP_COND_BR
, 0);
733 if ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) != 0)
737 trace_output (OP_COND_BR
);
747 trace_input ("ble", OP_COND_BR
, 0);
751 if ((((psw
& PSW_Z
) != 0)
752 || (((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0))) != 0)
756 trace_output (OP_COND_BR
);
766 trace_input ("bnv", OP_COND_BR
, 0);
770 if ((psw
& PSW_OV
) == 0)
774 trace_output (OP_COND_BR
);
784 trace_input ("bnl", OP_COND_BR
, 0);
788 if ((psw
& PSW_CY
) == 0)
792 trace_output (OP_COND_BR
);
802 trace_input ("bne", OP_COND_BR
, 0);
806 if ((psw
& PSW_Z
) == 0)
810 trace_output (OP_COND_BR
);
820 trace_input ("bh", OP_COND_BR
, 0);
824 if ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) == 0)
828 trace_output (OP_COND_BR
);
838 trace_input ("bp", OP_COND_BR
, 0);
842 if ((psw
& PSW_S
) == 0)
846 trace_output (OP_COND_BR
);
856 trace_input ("bsa", OP_COND_BR
, 0);
860 if ((psw
& PSW_SAT
) != 0)
864 trace_output (OP_COND_BR
);
874 trace_input ("bge", OP_COND_BR
, 0);
878 if ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) == 0)
882 trace_output (OP_COND_BR
);
892 trace_input ("bgt", OP_COND_BR
, 0);
896 if ((((psw
& PSW_Z
) != 0)
897 || (((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0))) == 0)
901 trace_output (OP_COND_BR
);
908 /* interp.c will bump this by +2, so correct for it here. */
909 trace_input ("jmp", OP_REG
, 0);
910 State
.pc
= State
.regs
[OP
[0]] - 2;
911 trace_output (OP_REG
);
914 /* jarl disp22, reg */
918 unsigned int op0
, opc
;
921 trace_input ("jarl", OP_JUMP
, 0);
922 temp
= SEXT22 (OP
[0]);
928 /* Gross. jarl X,r0 is really jr and doesn't save its result. */
930 State
.regs
[OP
[1]] = opc
+ 4;
931 trace_output (OP_JUMP
);
938 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
940 trace_input ("add", OP_REG_REG
, 0);
941 /* Compute the result. */
942 op0
= State
.regs
[OP
[0]];
943 op1
= State
.regs
[OP
[1]];
946 /* Compute the condition codes. */
948 s
= (result
& 0x80000000);
949 cy
= (result
< op0
|| result
< op1
);
950 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
951 && (op0
& 0x80000000) != (result
& 0x80000000));
953 /* Store the result and condition codes. */
954 State
.regs
[OP
[1]] = result
;
955 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
956 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
957 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
958 trace_output (OP_REG_REG
);
961 /* add sign_extend(imm5), reg */
965 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
968 trace_input ("add", OP_IMM_REG
, 0);
970 /* Compute the result. */
971 temp
= SEXT5 (OP
[0]);
973 op1
= State
.regs
[OP
[1]];
976 /* Compute the condition codes. */
978 s
= (result
& 0x80000000);
979 cy
= (result
< op0
|| result
< op1
);
980 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
981 && (op0
& 0x80000000) != (result
& 0x80000000));
983 /* Store the result and condition codes. */
984 State
.regs
[OP
[1]] = result
;
985 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
986 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
987 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
988 trace_output (OP_IMM_REG
);
991 /* addi sign_extend(imm16), reg, reg */
995 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
998 trace_input ("addi", OP_IMM_REG_REG
, 0);
1000 /* Compute the result. */
1001 temp
= SEXT16 (OP
[0]);
1003 op1
= State
.regs
[OP
[1]];
1006 /* Compute the condition codes. */
1008 s
= (result
& 0x80000000);
1009 cy
= (result
< op0
|| result
< op1
);
1010 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
1011 && (op0
& 0x80000000) != (result
& 0x80000000));
1013 /* Store the result and condition codes. */
1014 State
.regs
[OP
[2]] = result
;
1015 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1016 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1017 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1018 trace_output (OP_IMM_REG_REG
);
1021 /* sub reg1, reg2 */
1025 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1027 trace_input ("sub", OP_REG_REG
, 0);
1028 /* Compute the result. */
1029 op0
= State
.regs
[OP
[0]];
1030 op1
= State
.regs
[OP
[1]];
1033 /* Compute the condition codes. */
1035 s
= (result
& 0x80000000);
1037 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1038 && (op1
& 0x80000000) != (result
& 0x80000000));
1040 /* Store the result and condition codes. */
1041 State
.regs
[OP
[1]] = result
;
1042 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1043 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1044 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1045 trace_output (OP_REG_REG
);
1048 /* subr reg1, reg2 */
1052 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1054 trace_input ("subr", OP_REG_REG
, 0);
1055 /* Compute the result. */
1056 op0
= State
.regs
[OP
[0]];
1057 op1
= State
.regs
[OP
[1]];
1060 /* Compute the condition codes. */
1062 s
= (result
& 0x80000000);
1064 ov
= ((op0
& 0x80000000) != (op1
& 0x80000000)
1065 && (op0
& 0x80000000) != (result
& 0x80000000));
1067 /* Store the result and condition codes. */
1068 State
.regs
[OP
[1]] = result
;
1069 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1070 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1071 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1072 trace_output (OP_REG_REG
);
1075 /* mulh reg1, reg2 */
1079 trace_input ("mulh", OP_REG_REG
, 0);
1080 State
.regs
[OP
[1]] = ((State
.regs
[OP
[1]] & 0xffff)
1081 * (State
.regs
[OP
[0]] & 0xffff));
1082 trace_output (OP_REG_REG
);
1085 /* mulh sign_extend(imm5), reg2
1091 int value
= SEXT5 (OP
[0]);
1093 trace_input ("mulh", OP_IMM_REG
, 0);
1094 State
.regs
[OP
[1]] = (State
.regs
[OP
[1]] & 0xffff) * value
;
1095 trace_output (OP_IMM_REG
);
1098 /* mulhi imm16, reg1, reg2 */
1102 int value
= OP
[0] & 0xffff;
1104 trace_input ("mulhi", OP_IMM_REG_REG
, 0);
1105 State
.regs
[OP
[2]] = (State
.regs
[OP
[1]] & 0xffff) * value
;
1106 trace_output (OP_IMM_REG_REG
);
1109 /* divh reg1, reg2 */
1113 unsigned int op0
, op1
, result
, ov
, s
, z
;
1116 trace_input ("divh", OP_REG_REG
, 0);
1118 /* Compute the result. */
1119 temp
= SEXT16 (State
.regs
[OP
[0]]);
1121 op1
= State
.regs
[OP
[1]];
1123 if (op0
== 0xffffffff && op1
== 0x80000000)
1125 result
= 0x80000000;
1139 /* Compute the condition codes. */
1141 s
= (result
& 0x80000000);
1143 /* Store the result and condition codes. */
1144 State
.regs
[OP
[1]] = result
;
1145 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1146 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1147 | (ov
? PSW_OV
: 0));
1148 trace_output (OP_REG_REG
);
1155 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1157 trace_input ("cmp", OP_REG_REG_CMP
, 0);
1158 /* Compute the result. */
1159 op0
= State
.regs
[OP
[0]];
1160 op1
= State
.regs
[OP
[1]];
1163 /* Compute the condition codes. */
1165 s
= (result
& 0x80000000);
1167 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1168 && (op1
& 0x80000000) != (result
& 0x80000000));
1170 /* Set condition codes. */
1171 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1172 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1173 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1174 trace_output (OP_REG_REG_CMP
);
1177 /* cmp sign_extend(imm5), reg */
1181 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1184 /* Compute the result. */
1185 trace_input ("cmp", OP_IMM_REG_CMP
, 0);
1186 temp
= SEXT5 (OP
[0]);
1188 op1
= State
.regs
[OP
[1]];
1191 /* Compute the condition codes. */
1193 s
= (result
& 0x80000000);
1195 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1196 && (op1
& 0x80000000) != (result
& 0x80000000));
1198 /* Set condition codes. */
1199 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1200 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1201 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1202 trace_output (OP_IMM_REG_CMP
);
1205 /* setf cccc,reg2 */
1209 /* Hack alert. We turn off a bit in op0 since we really only
1211 unsigned int op0
, psw
, result
= 0;
1213 trace_input ("setf", OP_EX1
, 0);
1220 result
= ((psw
& PSW_OV
) != 0);
1223 result
= ((psw
& PSW_CY
) != 0);
1226 result
= ((psw
& PSW_Z
) != 0);
1229 result
= ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) != 0);
1232 result
= ((psw
& PSW_S
) != 0);
1238 result
= ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) != 0);
1241 result
= (((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0))
1242 || ((psw
& PSW_Z
) != 0)) != 0);
1245 result
= ((psw
& PSW_OV
) == 0);
1248 result
= ((psw
& PSW_CY
) == 0);
1251 result
= ((psw
& PSW_Z
) == 0);
1254 result
= ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) == 0);
1257 result
= ((psw
& PSW_S
) == 0);
1260 result
= ((psw
& PSW_SAT
) != 0);
1263 result
= ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) == 0);
1266 result
= (((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0))
1267 || ((psw
& PSW_Z
) != 0)) == 0);
1271 State
.regs
[OP
[1]] = result
;
1272 trace_output (OP_EX1
);
1275 /* satadd reg,reg */
1279 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1281 trace_input ("satadd", OP_REG_REG
, 0);
1282 /* Compute the result. */
1283 op0
= State
.regs
[OP
[0]];
1284 op1
= State
.regs
[OP
[1]];
1287 /* Compute the condition codes. */
1289 s
= (result
& 0x80000000);
1290 cy
= (result
< op0
|| result
< op1
);
1291 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
1292 && (op0
& 0x80000000) != (result
& 0x80000000));
1295 /* Store the result and condition codes. */
1296 State
.regs
[OP
[1]] = result
;
1297 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1298 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1299 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1300 | (sat
? PSW_SAT
: 0));
1302 /* Handle saturated results. */
1304 State
.regs
[OP
[1]] = 0x80000000;
1306 State
.regs
[OP
[1]] = 0x7fffffff;
1307 trace_output (OP_REG_REG
);
1310 /* satadd sign_extend(imm5), reg */
1314 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1318 trace_input ("satadd", OP_IMM_REG
, 0);
1320 /* Compute the result. */
1321 temp
= SEXT5 (OP
[0]);
1323 op1
= State
.regs
[OP
[1]];
1326 /* Compute the condition codes. */
1328 s
= (result
& 0x80000000);
1329 cy
= (result
< op0
|| result
< op1
);
1330 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
1331 && (op0
& 0x80000000) != (result
& 0x80000000));
1334 /* Store the result and condition codes. */
1335 State
.regs
[OP
[1]] = result
;
1336 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1337 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1338 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1339 | (sat
? PSW_SAT
: 0));
1341 /* Handle saturated results. */
1343 State
.regs
[OP
[1]] = 0x80000000;
1345 State
.regs
[OP
[1]] = 0x7fffffff;
1346 trace_output (OP_IMM_REG
);
1349 /* satsub reg1, reg2 */
1353 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1355 trace_input ("satsub", OP_REG_REG
, 0);
1357 /* Compute the result. */
1358 op0
= State
.regs
[OP
[0]];
1359 op1
= State
.regs
[OP
[1]];
1362 /* Compute the condition codes. */
1364 s
= (result
& 0x80000000);
1366 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1367 && (op1
& 0x80000000) != (result
& 0x80000000));
1370 /* Store the result and condition codes. */
1371 State
.regs
[OP
[1]] = result
;
1372 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1373 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1374 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1375 | (sat
? PSW_SAT
: 0));
1377 /* Handle saturated results. */
1379 State
.regs
[OP
[1]] = 0x80000000;
1381 State
.regs
[OP
[1]] = 0x7fffffff;
1382 trace_output (OP_REG_REG
);
1385 /* satsubi sign_extend(imm16), reg */
1389 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1392 trace_input ("satsubi", OP_IMM_REG
, 0);
1394 /* Compute the result. */
1395 temp
= SEXT16 (OP
[0]);
1397 op1
= State
.regs
[OP
[1]];
1400 /* Compute the condition codes. */
1402 s
= (result
& 0x80000000);
1404 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1405 && (op1
& 0x80000000) != (result
& 0x80000000));
1408 /* Store the result and condition codes. */
1409 State
.regs
[OP
[1]] = result
;
1410 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1411 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1412 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1413 | (sat
? PSW_SAT
: 0));
1415 /* Handle saturated results. */
1417 State
.regs
[OP
[1]] = 0x80000000;
1419 State
.regs
[OP
[1]] = 0x7fffffff;
1420 trace_output (OP_IMM_REG
);
1423 /* satsubr reg,reg */
1427 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1429 trace_input ("satsubr", OP_REG_REG
, 0);
1431 /* Compute the result. */
1432 op0
= State
.regs
[OP
[0]];
1433 op1
= State
.regs
[OP
[1]];
1436 /* Compute the condition codes. */
1438 s
= (result
& 0x80000000);
1439 cy
= (result
< op0
);
1440 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1441 && (op1
& 0x80000000) != (result
& 0x80000000));
1444 /* Store the result and condition codes. */
1445 State
.regs
[OP
[1]] = result
;
1446 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1447 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1448 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1449 | (sat
? PSW_SAT
: 0));
1451 /* Handle saturated results. */
1453 State
.regs
[OP
[1]] = 0x80000000;
1455 State
.regs
[OP
[1]] = 0x7fffffff;
1456 trace_output (OP_REG_REG
);
1463 unsigned int op0
, op1
, result
, z
, s
;
1465 trace_input ("tst", OP_REG_REG_CMP
, 0);
1467 /* Compute the result. */
1468 op0
= State
.regs
[OP
[0]];
1469 op1
= State
.regs
[OP
[1]];
1472 /* Compute the condition codes. */
1474 s
= (result
& 0x80000000);
1476 /* Store the condition codes. */
1477 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1478 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1479 trace_output (OP_REG_REG_CMP
);
1486 trace_input ("mov", OP_REG_REG_MOVE
, 0);
1487 State
.regs
[OP
[1]] = State
.regs
[OP
[0]];
1488 trace_output (OP_REG_REG_MOVE
);
1491 /* mov sign_extend(imm5), reg */
1495 int value
= SEXT5 (OP
[0]);
1497 trace_input ("mov", OP_IMM_REG_MOVE
, 0);
1498 State
.regs
[OP
[1]] = value
;
1499 trace_output (OP_IMM_REG_MOVE
);
1502 /* movea sign_extend(imm16), reg, reg */
1507 int value
= SEXT16 (OP
[0]);
1509 trace_input ("movea", OP_IMM_REG_REG
, 0);
1510 State
.regs
[OP
[2]] = State
.regs
[OP
[1]] + value
;
1511 trace_output (OP_IMM_REG_REG
);
1514 /* movhi imm16, reg, reg */
1518 uint32 value
= (OP
[0] & 0xffff) << 16;
1520 trace_input ("movhi", OP_UIMM_REG_REG
, 16);
1521 State
.regs
[OP
[2]] = State
.regs
[OP
[1]] + value
;
1522 trace_output (OP_UIMM_REG_REG
);
1525 /* sar zero_extend(imm5),reg1 */
1529 unsigned int op0
, op1
, result
, z
, s
, cy
;
1531 trace_input ("sar", OP_IMM_REG
, 0);
1533 op1
= State
.regs
[OP
[1]];
1534 result
= (signed)op1
>> op0
;
1536 /* Compute the condition codes. */
1538 s
= (result
& 0x80000000);
1539 cy
= (op1
& (1 << (op0
- 1)));
1541 /* Store the result and condition codes. */
1542 State
.regs
[OP
[1]] = result
;
1543 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1544 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1545 | (cy
? PSW_CY
: 0));
1546 trace_output (OP_IMM_REG
);
1549 /* sar reg1, reg2 */
1553 unsigned int op0
, op1
, result
, z
, s
, cy
;
1555 trace_input ("sar", OP_REG_REG
, 0);
1556 op0
= State
.regs
[OP
[0]] & 0x1f;
1557 op1
= State
.regs
[OP
[1]];
1558 result
= (signed)op1
>> op0
;
1560 /* Compute the condition codes. */
1562 s
= (result
& 0x80000000);
1563 cy
= (op1
& (1 << (op0
- 1)));
1565 /* Store the result and condition codes. */
1566 State
.regs
[OP
[1]] = result
;
1567 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1568 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1569 | (cy
? PSW_CY
: 0));
1570 trace_output (OP_REG_REG
);
1573 /* shl zero_extend(imm5),reg1 */
1577 unsigned int op0
, op1
, result
, z
, s
, cy
;
1579 trace_input ("shl", OP_IMM_REG
, 0);
1581 op1
= State
.regs
[OP
[1]];
1582 result
= op1
<< op0
;
1584 /* Compute the condition codes. */
1586 s
= (result
& 0x80000000);
1587 cy
= (op1
& (1 << (32 - op0
)));
1589 /* Store the result and condition codes. */
1590 State
.regs
[OP
[1]] = result
;
1591 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1592 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1593 | (cy
? PSW_CY
: 0));
1594 trace_output (OP_IMM_REG
);
1597 /* shl reg1, reg2 */
1601 unsigned int op0
, op1
, result
, z
, s
, cy
;
1603 trace_input ("shl", OP_REG_REG
, 0);
1604 op0
= State
.regs
[OP
[0]] & 0x1f;
1605 op1
= State
.regs
[OP
[1]];
1606 result
= op1
<< op0
;
1608 /* Compute the condition codes. */
1610 s
= (result
& 0x80000000);
1611 cy
= (op1
& (1 << (32 - op0
)));
1613 /* Store the result and condition codes. */
1614 State
.regs
[OP
[1]] = result
;
1615 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1616 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1617 | (cy
? PSW_CY
: 0));
1618 trace_output (OP_REG_REG
);
1621 /* shr zero_extend(imm5),reg1 */
1625 unsigned int op0
, op1
, result
, z
, s
, cy
;
1627 trace_input ("shr", OP_IMM_REG
, 0);
1629 op1
= State
.regs
[OP
[1]];
1630 result
= op1
>> op0
;
1632 /* Compute the condition codes. */
1634 s
= (result
& 0x80000000);
1635 cy
= (op1
& (1 << (op0
- 1)));
1637 /* Store the result and condition codes. */
1638 State
.regs
[OP
[1]] = result
;
1639 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1640 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1641 | (cy
? PSW_CY
: 0));
1642 trace_output (OP_IMM_REG
);
1645 /* shr reg1, reg2 */
1649 unsigned int op0
, op1
, result
, z
, s
, cy
;
1651 trace_input ("shr", OP_REG_REG
, 0);
1652 op0
= State
.regs
[OP
[0]] & 0x1f;
1653 op1
= State
.regs
[OP
[1]];
1654 result
= op1
>> op0
;
1656 /* Compute the condition codes. */
1658 s
= (result
& 0x80000000);
1659 cy
= (op1
& (1 << (op0
- 1)));
1661 /* Store the result and condition codes. */
1662 State
.regs
[OP
[1]] = result
;
1663 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1664 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1665 | (cy
? PSW_CY
: 0));
1666 trace_output (OP_REG_REG
);
1673 unsigned int op0
, op1
, result
, z
, s
;
1675 trace_input ("or", OP_REG_REG
, 0);
1677 /* Compute the result. */
1678 op0
= State
.regs
[OP
[0]];
1679 op1
= State
.regs
[OP
[1]];
1682 /* Compute the condition codes. */
1684 s
= (result
& 0x80000000);
1686 /* Store the result and condition codes. */
1687 State
.regs
[OP
[1]] = result
;
1688 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1689 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1690 trace_output (OP_REG_REG
);
1693 /* ori zero_extend(imm16), reg, reg */
1697 unsigned int op0
, op1
, result
, z
, s
;
1699 trace_input ("ori", OP_UIMM_REG_REG
, 0);
1700 op0
= OP
[0] & 0xffff;
1701 op1
= State
.regs
[OP
[1]];
1704 /* Compute the condition codes. */
1706 s
= (result
& 0x80000000);
1708 /* Store the result and condition codes. */
1709 State
.regs
[OP
[2]] = result
;
1710 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1711 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1712 trace_output (OP_UIMM_REG_REG
);
1719 unsigned int op0
, op1
, result
, z
, s
;
1721 trace_input ("and", OP_REG_REG
, 0);
1723 /* Compute the result. */
1724 op0
= State
.regs
[OP
[0]];
1725 op1
= State
.regs
[OP
[1]];
1728 /* Compute the condition codes. */
1730 s
= (result
& 0x80000000);
1732 /* Store the result and condition codes. */
1733 State
.regs
[OP
[1]] = result
;
1734 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1735 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1736 trace_output (OP_REG_REG
);
1739 /* andi zero_extend(imm16), reg, reg */
1743 unsigned int op0
, op1
, result
, z
;
1745 trace_input ("andi", OP_UIMM_REG_REG
, 0);
1746 op0
= OP
[0] & 0xffff;
1747 op1
= State
.regs
[OP
[1]];
1750 /* Compute the condition codes. */
1753 /* Store the result and condition codes. */
1754 State
.regs
[OP
[2]] = result
;
1755 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1756 PSW
|= (z
? PSW_Z
: 0);
1757 trace_output (OP_UIMM_REG_REG
);
1764 unsigned int op0
, op1
, result
, z
, s
;
1766 trace_input ("xor", OP_REG_REG
, 0);
1768 /* Compute the result. */
1769 op0
= State
.regs
[OP
[0]];
1770 op1
= State
.regs
[OP
[1]];
1773 /* Compute the condition codes. */
1775 s
= (result
& 0x80000000);
1777 /* Store the result and condition codes. */
1778 State
.regs
[OP
[1]] = result
;
1779 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1780 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1781 trace_output (OP_REG_REG
);
1784 /* xori zero_extend(imm16), reg, reg */
1788 unsigned int op0
, op1
, result
, z
, s
;
1790 trace_input ("xori", OP_UIMM_REG_REG
, 0);
1791 op0
= OP
[0] & 0xffff;
1792 op1
= State
.regs
[OP
[1]];
1795 /* Compute the condition codes. */
1797 s
= (result
& 0x80000000);
1799 /* Store the result and condition codes. */
1800 State
.regs
[OP
[2]] = result
;
1801 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1802 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1803 trace_output (OP_UIMM_REG_REG
);
1806 /* not reg1, reg2 */
1810 unsigned int op0
, result
, z
, s
;
1812 trace_input ("not", OP_REG_REG_MOVE
, 0);
1813 /* Compute the result. */
1814 op0
= State
.regs
[OP
[0]];
1817 /* Compute the condition codes. */
1819 s
= (result
& 0x80000000);
1821 /* Store the result and condition codes. */
1822 State
.regs
[OP
[1]] = result
;
1823 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1824 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1825 trace_output (OP_REG_REG_MOVE
);
1832 unsigned int op0
, op1
, op2
;
1835 trace_input ("set1", OP_BIT
, 0);
1836 op0
= State
.regs
[OP
[0]];
1838 temp
= SEXT16 (OP
[2]);
1840 temp
= load_mem (op0
+ op2
, 1);
1842 if ((temp
& (1 << op1
)) == 0)
1845 store_mem (op0
+ op2
, 1, temp
);
1846 trace_output (OP_BIT
);
1853 unsigned int op0
, op1
, op2
;
1856 trace_input ("not1", OP_BIT
, 0);
1857 op0
= State
.regs
[OP
[0]];
1859 temp
= SEXT16 (OP
[2]);
1861 temp
= load_mem (op0
+ op2
, 1);
1863 if ((temp
& (1 << op1
)) == 0)
1866 store_mem (op0
+ op2
, 1, temp
);
1867 trace_output (OP_BIT
);
1874 unsigned int op0
, op1
, op2
;
1877 trace_input ("clr1", OP_BIT
, 0);
1878 op0
= State
.regs
[OP
[0]];
1880 temp
= SEXT16 (OP
[2]);
1882 temp
= load_mem (op0
+ op2
, 1);
1884 if ((temp
& (1 << op1
)) == 0)
1886 temp
&= ~(1 << op1
);
1887 store_mem (op0
+ op2
, 1, temp
);
1888 trace_output (OP_BIT
);
1895 unsigned int op0
, op1
, op2
;
1898 trace_input ("tst1", OP_BIT
, 0);
1899 op0
= State
.regs
[OP
[0]];
1901 temp
= SEXT16 (OP
[2]);
1903 temp
= load_mem (op0
+ op2
, 1);
1905 if ((temp
& (1 << op1
)) == 0)
1907 trace_output (OP_BIT
);
1914 State
.exception
= SIGTRAP
;
1922 trace_input ("di", OP_NONE
, 0);
1924 trace_output (OP_NONE
);
1931 trace_input ("ei", OP_NONE
, 0);
1933 trace_output (OP_NONE
);
1940 trace_input ("halt", OP_NONE
, 0);
1941 /* FIXME this should put processor into a mode where NMI still handled */
1942 State
.exception
= SIGQUIT
;
1943 trace_output (OP_NONE
);
1950 trace_input ("reti", OP_NONE
, 0);
1951 trace_output (OP_NONE
);
1953 /* Restore for NMI if only NP on, otherwise is interrupt or exception. */
1954 if ((PSW
& (PSW_NP
| PSW_EP
)) == PSW_NP
)
1970 trace_input ("trap", OP_TRAP
, 0);
1971 trace_output (OP_TRAP
);
1973 /* Trap 31 is used for simulating OS I/O functions */
1977 int save_errno
= errno
;
1980 /* Registers passed to trap 0 */
1982 #define FUNC State.regs[6] /* function number, return value */
1983 #define PARM1 State.regs[7] /* optional parm 1 */
1984 #define PARM2 State.regs[8] /* optional parm 2 */
1985 #define PARM3 State.regs[9] /* optional parm 3 */
1987 /* Registers set by trap 0 */
1989 #define RETVAL State.regs[10] /* return value */
1990 #define RETERR State.regs[11] /* return error code */
1992 /* Turn a pointer in a register into a pointer into real memory. */
1994 #define MEMPTR(x) (map (x))
1998 #if !defined(__GO32__) && !defined(_WIN32)
2003 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
),
2004 (char **)MEMPTR (PARM3
));
2007 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
), NULL
);
2016 RETVAL
= pipe (host_fd
);
2017 SW (buf
, host_fd
[0]);
2018 buf
+= sizeof(uint16
);
2019 SW (buf
, host_fd
[1]);
2027 RETVAL
= wait (&status
);
2035 RETVAL
= v850_callback
->read (v850_callback
, PARM1
, MEMPTR (PARM2
),
2040 RETVAL
= (int)v850_callback
->write_stdout (v850_callback
,
2041 MEMPTR (PARM2
), PARM3
);
2043 RETVAL
= (int)v850_callback
->write (v850_callback
, PARM1
,
2044 MEMPTR (PARM2
), PARM3
);
2047 RETVAL
= v850_callback
->lseek (v850_callback
, PARM1
, PARM2
, PARM3
);
2050 RETVAL
= v850_callback
->close (v850_callback
, PARM1
);
2053 RETVAL
= v850_callback
->open (v850_callback
, MEMPTR (PARM1
), PARM2
);
2056 if ((PARM1
& 0xffff0000) == 0xdead0000 && (PARM1
& 0xffff) != 0)
2057 State
.exception
= PARM1
& 0xffff; /* get signal encoded by kill */
2058 else if (PARM1
== 0xdead)
2059 State
.exception
= SIGABRT
; /* old libraries */
2061 State
.exception
= SIG_V850_EXIT
; /* PARM1 has exit status encoded */
2064 case SYS_stat
: /* added at hmsi */
2065 /* stat system call */
2067 struct stat host_stat
;
2070 RETVAL
= stat (MEMPTR (PARM1
), &host_stat
);
2074 /* Just wild-assed guesses. */
2075 store_mem (buf
, 2, host_stat
.st_dev
);
2076 store_mem (buf
+ 2, 2, host_stat
.st_ino
);
2077 store_mem (buf
+ 4, 4, host_stat
.st_mode
);
2078 store_mem (buf
+ 8, 2, host_stat
.st_nlink
);
2079 store_mem (buf
+ 10, 2, host_stat
.st_uid
);
2080 store_mem (buf
+ 12, 2, host_stat
.st_gid
);
2081 store_mem (buf
+ 14, 2, host_stat
.st_rdev
);
2082 store_mem (buf
+ 16, 4, host_stat
.st_size
);
2083 store_mem (buf
+ 20, 4, host_stat
.st_atime
);
2084 store_mem (buf
+ 28, 4, host_stat
.st_mtime
);
2085 store_mem (buf
+ 36, 4, host_stat
.st_ctime
);
2090 RETVAL
= chown (MEMPTR (PARM1
), PARM2
, PARM3
);
2093 RETVAL
= chmod (MEMPTR (PARM1
), PARM2
);
2098 RETVAL
= time (&now
);
2099 store_mem (PARM1
, 4, now
);
2105 RETVAL
= times (&tms
);
2106 store_mem (PARM1
, 4, tms
.tms_utime
);
2107 store_mem (PARM1
+ 4, 4, tms
.tms_stime
);
2108 store_mem (PARM1
+ 8, 4, tms
.tms_cutime
);
2109 store_mem (PARM1
+ 12, 4, tms
.tms_cstime
);
2112 case SYS_gettimeofday
:
2116 RETVAL
= gettimeofday (&t
, &tz
);
2117 store_mem (PARM1
, 4, t
.tv_sec
);
2118 store_mem (PARM1
+ 4, 4, t
.tv_usec
);
2119 store_mem (PARM2
, 4, tz
.tz_minuteswest
);
2120 store_mem (PARM2
+ 4, 4, tz
.tz_dsttime
);
2124 /* Cast the second argument to void *, to avoid type mismatch
2125 if a prototype is present. */
2126 RETVAL
= utime (MEMPTR (PARM1
), (void *) MEMPTR (PARM2
));
2135 { /* Trap 0 -> 30 */
2140 ECR
|= 0x40 + OP
[0];
2141 /* Flag that we are now doing exception processing. */
2142 PSW
|= PSW_EP
| PSW_ID
;
2143 PC
= ((OP
[0] < 0x10) ? 0x40 : 0x50) - 4;
2153 trace_input ("ldsr", OP_LDSR
, 0);
2154 op0
= State
.regs
[OP
[0]];
2155 State
.sregs
[OP
[1]] = op0
;
2156 trace_output (OP_LDSR
);
2165 trace_input ("stsr", OP_STSR
, 0);
2166 op0
= State
.sregs
[OP
[1]];
2167 State
.regs
[OP
[0]] = op0
;
2168 trace_output (OP_STSR
);
This page took 0.072654 seconds and 5 git commands to generate.